SAMD/L: Change ordering of some initialization steps to match Atmel sample code. Add Errate 13134 support. SAML wait states changed to 1. Sample code is using 0

arch/arm/src/samdl/chip/saml_nvmctrl.h

@@ -110,7 +110,6 @@
 #  define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS    (0 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power on first access */
 #  define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT   (1 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power when exit sleep */
 #  define NVMCTRL_CTRLB_SLEEPPRM_DISABLED        (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Auto power reduction disabled */
-
 #define NVMCTRL_CTRLB_READMODE_SHIFT (16)      /* Bits 16-17: NVMCTRL Read Mode */
 #define NVMCTRL_CTRLB_READMODE_MASK  (3 << NVMCTRL_CTRLB_READMODE_SHIFT)
 #  define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (0 << NVMCTRL_CTRLB_READMODE_SHIFT) /* No extra wait states on miss */

arch/arm/src/samdl/sam_start.c

@@ -114,12 +114,6 @@ void __start(void)
   const uint32_t *src;
   uint32_t *dest;
 
-  /* Configure the uart so that we can get debug output as soon as possible */
-
-  sam_clockconfig();
-  sam_lowsetup();
-  showprogress('A');
-
   /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
    * certain that there are no issues with the state of global variables.
    */
@@ -129,8 +123,6 @@ void __start(void)
       *dest++ = 0;
     }
 
-  showprogress('B');
-
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the
@@ -142,14 +134,21 @@ void __start(void)
       *dest++ = *src++;
     }
 
-  showprogress('C');
+  /* Configure basic clocking */
+
+  sam_clockconfig();
+
+  /* Configure the uart early so that we can get debug output as soon as possible */
+
+  sam_lowsetup();
+  showprogress('A');
 
   /* Perform early serial initialization */
 
 #ifdef USE_EARLYSERIALINIT
   up_earlyserialinit();
 #endif
-  showprogress('D');
+  showprogress('B');
 
   /* For the case of the separate user-/kernel-space build, perform whatever
    * platform specific initialization of the user memory is required.
@@ -159,13 +158,13 @@ void __start(void)
 
 #ifdef CONFIG_BUILD_PROTECTED
   sam_userspace();
-  showprogress('E');
+  showprogress('C');
 #endif
 
   /* Initialize onboard resources */
 
   sam_boardinitialize();
-  showprogress('F');
+  showprogress('D');
 
   /* Then start NuttX */
 

arch/arm/src/samdl/saml_clockconfig.c

@@ -323,7 +323,14 @@ static inline void sam_flash_waitstates(void)
 {
   uint32_t regval;
 
+  /* Errate 13134: Correct the default value of the NVMCTRL.CTRLB.MANW bit */
+
   regval  = getreg32(SAM_NVMCTRL_CTRLB);
+  regval |= NVMCTRL_CTRLB_MANW;
+  putreg32(regval, SAM_NVMCTRL_CTRLB);
+
+  /* Set the configured number of flash wait states */
+
   regval &= ~NVMCTRL_CTRLB_RWS_MASK;
   regval |= NVMCTRL_CTRLB_RWS(BOARD_FLASH_WAITSTATES);
   putreg32(regval, SAM_NVMCTRL_CTRLB);

configs/saml21-xplained/include/board.h

@@ -392,6 +392,7 @@
 
 /* FLASH wait states
  *
+ * REVISIT: These values come from the SAMD20
  * Vdd Range     Wait states    Maximum Operating Frequency
  * ------------- -------------- ---------------------------
  * 1.62V to 2.7V  0             14 MHz
@@ -402,10 +403,10 @@
  *                1             48 MHz
  */
 
-#if 0 /* REVISIT -- should not be necessary */
-#  define BOARD_FLASH_WAITSTATES     1
+#if 0 /* REVISIT -- Sample code is running with zero wait states */
+#  define BOARD_FLASH_WAITSTATES     0
 #else
-#  define BOARD_FLASH_WAITSTATES     2
+#  define BOARD_FLASH_WAITSTATES     1
 #endif
 
 /* SERCOM definitions ***************************************************************/