diff --git a/arch/z80/src/ez80/ez80_restorecontext.asm b/arch/z80/src/ez80/ez80_restorecontext.asm
index 443ea0c723..1785ddb174 100644
--- a/arch/z80/src/ez80/ez80_restorecontext.asm
+++ b/arch/z80/src/ez80/ez80_restorecontext.asm
@@ -99,7 +99,7 @@ _ez80_restorecontext:
 	; Restore interrupt state
 
 	ex	af, af'			; Recover interrupt state
-	jp	po, noinrestore		; No parity, IFF2=0, means disabled
+	jp	po, noinrestore		; Odd parity, IFF2=0, means disabled
 	ex	af, af'			; Restore AF (before enabling interrupts)
 	ei				; yes.. Enable interrupts
 	ret				; and return
diff --git a/arch/z80/src/ez80/ez80_saveusercontext.asm b/arch/z80/src/ez80/ez80_saveusercontext.asm
index 002fb11353..4a034dc21a 100644
--- a/arch/z80/src/ez80/ez80_saveusercontext.asm
+++ b/arch/z80/src/ez80/ez80_saveusercontext.asm
@@ -122,7 +122,7 @@ _ez80_saveusercontext:
 
 	; Save the current interrupt state at offset 0
 
-	ld	a, i			; Get interrupt state
+	ld	a, i			; Get interrupt state in parity bit
 	push	af
 	pop	hl
 	ld	(iy + XCPT_I), hl	; Index 0: I w/interrupt state in parity/overflow
diff --git a/arch/z80/src/ez80/ez80_timerisr.c b/arch/z80/src/ez80/ez80_timerisr.c
index 65e728f48f..51eb90ebe4 100644
--- a/arch/z80/src/ez80/ez80_timerisr.c
+++ b/arch/z80/src/ez80/ez80_timerisr.c
@@ -76,7 +76,7 @@
 
 int up_timerisr(int irq, chipreg_t *regs)
 {
-  ubyte reg;
+  volatile ubyte reg;
 
   /* Read the appropropriate timer0 registr to clear the interrupt */
   
@@ -116,7 +116,7 @@ void up_timerinit(void)
   ubyte  reg;
 
   /* Disable the timer */
-  
+
   outp(EZ80_TMR0_CTL, 0x00);
 
   /* Attach system timer interrupts */