simplification
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2878 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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0068ca76f4
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6c291c05a2
@ -131,6 +131,8 @@
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* table.
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*/
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#define PG_L1_LOCKED_PADDR (PGTABLE_BASE_PADDR + ((PG_LOCKED_VBASE >> 20) << 2))
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#define PG_L1_LOCKED_VADDR (PGTABLE_BASE_VADDR + ((PG_LOCKED_VBASE >> 20) << 2))
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#define PG_L2_LOCKED_PADDR PG_L2_BASE_PADDR
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#define PG_L2_LOCKED_VADDR PG_L2_BASE_VADDR
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#define PG_L2_LOCKED_SIZE (4*CONFIG_PAGING_NLOCKED)
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@ -138,19 +140,25 @@
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/* We position the paged region PTEs immediately after the locked
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* region PTEs.
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*/
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#define PG_L1_PAGED_PADDR (PGTABLE_BASE_PADDR + ((PG_PAGED_VBASE >> 20) << 2))
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#define PG_L1_PAGED_VADDR (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2))
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#define PG_L2_PAGED_PADDR (PG_L2_BASE_PADDR + PG_L2_LOCKED_SIZE)
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#define PG_L2_PAGED_VADDR (PG_L2_BASE_VADDR + PG_L2_LOCKED_SIZE)
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#define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NPPAGED)
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/* This describes the overall text region */
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#define PG_L1_TEXT_PADDR PG_L1_LOCKED_PADDR
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#define PG_L1_TEXT_VADDR PG_L1_LOCKED_VADDR
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#define PG_L2_TEXT_PADDR PG_L2_LOCKED_PADDR
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#define PG_L2_TEXT_VADDR PG_L2_LOCKED_VADDR
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#define PG_L2_TEXT_SIZE (PG_L2_LOCKED_SIZE + PG_L2_PAGED_SIZE)
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/* We position the data section PTEs just after the text region PTE's */
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#define PG_L1_DATA_PADDR (PGTABLE_BASE_PADDR + ((PG_DATA_VBASE >> 20) << 2))
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#define PG_L1_DATA_VADDR (PGTABLE_BASE_VADDR + ((PG_DATA_VBASE >> 20) << 2))
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#define PG_L2_DATA_PADDR (PG_L2_BASE_PADDR + PG_L2_TEXT_SIZE)
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#define PG_L2_DATA_VADDR (PG_L2_BASE_VADDR + PG_L2_TEXT_SIZE)
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#define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES)
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@ -161,6 +169,8 @@
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*/
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#define PG_PGTABLE_NPAGES (PGTABLE_SIZE >> PAGESHIFT)
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#define PG_L1_PGTABLE_PADDR (PGTABLE_BASE_PADDR + ((PGTABLE_BASE_VADDR >> 20) << 2))
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#define PG_L1_PGTABLE_VADDR (PGTABLE_BASE_VADDR + ((PGTABLE_BASE_VADDR >> 20) << 2))
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#define PG_L2_PGTABLE_PADDR (PG_L2_DATA_PADDR + PG_L2_DATA_SIZE)
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#define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + PG_L2_DATA_SIZE)
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#define PG_L2_PGTABLE_SIZE (4*PG_DATA_NPAGES)
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@ -368,12 +378,10 @@
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* macro is used when CONFIG_PAGING is enable. This case, it is used as
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* follows:
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*
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* ldr r0, =PGTABLE_BASE_PADDR <-- Address in L1 table
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* ldr r1, =PG_LOCKED_VBASE <-- Virtual address of region
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* pg_l1addr r0, r1, r0
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* ldr r1, =PG_LOCKED_PBASE <-- Physical address of region
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* ldr r1, =(CONFIG_PAGING_NLOCKED+CONFIG_PAGING_NVPAGED) <-- number of pages
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* ldr r3, =MMU_FLAGS <-- L1 MMU flags
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* ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table
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* ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table
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* ldr r2, =PG_PGTABLE_NPAGES <-- Number of pages
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* ldr r3, =MMU_L1_PGTABFLAGS <-- L1 MMU flags
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* pg_l1span r0, r1, r2, r3, r4
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*
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* Inputs (unmodified unless noted):
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@ -431,45 +439,6 @@
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bgt 1b
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.endm
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/****************************************************************************
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* Name: pg_l1addr
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*
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* Description:
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* Given the start of an L1 table and a virtual address, return the offset
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* address into the L1 table for that address.
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*
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* ldr r0, =PGTABLE_BASE_PADDR
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* ldr r1, =PG_LOCKED_VBASE
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* pg_l1addr r0, r1, r0
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*
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* Inputs (unmodified unless noted):
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* l1 - The physical or virtual address of the start of the L1 table
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* vaddr - The virtual address of the start of the region to span. Must
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* be aligned to 1Mb section boundaries (modified)
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* npages - Number of pages to required to span that memory region (modified)
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* mmuflags - L1 MMU flags to use
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*
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* Scratch registers (modified): vaddr
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*
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* Return:
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* The offset L1 table address is returned in result.
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*
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* Assumptions:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_PAGING
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.macro pg_l1addr, l1, vaddr, result
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/* Get result = the L1 table address coresponding to a virtual
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* address.
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*/
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lsr \vaddr, \vaddr, #20
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add \result, \l1, \vaddr, lsl #2
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.endm
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#endif /* CONFIG_PAGING */
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#endif /* __ASSEMBLY__ */
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@ -191,9 +191,8 @@ __start:
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*/
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adr r0, .Ltxtspan
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ldmia r0, {r0, r1, r2, r3, r4}
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pg_l1addr r0, r1, r0
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pg_l1span r0, r2, r3, r4, r1
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ldmia r0, {r0, r1, r2, r3}
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pg_l1span r0, r1, r2, r3, r4
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/* Then populate the L2 table for the locked text region only. */
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@ -206,9 +205,8 @@ __start:
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*/
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adr r0, .Lptabspan
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ldmia r0, {r0, r1, r2, r3, r4}
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pg_l1addr r0, r1, r0
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pg_l1span r0, r2, r3, r4, r1
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ldmia r0, {r0, r1, r2, r3}
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pg_l1span r0, r1, r2, r3, r4
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/* Then populate the L2 table. */
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@ -352,8 +350,7 @@ __start:
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#ifdef CONFIG_PAGING
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.Ltxtspan:
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.long PGTABLE_BASE_PADDR /* Physical address of L1 table */
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.long PG_L2_TEXT_VADDR /* Virtual address of the L2 page table */
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.long PG_L1_TEXT_PADDR /* Physical address in the L1 table */
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.long PG_L2_TEXT_PADDR /* Physical address of the L2 page table */
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.long PG_TEXT_NVPAGES /* Total (virtual) text pages to be mapped */
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.long MMU_L1_TEXTFLAGS /* L1 MMU flags to use */
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@ -365,8 +362,7 @@ __start:
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.long MMU_L2_TEXTFLAGS /* L2 MMU flags to use */
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.Lptabspan:
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.long PGTABLE_BASE_PADDR /* Physical address of L1 table */
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.long PG_L2_PGTABLE_VADDR /* Virtual address of the L2 page table */
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.long PG_L1_PGTABLE_PADDR /* Physical address in the L1 table */
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.long PG_L2_PGTABLE_PADDR /* Physical address of the L2 page table */
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.long PG_PGTABLE_NPAGES /* Total mapped page table pages */
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.long MMU_L1_PGTABFLAGS /* L1 MMU flags to use */
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@ -407,9 +403,8 @@ __start:
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/* Populate the L1 table for the data regions */
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adr r0, .Ldataspan
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ldmia r0, {r0, r1, r2, r3, r4}
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pg_l1addr r0, r1, r0
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pg_l1span r0, r2, r3, r4, r1
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ldmia r0, {r0, r1, r2, r3}
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pg_l1span r0, r1, r2, r3, r4
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/* Populate the L2 table for the data region */
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@ -513,8 +508,7 @@ __start:
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#ifdef CONFIG_PAGING
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.Ldataspan:
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.long PGTABLE_BASE_VADDR /* Virtual address of the L1 table */
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.long PG_L2_DATA_VADDR /* Virtual address of the L2 page table */
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.long PG_L1_DATA_VADDR /* Virtual address in the L1 table */
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.long PG_L2_DATA_PADDR /* Physical address of the L2 page table */
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.long PG_DATA_NPAGED /* Number of pages in the data region */
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.long MMU_L1_DATAFLAGS /* L1 MMU flags to use */
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