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This commit is contained in:
Gregory Nutt 2016-01-15 10:55:58 -06:00
parent aea0c7c3ef
commit 6c2cd3edee
8 changed files with 3036 additions and 3036 deletions
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2
arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h
View File

@ -110,7 +110,7 @@
#define LPC43_SCT_BASE (LPC43_AHBPERIPH_BASE + 0x00000000)
#define LPC43_DMA_BASE (LPC43_AHBPERIPH_BASE + 0x00002000)
#define LPC43_SPIFI_BASE (LPC43_AHBPERIPH_BASE + 0x00003000)
#define LPC43_SPIFI_BASE (LPC43_AHBPERIPH_BASE + 0x00003000)
#define LPC43_SDMMC_BASE (LPC43_AHBPERIPH_BASE + 0x00004000)
#define LPC43_EMC_BASE (LPC43_AHBPERIPH_BASE + 0x00005000)
#define LPC43_USB0_BASE (LPC43_AHBPERIPH_BASE + 0x00006000)

36
arch/arm/src/lpc43xx/chip/lpc43_cgu.h
View File

@ -577,26 +577,26 @@
/* Output stage 9 control register (BASE_APB1_CLK, BASE_APB3_CLK) */
/* NOTE: Clocks 4-19 are identical */
#define BASE_APB_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
#define BASE_APB_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
/* Bits 1-10: Reserved */
#define BASE_APB_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
#define BASE_APB_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
/* Bits 12-23: Reserved */
#define BASE_APB_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
#define BASE_APB_CLK_CLKSEL_MASK (31 << BASE_APB_CLK_CLKSEL_SHIFT)
# define BASE_APB_CLKSEL_32KHZOSC (0 << BASE_APB_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */
# define BASE_APB_CLKSEL_IRC (1 << BASE_APB_CLK_CLKSEL_SHIFT) /* IRC (default) */
# define BASE_APB_CLKSEL_ENET_RXCLK (2 << BASE_APB_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */
# define BASE_APB_CLKSEL_ENET_TXCLK (3 << BASE_APB_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */
# define BASE_APB_CLKSEL_GPCLKIN (4 << BASE_APB_CLK_CLKSEL_SHIFT) /* GP_CLKIN */
# define BASE_APB_CLKSEL_XTAL (6 << BASE_APB_CLK_CLKSEL_SHIFT) /* Crystal oscillator */
# define BASE_APB_CLKSEL_PLL0AUDIO (8 << BASE_APB_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */
# define BASE_APB_CLKSEL_PLL1 (9 << BASE_APB_CLK_CLKSEL_SHIFT) /* PLL1 */
# define BASE_APB_CLKSEL_IDIVA (12 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVA */
# define BASE_APB_CLKSEL_IDIVB (13 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVB */
# define BASE_APB_CLKSEL_IDIVC (14 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVC */
# define BASE_APB_CLKSEL_IDIVD (15 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVD */
# define BASE_APB_CLKSEL_IDIVE (16 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVE */
/* Bits 29-31: Reserved */
#define BASE_APB_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
#define BASE_APB_CLK_CLKSEL_MASK (31 << BASE_APB_CLK_CLKSEL_SHIFT)
# define BASE_APB_CLKSEL_32KHZOSC (0 << BASE_APB_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */
# define BASE_APB_CLKSEL_IRC (1 << BASE_APB_CLK_CLKSEL_SHIFT) /* IRC (default) */
# define BASE_APB_CLKSEL_ENET_RXCLK (2 << BASE_APB_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */
# define BASE_APB_CLKSEL_ENET_TXCLK (3 << BASE_APB_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */
# define BASE_APB_CLKSEL_GPCLKIN (4 << BASE_APB_CLK_CLKSEL_SHIFT) /* GP_CLKIN */
# define BASE_APB_CLKSEL_XTAL (6 << BASE_APB_CLK_CLKSEL_SHIFT) /* Crystal oscillator */
# define BASE_APB_CLKSEL_PLL0AUDIO (8 << BASE_APB_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */
# define BASE_APB_CLKSEL_PLL1 (9 << BASE_APB_CLK_CLKSEL_SHIFT) /* PLL1 */
# define BASE_APB_CLKSEL_IDIVA (12 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVA */
# define BASE_APB_CLKSEL_IDIVB (13 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVB */
# define BASE_APB_CLKSEL_IDIVC (14 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVC */
# define BASE_APB_CLKSEL_IDIVD (15 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVD */
# define BASE_APB_CLKSEL_IDIVE (16 << BASE_APB_CLK_CLKSEL_SHIFT) /* IDIVE */
/* Bits 29-31: Reserved */
/* Output stage 11 control register (BASE_LCD_CLK) */
/* NOTE: Clocks 4-19 are identical */

86
arch/arm/src/lpc43xx/chip/lpc43_spifi.h
View File

@ -71,68 +71,65 @@
* Pre-processor Definitions
****************************************************************************/
/* Register addresses *******************************************************/
/* Register addresses ***************************************************************/
#define LPC43_SPIFI_CTRL_OFFSET 0x000
#define LPC43_SPIFI_CMD_OFFSET 0x004
#define LPC43_SPIFI_ADDR_OFFSET 0x008
#define LPC43_SPIFI_IDATA_OFFSET 0x00C
#define LPC43_SPIFI_CLIMIT_OFFSET 0x010
#define LPC43_SPIFI_DATA_OFFSET 0x014
#define LPC43_SPIFI_MCMD_OFFSET 0x018
#define LPC43_SPIFI_STAT_OFFSET 0x01C
#define LPC43_SPIFI_CTRL (LPC43_SPIFI_BASE+LPC43_SPIFI_CTRL_OFFSET)
#define LPC43_SPIFI_CMD (LPC43_SPIFI_BASE+LPC43_SPIFI_CMD_OFFSET)
#define LPC43_SPIFI_ADDR (LPC43_SPIFI_BASE+LPC43_SPIFI_ADDR_OFFSET)
#define LPC43_SPIFI_IDATA (LPC43_SPIFI_BASE+LPC43_SPIFI_IDATA_OFFSET)
#define LPC43_SPIFI_CLIMIT (LPC43_SPIFI_BASE+LPC43_SPIFI_CLIMIT_OFFSET)
#define LPC43_SPIFI_DATA (LPC43_SPIFI_BASE+LPC43_SPIFI_DATA_OFFSET)
#define LPC43_SPIFI_MCMD (LPC43_SPIFI_BASE+LPC43_SPIFI_MCMD_OFFSET)
#define LPC43_SPIFI_STAT (LPC43_SPIFI_BASE+LPC43_SPIFI_STAT_OFFSET)
#define LPC43_SPIFI_CTRL_OFFSET 0x000
#define LPC43_SPIFI_CMD_OFFSET 0x004
#define LPC43_SPIFI_ADDR_OFFSET 0x008
#define LPC43_SPIFI_IDATA_OFFSET 0x00c
#define LPC43_SPIFI_CLIMIT_OFFSET 0x010
#define LPC43_SPIFI_DATA_OFFSET 0x014
#define LPC43_SPIFI_MCMD_OFFSET 0x018
#define LPC43_SPIFI_STAT_OFFSET 0x01c
#define LPC43_SPIFI_CTRL (LPC43_SPIFI_BASE+LPC43_SPIFI_CTRL_OFFSET)
#define LPC43_SPIFI_CMD (LPC43_SPIFI_BASE+LPC43_SPIFI_CMD_OFFSET)
#define LPC43_SPIFI_ADDR (LPC43_SPIFI_BASE+LPC43_SPIFI_ADDR_OFFSET)
#define LPC43_SPIFI_IDATA (LPC43_SPIFI_BASE+LPC43_SPIFI_IDATA_OFFSET)
#define LPC43_SPIFI_CLIMIT (LPC43_SPIFI_BASE+LPC43_SPIFI_CLIMIT_OFFSET)
#define LPC43_SPIFI_DATA (LPC43_SPIFI_BASE+LPC43_SPIFI_DATA_OFFSET)
#define LPC43_SPIFI_MCMD (LPC43_SPIFI_BASE+LPC43_SPIFI_MCMD_OFFSET)
#define LPC43_SPIFI_STAT (LPC43_SPIFI_BASE+LPC43_SPIFI_STAT_OFFSET)
/* The largest protection block of any serial flash that the ROM driver
* can handle
*/
#define SPIFI_LONGEST_PROTBLOCK 68
#define SPIFI_LONGEST_PROTBLOCK 68
/* Protection flag bit definitions */
#define SPIFI_RWPROT (1 << 0)
#define SPIFI_RWPROT (1 << 0)
/* Instruction classes for wait_busy */
#define SPIFI_STAT_INST 0
#define SPIFI_BLOCK_ERASE 1
#define SPIFI_PROG_INST 2
#define SPIFI_CHIP_ERASE 3
#define SPIFI_STAT_INST 0
#define SPIFI_BLOCK_ERASE 1
#define SPIFI_PROG_INST 2
#define SPIFI_CHIP_ERASE 3
/* Bit definitions in options operands (MODE3, RCVCLK, and FULLCLK
* have the same relationship as in the Control register)
*/
#define S_MODE3 (1 << 0)
#define S_MODE0 (0)
#define S_MINIMAL (1 << 1)
#define S_MAXIMAL (0)
#define S_FORCE_ERASE (1 << 2)
#define S_ERASE_NOT_REQD (1 << 3)
#define S_CALLER_ERASE (1 << 3)
#define S_ERASE_AS_REQD (0)
#define S_VERIFY_PROG (1 << 4)
#define S_VERIFY_ERASE (1 << 5)
#define S_NO_VERIFY (0)
#define S_FULLCLK (1 << 6)
#define S_HALFCLK (0)
#define S_RCVCLK (1 << 7)
#define S_INTCLK (0)
#define S_DUAL (1 << 8)
#define S_CALLER_PROT (1 << 9)
#define S_DRIVER_PROT (0)
#define S_MODE3 (1 << 0)
#define S_MODE0 (0)
#define S_MINIMAL (1 << 1)
#define S_MAXIMAL (0)
#define S_FORCE_ERASE (1 << 2)
#define S_ERASE_NOT_REQD (1 << 3)
#define S_CALLER_ERASE (1 << 3)
#define S_ERASE_AS_REQD (0)
#define S_VERIFY_PROG (1 << 4)
#define S_VERIFY_ERASE (1 << 5)
#define S_NO_VERIFY (0)
#define S_FULLCLK (1 << 6)
#define S_HALFCLK (0)
#define S_RCVCLK (1 << 7)
#define S_INTCLK (0)
#define S_DUAL (1 << 8)
#define S_CALLER_PROT (1 << 9)
#define S_DRIVER_PROT (0)
/* The length of a standard program command is 256 on all devices */
@ -296,4 +293,3 @@ int32_t spifi_erase(struct spifi_dev_s *dev,
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPIFI_H */

163
arch/arm/src/lpc43xx/lpc43_adc.c
View File

@ -1,13 +1,18 @@
/************************************************************************************
* arch/arm/src/lpc43xx/lpc43_adc.c
*
* Copyright (C) 2011 Li Zhuoyi. All rights reserved.
* Copyright(C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Ported from from the LPC17 version:
*
* Copyright(C) 2011 Li Zhuoyi. All rights reserved.
* Author: Li Zhuoyi <lzyy.cn@gmail.com>
* History: 0.1 2011-08-05 initial version
*
* This file is a part of NuttX:
*
* Copyright (C) 2010, 2015 Gregory Nutt. All rights reserved.
* Copyright(C) 2010-2012, 2015 Gregory Nutt. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -28,11 +33,11 @@
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
@ -70,12 +75,12 @@
#include <chip/lpc43_timer.h>
#include "lpc43_pinconfig.h"
#if defined(CONFIG_LPC43_ADC0) /* TODO ADC1 */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_ADC0_MASK
#define CONFIG_ADC0_MASK 0x01
#endif
@ -84,17 +89,18 @@
#endif
#define LPC43_ADC_MAX_FREQUENCY 4500000
#define LPC43_ADC_MIN_FREQUENCY (BOARD_ABP3_FREQUENCY/256)
#define LPC43_ADC_MIN_FREQUENCY(BOARD_ABP3_FREQUENCY/256)
#if defined(CONFIG_ADC0_USE_TIMER) && CONFIG_ADC0_FREQ == 0
# error "set CONFIG_ADC0_FREQ!=0 if CONFIG_ADC0_USE_TIMER"
# error "Set CONFIG_ADC0_FREQ != 0 if CONFIG_ADC0_USE_TIMER"
#endif
#ifndef CONFIG_ADC0_USE_TIMER
# if (CONFIG_ADC0_FREQ != 0 && (CONFIG_ADC0_FREQ > LPC43_ADC_MAX_FREQUENCY || CONFIG_ADC0_FREQ < LPC43_ADC_MIN_FREQUENCY))
# if (CONFIG_ADC0_FREQ != 0 &&(CONFIG_ADC0_FREQ > LPC43_ADC_MAX_FREQUENCY || \
CONFIG_ADC0_FREQ < LPC43_ADC_MIN_FREQUENCY))
# error "ADC0 sample rate can't be grater than LPC43_ADC_MAX_FREQUENCY or less than LPC43_ADC_MIN_FREQUENCY"
# endif
#define CONFIG_ADC0_USE_TIMER 0
# define CONFIG_ADC0_USE_TIMER 0
#endif
/****************************************************************************
@ -107,7 +113,7 @@ struct up_dev_s
uint8_t mask_int;
uint32_t freq;
int irq;
bool timer;
bool timer;
bool m_ch;
};
@ -144,7 +150,7 @@ static struct up_dev_s g_adcpriv =
.mask_int = CONFIG_ADC0_MASK,
.irq = LPC43M4_IRQ_ADC0,
.timer = CONFIG_ADC0_USE_TIMER,
.m_ch = ( CONFIG_ADC0_MASK & (CONFIG_ADC0_MASK-1) )?true:false
.m_ch = (CONFIG_ADC0_MASK & (CONFIG_ADC0_MASK - 1)) ? true : false
};
static struct adc_dev_s g_adcdev =
@ -172,11 +178,11 @@ static void adc_reset(FAR struct adc_dev_s *dev)
irqstate_t flags;
uint32_t regval;
if ( priv->m_ch ) /* calc MSB */
if (priv->m_ch) /* calc MSB */
{
priv->mask_int |= (priv->mask_int >> 1);
priv->mask_int |= (priv->mask_int >> 2);
priv->mask_int |= (priv->mask_int >> 4);
priv->mask_int |= (priv->mask_int >> 1);
priv->mask_int |= (priv->mask_int >> 2);
priv->mask_int |= (priv->mask_int >> 4);
priv->mask_int &= ~(priv->mask_int >> 1);
}
@ -188,58 +194,55 @@ static void adc_reset(FAR struct adc_dev_s *dev)
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_APB3_ADC0_CFG);
/* Calc config value*/
/* calc config value*/
regval = ADC_CR_PDN;
regval = ADC_CR_PDN;
regval |= priv->mask;
if (priv->freq != 0 )
if (priv->freq != 0)
{
if (priv->timer)
{
{
/* Start adc on timer */
/* start adc on timer */
regval |= ADC_CR_START_CTOUT8;
regval |= ADC_CR_START_CTOUT8;
/* enable timer out in creg */
/* enable timer out in creg*/
uint32_t regval_timer = getreg32(LPC43_CREG6);
regval_timer &= ~CREG6_CTOUTCTRL;
putreg32(regval_timer, LPC43_CREG6);
uint32_t regval_timer = getreg32(LPC43_CREG6);
regval_timer &= ~CREG6_CTOUTCTRL;
putreg32(regval_timer, LPC43_CREG6);
/* Enable synch timer 2 match 0 to adc */
/* enable synch timer 2 match 0 to adc*/
putreg32(GIMA_EDGE | GIMA_SYNCH | GIMA_ADC1_SELECT_T2MAT0, LPC43_GIMA_ADCSTART1);
putreg32( GIMA_EDGE | GIMA_SYNCH | GIMA_ADC1_SELECT_T2MAT0, LPC43_GIMA_ADCSTART1);
/* Power on */
/* power on */
regval_timer = getreg32(LPC43_CCU1_M4_TIMER2_CFG);
regval_timer |= CCU_CLK_CFG_RUN;
putreg32(regval_timer, LPC43_CCU1_M4_TIMER2_CFG);
regval_timer = getreg32(LPC43_CCU1_M4_TIMER2_CFG);
regval_timer |= CCU_CLK_CFG_RUN;
putreg32(regval_timer, LPC43_CCU1_M4_TIMER2_CFG);
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_TCR_OFFSET); /* disable */
putreg32(TMR_MCR_MR0R, LPC43_TIMER2_BASE+LPC43_TMR_MCR_OFFSET); /* reset on match only*/
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_CCR_OFFSET); /* do not use capture */
putreg32(TMR_EMR_EMC0_SET, LPC43_TIMER2_BASE+LPC43_TMR_EMR_OFFSET); /* external match */
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_CTCR_OFFSET); /* counter/timer mode */
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_TCR_OFFSET); /* disable */
putreg32(TMR_MCR_MR0R, LPC43_TIMER2_BASE+LPC43_TMR_MCR_OFFSET); /* reset on match only */
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_CCR_OFFSET); /* do not use capture */
putreg32(TMR_EMR_EMC0_SET, LPC43_TIMER2_BASE+LPC43_TMR_EMR_OFFSET); /* external match */
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_CTCR_OFFSET); /* counter/timer mode */
putreg32(LPC43_CCLK/priv->freq/2-1, LPC43_TIMER2_BASE+LPC43_TMR_PR_OFFSET); /* set clock, divide by 2 - bug in chip */
putreg32(LPC43_CCLK/priv->freq/2-1, LPC43_TIMER2_BASE+LPC43_TMR_PR_OFFSET); /* set clock, divide by 2 - bug in chip */
putreg32(1, LPC43_TMR2_MR0); /* set match on 1*/
}
putreg32(1, LPC43_TMR2_MR0); /* set match on 1*/
}
else
{
uint32_t clkdiv = BOARD_ABP3_FREQUENCY/priv->freq + (BOARD_ABP3_FREQUENCY%priv->freq!=0) - 1;
regval |= clkdiv<<ADC_CR_CLKDIV_SHIFT;
}
{
uint32_t clkdiv = BOARD_ABP3_FREQUENCY/priv->freq +(BOARD_ABP3_FREQUENCY%priv->freq != 0) - 1;
regval |= clkdiv<<ADC_CR_CLKDIV_SHIFT;
}
}
putreg32(regval, LPC43_ADC0_CR);
/* do pin configuration if defined */
/* Do pin configuration if defined */
#ifdef PINCONF_ADC0_C0
if ((priv->mask & 0x01) != 0)
@ -366,32 +369,31 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
{
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
if (enable)
{
putreg32(priv->mask_int, LPC43_ADC0_INTEN);
if (priv->timer)
{
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_PC_OFFSET); /* reset prescale counter */
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_TC_OFFSET); /* reset timer counter */
putreg32(TMR_TCR_EN, LPC43_TIMER2_BASE+LPC43_TMR_TCR_OFFSET); /* enable the timer */
}
{
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_PC_OFFSET); /* reset prescale counter */
putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_TC_OFFSET); /* reset timer counter */
putreg32(TMR_TCR_EN, LPC43_TIMER2_BASE+LPC43_TMR_TCR_OFFSET); /* enable the timer */
}
else
{
uint32_t regval = getreg32(LPC43_ADC0_CR);
{
uint32_t regval = getreg32(LPC43_ADC0_CR);
if(priv->freq == 0 && !priv->m_ch)
{
regval |= ADC_CR_START_NOW;
}
else
{
regval |= ADC_CR_BURST;
}
if (priv->freq == 0 && !priv->m_ch)
{
regval |= ADC_CR_START_NOW;
}
else
{
regval |= ADC_CR_BURST;
}
putreg32(regval, LPC43_ADC0_CR);
}
putreg32(regval, LPC43_ADC0_CR);
}
}
else
{
@ -427,32 +429,31 @@ static int adc_interrupt(int irq, void *context)
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
uint32_t regval;
int i;
if( priv->timer)
if (priv->timer)
{
putreg32(TMR_EMR_EMC0_SET, LPC43_TIMER2_BASE+LPC43_TMR_EMR_OFFSET); /* put match to low */
}
else
{
if (priv->freq == 0 && priv->m_ch ) /* clear burst mode */
{
regval = getreg32(LPC43_ADC0_CR);
regval &= ~ADC_CR_BURST;
putreg32(regval, LPC43_ADC0_CR);
}
if (priv->freq == 0 && priv->m_ch) /* clear burst mode */
{
regval = getreg32(LPC43_ADC0_CR);
regval &= ~ADC_CR_BURST;
putreg32(regval, LPC43_ADC0_CR);
}
}
/* Read data, clear interrupt by this */
/* read data, clear interrupt by this */
int i;
for (i = 0; i < 8; i++)
for(i = 0; i < 8; i++)
{
if (priv->mask & 1<<i)
{
regval = getreg32(LPC43_ADC0_DR(i));
adc_receive(&g_adcdev, i, (regval&ADC_DR_VVREF_MASK)>>ADC_DR_VVREF_SHIFT);
}
if (priv->mask & (1 << i))
{
regval = getreg32(LPC43_ADC0_DR(i));
adc_receive(&g_adcdev, i,(regval&ADC_DR_VVREF_MASK)>>ADC_DR_VVREF_SHIFT);
}
}
return OK;

1
arch/arm/src/lpc43xx/lpc43_i2c.c
View File

@ -630,7 +630,6 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev)
return OK;
}
/************************************************************************************
* Name: up_i2creset
*

2
arch/arm/src/lpc43xx/lpc43_spifi.c
View File

@ -245,7 +245,7 @@
* csHigh = ceiling(min CS high / SPIFI clock period) - 1
*
* where ceiling means round up to the next higher integer if the argument
* isn<EFBFBD>t an integer.
* isn't an integer.
*/
#define SPIFI_CSHIGH 9

48
arch/arm/src/lpc43xx/lpc43_ssp.c
View File

@ -595,19 +595,19 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF) &&
(rxpending < LPC43_SSP_FIFOSZ) && nwords)
(rxpending < LPC43_SSP_FIFOSZ) && nwords)
{
if (txbuffer)
{
if (priv->nbits > 8)
{
data = (uint32_t)*tx.p16++;
}
else
{
data = (uint32_t)*tx.p8++;
}
}
{
if (priv->nbits > 8)
{
data = (uint32_t)*tx.p16++;
}
else
{
data = (uint32_t)*tx.p8++;
}
}
ssp_putreg(priv, LPC43_SSP_DR_OFFSET, txbuffer?data:datadummy);
nwords--;
@ -621,16 +621,16 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
{
data = ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
if (rxbuffer)
{
if(priv->nbits > 8)
{
*rx.p16++ = (uint16_t)data;
}
else
{
*rx.p8++ = (uint8_t)data;
}
}
{
if(priv->nbits > 8)
{
*rx.p16++ = (uint16_t)data;
}
else
{
*rx.p8++ = (uint8_t)data;
}
}
rxpending--;
}
@ -658,7 +658,8 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
****************************************************************************/
#ifndef CONFIG_SPI_EXCHANGE
static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
size_t nwords)
{
return ssp_exchange(dev, buffer, NULL, nwords);
}
@ -683,7 +684,8 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
*
****************************************************************************/
static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
size_t nwords)
{
return ssp_exchange(dev, NULL, buffer, nwords);
}

5734
arch/arm/src/lpc43xx/lpc43_usb0dev.c
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