SAM4L: Add DFLL0 support, add logic to set the power scaling mode, add support for RAM functions

configs/sam4l-xplained/include/board.h

@@ -103,9 +103,9 @@
  */
 
 #define BOARD_DFLL0_SOURCE_OSC32K  1
-#define BOARD_FDLL0_FREQUENCY      48000000
-#define BOARD_FDLL0_MUL            (BOARD_FDLL0_FREQUENCY / BOARD_OSC32_FREQUENCY)
-#define BOARD_FDLL0_DIV            1
+#define BOARD_DFLL0_FREQUENCY      48000000
+#define BOARD_DFLL0_MUL            (BOARD_DFLL0_FREQUENCY / BOARD_OSC32_FREQUENCY)
+#define BOARD_DFLL0_DIV            1
 
 /* Phase Locked Loop configuration
  *  Fdfll = (Fclk * PLLmul) / PLLdiv

configs/sam4l-xplained/ostest/defconfig

@@ -126,6 +126,7 @@ CONFIG_ARCH_CHIP_SAM4L=y
 #
 # AT91SAM3 Peripheral Support
 #
+CONFIG_SAM_PICOCACHE=y
 # CONFIG_SAM34_DMA is not set
 # CONFIG_SAM34_NAND is not set
 # CONFIG_SAM34_HSMCI is not set
@@ -164,7 +165,8 @@ CONFIG_ARCH_IRQPRIO=y
 CONFIG_ARCH_HAVE_VFORK=y
 CONFIG_ARCH_STACKDUMP=y
 # CONFIG_ENDIAN_BIG is not set
-# CONFIG_ARCH_HAVE_RAMFUNCS is not set
+CONFIG_ARCH_HAVE_RAMFUNCS=y
+CONFIG_ARCH_RAMFUNCS=y
 CONFIG_ARCH_HAVE_RAMVECTORS=y
 # CONFIG_ARCH_RAMVECTORS is not set
 
@@ -313,6 +315,10 @@ CONFIG_USART1_BAUD=115200
 CONFIG_USART1_BITS=8
 CONFIG_USART1_PARITY=0
 CONFIG_USART1_2STOP=0
+# CONFIG_USART1_IFLOWCONTROL is not set
+# CONFIG_USART1_OFLOWCONTROL is not set
+# CONFIG_SERIAL_IFLOWCONTROL is not set
+# CONFIG_SERIAL_OFLOWCONTROL is not set
 # CONFIG_USBDEV is not set
 # CONFIG_USBHOST is not set
 # CONFIG_WIRELESS is not set

configs/sam4l-xplained/scripts/ld.script

@@ -63,8 +63,6 @@ SECTIONS
 		_etext = ABSOLUTE(.);
 	} > flash
 
-	_eronly = ABSOLUTE(.);
-
 	.data : {
 		_sdata = ABSOLUTE(.);
 		*(.data .data.*)
@@ -73,6 +71,16 @@ SECTIONS
 		_edata = ABSOLUTE(.);
 	} > sram AT > flash
 
+	_eronly = LOADADDR(.data);
+
+	.ramfunc ALIGN(4): {
+		_sramfuncs = ABSOLUTE(.);
+		*(.ramfunc  .ramfunc.*)
+		_eramfuncs = ABSOLUTE(.);
+	} > sram AT > flash
+
+	_framfuncs = LOADADDR(.ramfunc);
+
 	.ARM.extab : {
 		*(.ARM.extab*)
 	} >sram