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Squashed commit of the following:

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lpc17, sam34:  Rename some improperly scoped configuration variables; fix some duplicate configuration variable names.
    lpc11, lpc17, lc823450:  Rename some improperly scoped configuration variables; fix some duplicate configuration variable names.
    lpc11, lpc17, lpc43:  Rename some improperly scoped configuration variables; fix one duplicate configuration variable.
This commit is contained in:
Gregory Nutt 2018-07-06 09:15:57 -06:00
parent 5764d5a529
commit 6cb9f8001c
12 changed files with 170 additions and 164 deletions
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14
arch/arm/src/lc823450/lc823450_adc.c
View File

@ -79,8 +79,8 @@
#define LC823450_MAX_ADCCLK (5 * 1000 * 1000) /* Hz */
#ifndef CONFIG_ADC_NCHANNELS
# define CONFIG_ADC_NCHANNELS 6
#ifndef CONFIG_LC823450_ADC_NCHANNELS
# define CONFIG_LC823450_ADC_NCHANNELS 6
#endif
#if defined(CONFIG_DVFS) && !defined(CONFIG_ADC_POLLED)
@ -130,7 +130,7 @@ static struct lc823450_adc_inst_s *g_inst = NULL;
/* IDs to recognize each AD channel */
static const uint8_t lc823450_chanlist[CONFIG_ADC_NCHANNELS] =
static const uint8_t lc823450_chanlist[CONFIG_LC823450_ADC_NCHANNELS] =
{
0, /* Channel 0 */
1, /* Channel 1 */
@ -250,7 +250,7 @@ static void lc823450_adc_start(FAR struct lc823450_adc_inst_s *inst)
/* Setup ADC channels */
putreg32((i << rADCCTL_fADCNVCK_SHIFT) |
LC823450_ADCHST(CONFIG_ADC_NCHANNELS - 1) |
LC823450_ADCHST(CONFIG_LC823450_ADC_NCHANNELS - 1) |
rADCCTL_fADCHSCN, rADCCTL);
/* Start A/D conversion */
@ -488,7 +488,7 @@ static int lc823450_adc_ioctl(FAR struct adc_dev_s *dev, int cmd,
/* Get ADC data */
for (ch = 0; ch < CONFIG_ADC_NCHANNELS; ch++)
for (ch = 0; ch < CONFIG_LC823450_ADC_NCHANNELS; ch++)
{
val = getreg32(LC823450_ADC0DT(ch));
@ -554,7 +554,7 @@ FAR struct adc_dev_s *lc823450_adcinitialize(void)
inst->dev.ad_ops = &lc823450_adc_ops;
inst->dev.ad_priv = inst;
inst->nchannels = CONFIG_ADC_NCHANNELS;
inst->nchannels = CONFIG_LC823450_ADC_NCHANNELS;
inst->chanlist = lc823450_chanlist;
nxsem_init(&inst->sem_excl, 0, 1);
@ -634,7 +634,7 @@ int lc823450_adc_receive(FAR struct adc_dev_s *dev, FAR struct adc_msg_s *msg)
lc823450_adc_standby(0);
lc823450_adc_start(inst);
for (ch = 0; ch < CONFIG_ADC_NCHANNELS; ch++)
for (ch = 0; ch < CONFIG_LC823450_ADC_NCHANNELS; ch++)
{
msg[ch].am_channel = ch;
msg[ch].am_data = getreg32(LC823450_ADC0DT(ch));

30
arch/arm/src/lpc11xx/Kconfig
View File

@ -104,19 +104,19 @@ endmenu
menu "ADC driver options"
depends on LPC11_ADC
config ADC0_AVERAGE
config LPC11_ADC0_AVERAGE
int "ADC0 average"
default 200
config ADC0_MASK
config LPC11_ADC0_MASK
hex "ADC0 mask"
default 0x01
config ADC0_SPS
config LPC11_ADC0_SPS
int "ADC0 SPS"
default 1000
config ADC_CHANLIST
config LPC11_ADC_CHANLIST
bool "Use ADC channel list"
default n
---help---
@ -131,25 +131,27 @@ config ADC_CHANLIST
triggering interrupt from the global DONE flag).
If this option is enabled, then the platform specific code must do
two things: (1) define ADC_NCHANNELS in the configuration file and
(2) provide an array g_adc_chanlist[] with the channel numbers
matching the ADC0_MASK within the board-specific library.
two things: (1) define LPC11_ADC_NCHANNELS in the configuration file
and (2) provide an array g_adc_chanlist[] with the channel numbers
matching the LPC11_ADC0_MASK within the board-specific library.
config ADC_BURSTMODE
config LPC11_ADC_BURSTMODE
bool "One interrupt at the end of all ADC cconversions"
default n
---help---
Select this if you want to generate only one interrupt once all selected channels has been converted by the ADC
Select this if you want to generate only one interrupt once all
selected channels has been converted by the ADC
config ADC_NCHANNELS
config LPC11_ADC_NCHANNELS
int "ADC0 number of channels"
depends on ADC_CHANLIST
depends on LPC11_ADC_CHANLIST
default 0
---help---
If ADC_CHANLIST is enabled, then the platform specific code
must do two things: (1) define ADC_NCHANNELS in the configuration
If LPC11_ADC_CHANLIST is enabled, then the platform specific code
must do two things: (1) define LPC11_ADC_NCHANNELS in the configuration
file and (2) provide an array g_adc_chanlist[] with the channel
numbers matching the ADC0_MASK within the board-specific library.
numbers matching the LPC11_ADC0_MASK within the board-specific
library.
endmenu

62
arch/arm/src/lpc17xx/Kconfig
View File

@ -61,7 +61,7 @@ config ARCH_CHIP_LPC1769
config ARCH_CHIP_LPC1773
bool "LPC1773"
select ARCH_FAMILY_LPC177X
select ARCH_HAVE_SPIFI
select LPC17_HAVE_SPIFI
config ARCH_CHIP_LPC1774
bool "LPC1774"
@ -109,7 +109,7 @@ config ARCH_FAMILY_LPC177X
config ARCH_FAMILY_LPC178X
bool
config ARCH_HAVE_SPIFI
config LPC17_HAVE_SPIFI
bool
menu "LPC17xx Peripheral Support"
@ -130,10 +130,10 @@ config LPC17_EMC
bool "EMC"
default y
depends on ARCH_FAMILY_LPC178X
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTDRAM
select ARCH_HAVE_EXTNOR
select LPC17_HAVE_EXTNAND
select LPC17_HAVE_EXTSRAM0
select LPC17_HAVE_EXTDRAM
select LPC17_HAVE_EXTNOR
config LPC17_ETHERNET
bool "Ethernet"
@ -228,7 +228,7 @@ config LPC17_SSP2
config LPC17_SPIFI
bool "SPIFI Interface"
depends on ARCH_HAVE_SPIFI
depends on LPC17_HAVE_SPIFI
default n
config LPC17_I2C0
@ -364,22 +364,22 @@ endmenu
menu "External Memory Configuration"
config ARCH_HAVE_EXTNAND
config LPC17_HAVE_EXTNAND
bool
config ARCH_HAVE_EXTNOR
config LPC17_HAVE_EXTNOR
bool
config ARCH_HAVE_EXTDRAM
config LPC17_HAVE_EXTDRAM
bool
config ARCH_HAVE_EXTSRAM0
config LPC17_HAVE_EXTSRAM0
bool
config LPC17_EXTNAND
bool "Configure external NAND"
default n
depends on ARCH_HAVE_EXTNAND
depends on LPC17_HAVE_EXTNAND
---help---
Configure external NAND memory and, if applicable, map then external
NAND into the memory map.
@ -397,7 +397,7 @@ endif
config LPC17_EXTNOR
bool "Configure external NOR memory"
default n
depends on ARCH_HAVE_EXTNOR
depends on LPC17_HAVE_EXTNOR
---help---
Configure external NOR memory and, if applicable, map then external
NOR into the memory map.
@ -415,7 +415,7 @@ endif
config LPC17_EXTDRAM
bool "Configure external DRAM"
default n
depends on ARCH_HAVE_EXTDRAM
depends on LPC17_HAVE_EXTDRAM
select ARCH_HAVE_SDRAM
---help---
Configure external DRAM memory and, if applicable, map then external
@ -455,7 +455,7 @@ endif
config LPC17_EXTSRAM0
bool "Configure external SRAM (Bank 0)"
default n
depends on ARCH_HAVE_EXTSRAM0
depends on LPC17_HAVE_EXTSRAM0
---help---
Configure external SRAM Bank 0 memory and, if applicable, map then
external SRAM Bank 0 into the memory map.
@ -480,7 +480,7 @@ endmenu
menu "Serial driver options"
depends on LPC17_UART0 || LPC17_UART1 || LPC17_UART2 || LPC17_UART3 || LPC17_UART4
config UART1_RINGINDICATOR
config LPC17_UART1_RINGINDICATOR
bool "UART1 ring indicator"
depends on LPC17_UART1
default n
@ -492,19 +492,19 @@ endmenu
menu "ADC driver options"
depends on LPC17_ADC
config ADC0_AVERAGE
config LPC17_ADC0_AVERAGE
int "ADC0 average"
default 200
config ADC0_MASK
config LPC17_ADC0_MASK
hex "ADC0 mask"
default 0x01
config ADC0_SPS
config LPC17_ADC0_SPS
int "ADC0 SPS"
default 1000
config ADC_CHANLIST
config LPC17_ADC_CHANLIST
bool "Use ADC channel list"
default n
---help---
@ -519,25 +519,27 @@ config ADC_CHANLIST
triggering interrupt from the global DONE flag).
If this option is enabled, then the platform specific code must do
two things: (1) define ADC_NCHANNELS in the configuration file and
(2) provide an array g_adc_chanlist[] with the channel numbers
matching the ADC0_MASK within the board-specific library.
two things: (1) define LPC17_ADC_NCHANNELS in the configuration file
and (2) provide an array g_adc_chanlist[] with the channel numbers
matching the LPC17_ADC0_MASK within the board-specific library.
config ADC_BURSTMODE
config LPC17_ADC_BURSTMODE
bool "One interrupt at the end of all ADC cconversions"
default n
---help---
Select this if you want to generate only one interrupt once all selected channels has been converted by the ADC
Select this if you want to generate only one interrupt once all selected
channels has been converted by the ADC
config ADC_NCHANNELS
config LPC17_ADC_NCHANNELS
int "ADC0 number of channels"
depends on ADC_CHANLIST
depends on LPC17_ADC_CHANLIST
default 0
---help---
If ADC_CHANLIST is enabled, then the platform specific code
must do two things: (1) define ADC_NCHANNELS in the configuration
If LPC17_ADC_CHANLIST is enabled, then the platform specific code
must do two things: (1) define LPC17_ADC_NCHANNELS in the configuration
file and (2) provide an array g_adc_chanlist[] with the channel
numbers matching the ADC0_MASK within the board-specific library.
numbers matching the LPC17_ADC0_MASK within the board-specific
library.
endmenu

48
arch/arm/src/lpc17xx/lpc17_adc.c
View File

@ -73,14 +73,16 @@
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_ADC0_MASK
#define CONFIG_ADC0_MASK 0x01
#ifndef CONFIG_LPC17_ADC0_MASK
# define CONFIG_LPC17_ADC0_MASK 0x01
#endif
#ifndef CONFIG_ADC0_SPS
#define CONFIG_ADC0_SPS 1000
#ifndef CONFIG_LPC17_ADC0_SPS
# define CONFIG_LPC17_ADC0_SPS 1000
#endif
#ifndef CONFIG_ADC0_AVERAGE
#define CONFIG_ADC0_AVERAGE 200
#ifndef CONFIG_LPC17_ADC0_AVERAGE
# define CONFIG_LPC17_ADC0_AVERAGE 200
#endif
/****************************************************************************
@ -130,8 +132,8 @@ static const struct adc_ops_s g_adcops =
static struct up_dev_s g_adcpriv =
{
.sps = CONFIG_ADC0_SPS,
.mask = CONFIG_ADC0_MASK,
.sps = CONFIG_LPC17_ADC0_SPS,
.mask = CONFIG_LPC17_ADC0_MASK,
.irq = LPC17_IRQ_ADC,
};
@ -216,7 +218,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
regval |= (SYSCON_PCLKSEL_CCLK8 << SYSCON_PCLKSEL0_ADC_SHIFT);
putreg32(regval, LPC17_SYSCON_PCLKSEL0);
#ifdef CONFIG_ADC_BURSTMODE
#ifdef CONFIG_LPC17_ADC_BURSTMODE
clkdiv = LPC17_CCLK / 3 / 65 / priv->sps;
//putreg32(0x04, LPC17_ADC_INTEN); /* Enable only last channel interrupt */
@ -236,14 +238,14 @@ static void adc_reset(FAR struct adc_dev_s *dev)
* trigger A/D conversion) */
LPC17_ADC_CR);
#else /* CONFIG_ADC_BURSTMODE */
#else /* CONFIG_LPC17_ADC_BURSTMODE */
clkdiv = LPC17_CCLK / 8 / 65 / priv->sps;
clkdiv <<= 8;
clkdiv &= 0xff00;
putreg32(ADC_CR_PDN | ADC_CR_BURST | clkdiv | priv->mask, LPC17_ADC_CR);
#endif /* CONFIG_ADC_BURSTMODE */
#endif /* CONFIG_LPC17_ADC_BURSTMODE */
if ((priv->mask & 0x01) != 0)
{
@ -358,24 +360,24 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
if (enable)
{
#ifndef CONFIG_ADC_BURSTMODE
#ifdef CONFIG_ADC_CHANLIST
#ifndef CONFIG_LPC17_ADC_BURSTMODE
#ifdef CONFIG_LPC17_ADC_CHANLIST
/* Trigger interrupt at the end of conversion on the last A/D channel
* in the channel list.
*/
putreg32(ADC_INTEN_CHAN(g_adc_chanlist[CONFIG_ADC_NCHANNELS - 1]),
putreg32(ADC_INTEN_CHAN(g_adc_chanlist[CONFIG_LPC17_ADC_NCHANNELS - 1]),
LPC17_ADC_INTEN);
#else
/* Trigger interrupt using the global DONE flag. */
putreg32(ADC_INTEN_GLOBAL, LPC17_ADC_INTEN);
#endif
#else /* CONFIG_ADC_BURSTMODE */
#else /* CONFIG_LPC17_ADC_BURSTMODE */
/* Enable only global interrupt */
putreg32(0x100, LPC17_ADC_INTEN);
#endif /* CONFIG_ADC_BURSTMODE */
#endif /* CONFIG_LPC17_ADC_BURSTMODE */
}
else
{
@ -408,8 +410,8 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
static int adc_interrupt(int irq, void *context, FAR void *arg)
{
#ifndef CONFIG_ADC_BURSTMODE
#ifdef CONFIG_ADC_CHANLIST
#ifndef CONFIG_LPC17_ADC_BURSTMODE
#ifdef CONFIG_LPC17_ADC_CHANLIST
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
uint32_t regval;
@ -418,7 +420,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg)
int i;
regval = getreg32(LPC17_ADC_GDR);
for (i = 0; i < CONFIG_ADC_NCHANNELS; i++)
for (i = 0; i < CONFIG_LPC17_ADC_NCHANNELS; i++)
{
ch = g_adc_chanlist[i];
regval = getreg32(LPC17_ADC_DR(ch));
@ -428,7 +430,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg)
priv->count[ch]++;
priv->buf[ch] += regval & 0xfff0;
if (priv->count[ch] >= CONFIG_ADC0_AVERAGE)
if (priv->count[ch] >= CONFIG_LPC17_ADC0_AVERAGE)
{
value = priv->buf[ch] / priv->count[ch];
value <<= 15;
@ -453,7 +455,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg)
priv->buf[ch] += regval & 0xfff0;
priv->count[ch]++;
if (priv->count[ch] >= CONFIG_ADC0_AVERAGE)
if (priv->count[ch] >= CONFIG_LPC17_ADC0_AVERAGE)
{
value = priv->buf[ch] / priv->count[ch];
value <<= 15;
@ -465,7 +467,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg)
return OK;
#endif
#else /* CONFIG_ADC_BURSTMODE */
#else /* CONFIG_LPC17_ADC_BURSTMODE */
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
volatile uint32_t regVal, regVal2, regVal3;
@ -624,7 +626,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg)
//lpc17_gpiowrite(LPCXPRESSO_GPIO0_21, 0); /* Reset pin P0.21 */
//leave_critical_section(saved_state);
return OK;
#endif /* CONFIG_ADC_BURSTMODE */
#endif /* CONFIG_LPC17_ADC_BURSTMODE */
}
/****************************************************************************

32
arch/arm/src/lpc17xx/lpc17_adc.h
View File

@ -47,17 +47,17 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* If CONFIG_ADC_CHANLIST is enabled, then the platform specific code must do
* two things: (1) define CONFIG_ADC_NCHANNELS in the configuration file and
* (2) provide an array g_adc_chanlist[] with the channel numbers matching
* the ADC0_MASK within the board-specific library.
/* If CONFIG_LPC17_ADC_CHANLIST is enabled, then the platform specific code
* must do two things: (1) define CONFIG_LPC17_ADC_NCHANNELS in the
* configuration file and (2) provide an array g_adc_chanlist[] with the
* channel numbers matching the ADC0_MASK within the board-specific library.
*/
#ifdef CONFIG_ADC_CHANLIST
# if !defined(CONFIG_ADC_NCHANNELS)
# error "CONFIG_ADC_CHANLIST must defined in this configuration"
# elif CONFIG_ADC_NCHANNELS < 1
# error "The value of CONFIG_ADC_NCHANNELS is invalid"
#ifdef CONFIG_LPC17_ADC_CHANLIST
# if !defined(CONFIG_LPC17_ADC_NCHANNELS)
# error "CONFIG_LPC17_ADC_CHANLIST must defined in this configuration"
# elif CONFIG_LPC17_ADC_NCHANNELS < 1
# error "The value of CONFIG_LPC17_ADC_NCHANNELS is invalid"
# endif
#endif
@ -81,19 +81,19 @@ extern "C"
/* The errata that states: "A/D Global Data register should not be used with
* burst mode or hardware triggering". The configuration option
* CONFIG_ADC_CHANLIST is a workaround for this errata. If this option is
* selected, then the ADC driver will grab from the individual channel
* CONFIG_LPC17_ADC_CHANLIST is a workaround for this errata. If this option
* is selected, then the ADC driver will grab from the individual channel
* registers rather than from the global data register as this is the stated
* workaround in the errata.
*
* If this option is enabled, then the platform specific code must do two
* things: (1) define CONFIG_ADC_NCHANNELS in the configuration file and
* (2) provide an array g_adc_chanlist[] with the channel numbers matching
* the ADC0_MASK within the board-specific library.
* things: (1) define CONFIG_LPC17_ADC_NCHANNELS in the configuration file
* and (2) provide an array g_adc_chanlist[] with the channel numbers
* matching the ADC0_MASK within the board-specific library.
*/
#ifdef CONFIG_ADC_CHANLIST
EXTERN uint8_t g_adc_chanlist[CONFIG_ADC_NCHANNELS];
#ifdef CONFIG_LPC17_ADC_CHANLIST
EXTERN uint8_t g_adc_chanlist[CONFIG_LPC17_ADC_NCHANNELS];
#endif
/****************************************************************************

2
arch/arm/src/lpc17xx/lpc17_serial.c
View File

@ -744,7 +744,7 @@ static inline void lpc17_uart1config(void)
lpc17_configgpio(GPIO_UART1_DCD);
lpc17_configgpio(GPIO_UART1_DSR);
lpc17_configgpio(GPIO_UART1_DTR);
#ifdef CONFIG_UART1_RINGINDICATOR
#ifdef CONFIG_LPC17_UART1_RINGINDICATOR
lpc17_configgpio(GPIO_UART1_RI);
#endif
#endif

48
arch/arm/src/lpc31xx/Kconfig
View File

@ -12,31 +12,31 @@ choice
config ARCH_CHIP_LPC3130
bool "LPC3130"
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTSRAM1
select ARCH_HAVE_EXTDRAM
select LPC31_HAVE_EXTNAND
select LPC31_HAVE_EXTSRAM0
select LPC31_HAVE_EXTSRAM1
select LPC31_HAVE_EXTDRAM
config ARCH_CHIP_LPC3131
bool "LPC3131"
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTSRAM1
select ARCH_HAVE_EXTDRAM
select LPC31_HAVE_EXTNAND
select LPC31_HAVE_EXTSRAM0
select LPC31_HAVE_EXTSRAM1
select LPC31_HAVE_EXTDRAM
config ARCH_CHIP_LPC3152
bool "LPC3152"
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTSRAM1
select ARCH_HAVE_EXTDRAM
select LPC31_HAVE_EXTNAND
select LPC31_HAVE_EXTSRAM0
select LPC31_HAVE_EXTSRAM1
select LPC31_HAVE_EXTDRAM
config ARCH_CHIP_LPC3154
bool "LPC3154"
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTSRAM1
select ARCH_HAVE_EXTDRAM
select LPC31_HAVE_EXTNAND
select LPC31_HAVE_EXTSRAM0
select LPC31_HAVE_EXTSRAM1
select LPC31_HAVE_EXTDRAM
endchoice # LPC31xx Configuration Options
@ -71,22 +71,22 @@ endmenu # LPC31xx Peripheral Support
menu "External Memory Configuration"
config ARCH_HAVE_EXTNAND
config LPC31_HAVE_EXTNAND
bool
config ARCH_HAVE_EXTDRAM
config LPC31_HAVE_EXTDRAM
bool
config ARCH_HAVE_EXTSRAM0
config LPC31_HAVE_EXTSRAM0
bool
config ARCH_HAVE_EXTSRAM1
config LPC31_HAVE_EXTSRAM1
bool
config LPC31_EXTNAND
bool "Configure external NAND"
default n
depends on ARCH_HAVE_EXTNAND
depends on LPC31_HAVE_EXTNAND
---help---
Configure external NAND memory and, if applicable, map then external
NAND into the memory map.
@ -104,7 +104,7 @@ endif # LPC31_EXTNAND
config LPC31_EXTDRAM
bool "Configure external DRAM"
default n
depends on ARCH_HAVE_EXTDRAM
depends on LPC31_HAVE_EXTDRAM
select ARCH_HAVE_SDRAM
---help---
Configure external DRAM memory and, if applicable, map then external
@ -144,7 +144,7 @@ endif # LPC31_EXTDRAM
config LPC31_EXTSRAM0
bool "Configure external SRAM (Bank 0)"
default n
depends on ARCH_HAVE_EXTSRAM0
depends on LPC31_HAVE_EXTSRAM0
---help---
Configure external SRAM Bank 0 memory and, if applicable, map then
external SRAM Bank 0 into the memory map.
@ -168,7 +168,7 @@ endif # LPC31_EXTSRAM0
config LPC31_EXTSRAM1
bool "Configure external SRAM (Bank 1)"
default n
depends on ARCH_HAVE_EXTSRAM1
depends on LPC31_HAVE_EXTSRAM1
---help---
Configure external SRAM Bank 1 memory and, if applicable, map then
external SRAM Bank 1 into the memory map.

4
arch/arm/src/lpc43xx/Kconfig
View File

@ -690,11 +690,11 @@ endmenu # Ethernet MAC configuration
menu "ADC driver options"
depends on LPC43_ADC0 || LPC43_ADC1
config ADC0_MASK
config LPC43_ADC0_MASK
hex "ADC0 mask"
default 0x01
config ADC0_FREQ
config LPC43_ADC0_FREQ
int "ADC0 frequency"
default 4500000

30
arch/arm/src/lpc43xx/lpc43_adc.c
View File

@ -91,26 +91,26 @@
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_ADC0_MASK
# define CONFIG_ADC0_MASK 0x01
#ifndef CONFIG_LPC43_ADC0_MASK
# define CONFIG_LPC43_ADC0_MASK 0x01
#endif
#ifndef CONFIG_ADC0_FREQ
# define CONFIG_ADC0_FREQ 0
#ifndef CONFIG_LPC43_ADC0_FREQ
# define CONFIG_LPC43_ADC0_FREQ 0
#endif
#define LPC43_ADC_MAX_FREQUENCY 4500000
#define LPC43_ADC_MIN_FREQUENCY (BOARD_ABP3_FREQUENCY/256)
#if defined(CONFIG_ADC0_USE_TIMER) && CONFIG_ADC0_FREQ == 0
# error "Set CONFIG_ADC0_FREQ != 0 if CONFIG_ADC0_USE_TIMER"
#if defined(CONFIG_LPC43_ADC0_USE_TIMER) && CONFIG_LPC43_ADC0_FREQ == 0
# error "Set CONFIG_LPC43_ADC0_FREQ != 0 if CONFIG_LPC43_ADC0_USE_TIMER"
#endif
#ifndef CONFIG_ADC0_USE_TIMER
# if (CONFIG_ADC0_FREQ != 0 &&(CONFIG_ADC0_FREQ > LPC43_ADC_MAX_FREQUENCY || \
CONFIG_ADC0_FREQ < LPC43_ADC_MIN_FREQUENCY))
#ifndef CONFIG_LPC43_ADC0_USE_TIMER
# if (CONFIG_LPC43_ADC0_FREQ != 0 &&(CONFIG_LPC43_ADC0_FREQ > LPC43_ADC_MAX_FREQUENCY || \
CONFIG_LPC43_ADC0_FREQ < LPC43_ADC_MIN_FREQUENCY))
# error "ADC0 sample rate can't be grater than LPC43_ADC_MAX_FREQUENCY or less than LPC43_ADC_MIN_FREQUENCY"
# endif
# define CONFIG_ADC0_USE_TIMER 0
# define CONFIG_LPC43_ADC0_USE_TIMER 0
#endif
/****************************************************************************
@ -159,12 +159,12 @@ static const struct adc_ops_s g_adcops =
static struct up_dev_s g_adcpriv =
{
.freq = CONFIG_ADC0_FREQ,
.mask = CONFIG_ADC0_MASK,
.mask_int = CONFIG_ADC0_MASK,
.freq = CONFIG_LPC43_ADC0_FREQ,
.mask = CONFIG_LPC43_ADC0_MASK,
.mask_int = CONFIG_LPC43_ADC0_MASK,
.irq = LPC43M4_IRQ_ADC0,
.timer = CONFIG_ADC0_USE_TIMER,
.m_ch = (CONFIG_ADC0_MASK & (CONFIG_ADC0_MASK - 1)) ? true : false
.timer = CONFIG_LPC43_ADC0_USE_TIMER,
.m_ch = (CONFIG_LPC43_ADC0_MASK & (CONFIG_LPC43_ADC0_MASK - 1)) ? true : false
};
static struct adc_dev_s g_adcdev =

2
arch/arm/src/lpc43xx/lpc43_uart.c
View File

@ -417,7 +417,7 @@ void lpc43_uart1_setup(void)
lpc43_pin_config(PINCONF_U1_DSR);
lpc43_pin_config(PINCONF_U1_DTR);
lpc43_pin_config(PINCONF_U1_RTS);
#ifdef CONFIG_UART1_RINGINDICATOR
#ifdef CONFIG_LPC43_UART1_RINGINDICATOR
lpc43_pin_config(PINCONF_U1_RI);
#endif
#endif

60
arch/arm/src/sam34/Kconfig
View File

@ -44,10 +44,10 @@ config ARCH_CHIP_ATSAM3X8E
bool "ATSAMSAM3X8E"
select ARCH_CORTEXM3
select ARCH_CHIP_SAM3X
select ARCH_HAVE_EXTNOR
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTSRAM1
select SAM34_HAVE_EXTNOR
select SAM34_HAVE_EXTNAND
select SAM34_HAVE_EXTSRAM0
select SAM34_HAVE_EXTSRAM1
config ARCH_CHIP_ATSAM3X8C
bool "ATSAM3X8C"
@ -58,10 +58,10 @@ config ARCH_CHIP_ATSAM3X4E
bool "ATSAM3X4E"
select ARCH_CORTEXM3
select ARCH_CHIP_SAM3X
select ARCH_HAVE_EXTNOR
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTSRAM1
select SAM34_HAVE_EXTNOR
select SAM34_HAVE_EXTNAND
select SAM34_HAVE_EXTSRAM0
select SAM34_HAVE_EXTSRAM1
config ARCH_CHIP_ATSAM3X4C
bool "ATSAM3X4C"
@ -223,10 +223,10 @@ endchoice # AT91SAM3/4 Chip Selection
config ARCH_CHIP_SAM3U
bool
default n
select ARCH_HAVE_EXTNOR
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTSRAM1
select SAM34_HAVE_EXTNOR
select SAM34_HAVE_EXTNAND
select SAM34_HAVE_EXTSRAM0
select SAM34_HAVE_EXTSRAM1
config ARCH_CHIP_SAM3X
bool
@ -257,10 +257,10 @@ config ARCH_CHIP_SAM4L
config ARCH_CHIP_SAM4E
bool
default n
select ARCH_HAVE_EXTNOR
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTSRAM1
select SAM34_HAVE_EXTNOR
select SAM34_HAVE_EXTNAND
select SAM34_HAVE_EXTSRAM0
select SAM34_HAVE_EXTSRAM1
select SAM34_HAVE_GPIOD_IRQ
select SAM34_HAVE_GPIOE_IRQ
select SAM34_HAVE_GPIOF_IRQ
@ -268,10 +268,10 @@ config ARCH_CHIP_SAM4E
config ARCH_CHIP_SAM4S
bool
default n
select ARCH_HAVE_EXTNOR
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTSRAM1
select SAM34_HAVE_EXTNOR
select SAM34_HAVE_EXTNAND
select SAM34_HAVE_EXTSRAM0
select SAM34_HAVE_EXTSRAM1
menu "AT91SAM3/4 Peripheral Support"
@ -779,25 +779,25 @@ endif # ARCH_CHIP_SAM4L
menu "AT91SAM3/4 External Memory Configuration"
config ARCH_HAVE_EXTNAND
config SAM34_HAVE_EXTNAND
bool
config ARCH_HAVE_EXTNOR
config SAM34_HAVE_EXTNOR
bool
config ARCH_HAVE_EXTDRAM
config SAM34_HAVE_EXTDRAM
bool
config ARCH_HAVE_EXTSRAM0
config SAM34_HAVE_EXTSRAM0
bool
config ARCH_HAVE_EXTSRAM1
config SAM34_HAVE_EXTSRAM1
bool
config SAM34_EXTNAND
bool "Configure external NAND"
default n
depends on ARCH_HAVE_EXTNAND
depends on SAM34_HAVE_EXTNAND
---help---
Configure external NAND memory and, if applicable, map then external
NAND into the memory map.
@ -815,7 +815,7 @@ endif # SAM34_EXTNAND
config SAM34_EXTNOR
bool "Configure external NOR memory"
default n
depends on ARCH_HAVE_EXTNOR
depends on SAM34_HAVE_EXTNOR
---help---
Configure external NOR memory and, if applicable, map then external
NOR into the memory map.
@ -833,7 +833,7 @@ endif # SAM34_EXTNOR
config SAM34_EXTDRAM
bool "Configure external DRAM"
default n
depends on ARCH_HAVE_EXTDRAM
depends on SAM34_HAVE_EXTDRAM
select ARCH_HAVE_SDRAM
---help---
Configure external DRAM memory and, if applicable, map then external
@ -873,7 +873,7 @@ endif # SAM34_EXTDRAM
config SAM34_EXTSRAM0
bool "Configure external SRAM (Bank 0)"
default n
depends on ARCH_HAVE_EXTSRAM0
depends on SAM34_HAVE_EXTSRAM0
---help---
Configure external SRAM Bank 0 memory and, if applicable, map then
external SRAM Bank 0 into the memory map.
@ -897,7 +897,7 @@ endif # SAM34_EXTSRAM0
config SAM34_EXTSRAM1
bool "Configure external SRAM (Bank 1)"
default n
depends on ARCH_HAVE_EXTSRAM1
depends on SAM34_HAVE_EXTSRAM1
---help---
Configure external SRAM Bank 1 memory and, if applicable, map then
external SRAM Bank 1 into the memory map.

2
configs/u-blox-c027/nsh/defconfig
View File

@ -39,6 +39,7 @@ CONFIG_LPC17_I2C1=y
CONFIG_LPC17_PHY_AUTONEG=y
CONFIG_LPC17_UART0=y
CONFIG_LPC17_UART1=y
CONFIG_LPC17_UART1_RINGINDICATOR=y
CONFIG_LPC17_UART2=y
CONFIG_LPC17_UART3=y
CONFIG_MAX_TASKS=16
@ -103,7 +104,6 @@ CONFIG_TASK_NAME_SIZE=0
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_UART1_IFLOWCONTROL=y
CONFIG_UART1_OFLOWCONTROL=y
CONFIG_UART1_RINGINDICATOR=y
CONFIG_UART2_BAUD=9600
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=1