Xtensa ESP32: A few fixes for APP CPU start-up
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Gregory Nutt
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404925d93e
commit
6d5a718b98
@ -88,7 +88,7 @@ CHIP_CSRCS += esp32_timerisr.c
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# Configuration-dependent ESP32 files
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ifeq ($(CONFIG_SMP),y)
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CHIP_ASRCS = esp32_cpuhead.S esp32_cpuindex.S
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CHIP_ASRCS = esp32_cpuindex.S
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CMN_CSRCS += esp32_cpuidlestack.c esp32_cpustart.c esp32_intercpu_interrupt.c
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endif
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@ -1,153 +0,0 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/esp32_cpuhead.S
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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.file "esp32_cpuhead.S"
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/xtensa/xtensa_corebits.h>
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#include <arch/esp32/core-isa.h>
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#ifdef CONFIG_SMP
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/****************************************************************************
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* Private Data
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****************************************************************************/
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.section .noinit, "aw"
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.global g_cpu1_idlestack
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.type g_cpu1_idlestack, @object
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.align 16
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g_cpu1_idlestack:
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.space (CONFIG_SMP_IDLETHREAD_STACKSIZE & ~15)
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.Lcpu1_stacktop:
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.size g_cpu1_idlestack, . - g_cpu1_idlestack
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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.text
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/****************************************************************************
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* Name: __cpu[n]_start
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*
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* Description:
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* Boot functions for each CPU (other than CPU0). These functions set up
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* the ARM operating mode, the initial stack, and configure co-processor
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* registers. At the end of the boot, esp32_cpu_boot() is called.
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*
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* These functions are provided by the common ARMv7-A logic.
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*
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* Input parameters:
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* None
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*
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* Returned Value:
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* Do not return.
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*
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****************************************************************************/
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.global __cpu1_start
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.type __cpu1_start, @function
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.align 4
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.Lcpu1_bottomofstack:
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.long .Lcpu1_stacktop
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.size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack
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#ifdef CONFIG_STACK_COLORATION
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.Lcpu1_bottomofstack:
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.long .Lcpu1_stacktop
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.size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack
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.Lcpu1_stackcolor:
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.long STACK_COLOR
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.size .Lcpu1_stackcolor, . - .Lcpu1_stackcolor
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#endif
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.align 4
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__cpu1_start:
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/* Set up the stack pointer and the CPU index */
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l32r sp, .Lcpu1_bottomofstack
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/* REVIST: Does it make since to have co-processors enabled on the IDLE thread? */
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#ifdef CONFIG_STACK_COLORATION
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/* Write a known value to the IDLE thread stack to support stack
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* monitoring logic
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*/
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mov a0, sp
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l32r a1, .Lcpu1_bottomofstack
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l32r a2, .Lcpu1_stackcolor
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1:
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s32i a2, a1, 0
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addi a2, a2, 4
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bne a1, a2, 1b
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#endif
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/* Set up the intiali PS */
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#ifdef __XTENSA_CALL0_ABI__
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movi a0, (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM)
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#else
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movi a0, (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1))
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#endif
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wsr a0, PS
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/* Finish initialization in C */
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#ifdef __XTENSA_CALL0_ABI__
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movi a2, 1 /* Argument 1: CPU ID */
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call0 xtensa_start_handler
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#else
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movi a6, 1 /* Argument 1: CPU ID */
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call4 xtensa_start_handler
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#endif
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/* xtensa_start_handler() does not return */
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2: j 2b
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.size __cpu1_start, . - __cpu1_start
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#endif /* CONFIG_SMP */
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@ -36,6 +36,16 @@
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#ifdef CONFIG_SMP
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* Address of the CPU0 IDLE thread */
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uint32_t g_cpu1_idlestack[CPU1_IDLETHREAD_STACKWORDS]
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__attribute__((aligned(16) section(".noinit")));
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -129,24 +129,34 @@ static inline void xtensa_attach_fromcpu0_interrupt(void)
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****************************************************************************/
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/****************************************************************************
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* Name: xtensa_start_handler
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* Name: xtensa_appcpu_start
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*
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* Description:
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* This is the handler for SGI1. This handler simply returns from the
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* interrupt, restoring the state of the new task at the head of the ready
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* to run list.
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* This is the entry point used with the APP CPU was started via
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* up_cpu_start(). The actually start-up logic in in ROM and we boot up
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* in C code.
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*
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* Input Parameters:
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* Standard interrupt handling
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* None
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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* None, does not return
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*
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****************************************************************************/
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int xtensa_start_handler(int irq, FAR void *context)
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void xtensa_appcpu_start(void)
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{
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FAR struct tcb_s *tcb = this_task();
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register uint32_t sp;
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/* Move to the stack assigned to us by up_smp_start immediately. Although
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* we were give a stack pointer at start-up, we don't know where that stack
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* pointer is positioned respect to our memory map. The only safe option
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* is to switch to a well-known IDLE thread stack.
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*/
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sp = (uint32_t)tcb->adj_stack_ptr;
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__asm__ __volatile__("mov sp, %0\n" : : "r"(sp));
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sinfo("CPU%d Started\n", up_cpu_index());
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@ -209,7 +219,6 @@ int xtensa_start_handler(int irq, FAR void *context)
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*/
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xtensa_context_restore(tcb->xcp.regs);
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return OK;
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}
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/****************************************************************************
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@ -302,7 +311,7 @@ int up_cpu_start(int cpu)
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/* Set the CPU1 start address */
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ets_set_appcpu_boot_addr((uint32_t)__cpu1_start);
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ets_set_appcpu_boot_addr((uint32_t)xtensa_appcpu_start);
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/* And wait for the initial task to run on CPU1 */
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@ -44,6 +44,20 @@
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#ifdef CONFIG_SMP
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/****************************************************************************
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* Pre-procesor Definitions
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****************************************************************************/
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/* An IDLE thread stack size for CPU0 must be defined */
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#if !defined(CONFIG_SMP_IDLETHREAD_STACKSIZE)
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# error CONFIG_SMP_IDLETHREAD_STACKSIZE is not defined
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#elif CONFIG_SMP_IDLETHREAD_STACKSIZE < 16
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# error CONFIG_SMP_IDLETHREAD_STACKSIZE is to small
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#endif
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#define CPU1_IDLETHREAD_STACKSIZE ((CONFIG_SMP_IDLETHREAD_STACKSIZE + 15) & ~15)
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#define CPU1_IDLETHREAD_STACKWORDS (CPU1_IDLETHREAD_STACKSIZE >> 2)
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/****************************************************************************
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* Public Data
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@ -51,8 +65,7 @@
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/* This is the CPU1 IDLE stack */
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#define CPU1_IDLETHREAD_STACKSIZE (CONFIG_SMP_IDLETHREAD_STACKSIZE & ~15)
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extern uint32_t g_cpu1_idlestack[CPU1_IDLETHREAD_STACKSIZE / 34];
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extern uint32_t g_cpu1_idlestack[CPU1_IDLETHREAD_STACKWORDS];
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/****************************************************************************
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* Public Functions
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