From 6d5f497b018251e100209e63efae6b8acf2bd9e2 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 21 Dec 2009 22:10:13 +0000 Subject: [PATCH] Add LPC313x header files git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2407 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/src/lpc313x/lpc313x_memorymap.h | 2 +- arch/arm/src/lpc313x/lpc313x_nand.h | 378 +++++++++++++++++++++++ 2 files changed, 379 insertions(+), 1 deletion(-) create mode 100755 arch/arm/src/lpc313x/lpc313x_nand.h diff --git a/arch/arm/src/lpc313x/lpc313x_memorymap.h b/arch/arm/src/lpc313x/lpc313x_memorymap.h index 1dff54dbd4..5b48281a78 100755 --- a/arch/arm/src/lpc313x/lpc313x_memorymap.h +++ b/arch/arm/src/lpc313x/lpc313x_memorymap.h @@ -109,7 +109,7 @@ /* 0x00000280 Reserved */ #define LPC313X_APB4_DMA_OFFSET 0x00000000 /* DMA */ -#define LPC313X_APB4_NAND_OFFSET 0x0000080 /* NAND FLASH Controller */ +#define LPC313X_APB4_NAND_OFFSET 0x00000800 /* NAND FLASH Controller */ /* 0x00001000 Reserved */ /************************************************************************************ diff --git a/arch/arm/src/lpc313x/lpc313x_nand.h b/arch/arm/src/lpc313x/lpc313x_nand.h new file mode 100755 index 0000000000..3ff9a781ab --- /dev/null +++ b/arch/arm/src/lpc313x/lpc313x_nand.h @@ -0,0 +1,378 @@ +/************************************************************************************************ + * arch/arm/src/lpc313x/lpc313x_nand.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC313X_NAND_H +#define __ARCH_ARM_SRC_LPC313X_NAND_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "lpc313x_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* NAND FLASH controller register base address offset into the APB4 domain **********************/ + +#define LPC313X_NAND_VBASE (LPC313X_APB4_VSECTION+LPC313X_APB4_NAND_OFFSET) +#define LPC313X_NAND_PBASE (LPC313X_APB4_PSECTION+LPC313X_APB4_NAND_OFFSET) + +/* NAND FLASH controller register offsets (with respect to the base of the APB4 domain) *********/ + +#define LPC313X_NAND_IRQSTATUS1_OFFSET 0x00 /* Interrrupt status register (first 32-bits) */ +#define LPC313X_NAND_IRQMASK1_OFFSET 0x04 /* Interrupt mask register (first 32-bits) */ +#define LPC313X_NAND_IRQSTATUSRAW1_OFFSET 0x08 /* Unmasked register status (first 32-bits) */ +#define LPC313X_NAND_CONFIG_OFFSET 0x0c /* NAND Flash controller configuration register */ +#define LPC313X_NAND_IOCONFIG_OFFSET 0x10 /* Default value settings for IO signals */ +#define LPC313X_NAND_TIMING1_OFFSET 0x14 /* First NAND FLASH controller timing register */ +#define LPC313X_NAND_TIMING2_OFFSET 0x18 /* Second NAND FLASH controller timing register */ +#define LPC313X_NAND_SETCMD_OFFSET 0x20 /* NAND FLASH device command register */ +#define LPC313X_NAND_SETADDR_OFFSET 0x24 /* NAND FLASH device address register */ +#define LPC313X_NAND_WRITEDATA_OFFSET 0x28 /* NAND FLASH device write data register */ +#define LPC313X_NAND_SETCE_OFFSET 0x2c /* Set all CE and WP_n signals */ +#define LPC313X_NAND_READDATA_OFFSET 0x30 /* NAND FLASH device read data register */ +#define LPC313X_NAND_CHECKSTS_OFFSET 0x34 /* Check status of interrupts */ +#define LPC313X_NAND_CONTROLFLOW_OFFSET 0x38 /* Commands to read and write pages */ +#define LPC313X_NAND_GPIO1_OFFSET 0x40 /* Program IO pins that can be used as GPIO */ +#define LPC313X_NAND_GPIO2_OFFSET 0x44 /* Program IO pins that can be used as GPIO */ +#define LPC313X_NAND_IRQSTATUS2_OFFSET 0x48 /* Interrrupt status register (second 32-bits) */ +#define LPC313X_NAND_IRQMASK3_OFFSET 0x4c /* Interrupt mask register (second 32-bits) */ +#define LPC313X_NAND_IRQSTATUSRAW2_OFFSET 0x50 /* Unmasked register status (second 32-bits) */ +#define LPC313X_NAND_ECCERRSTATUS_OFFSET 0x78 /* ECC error status register */ + +/* NAND FLASH controller register (virtual) addresses *******************************************/ + +#define LPC313X_NAND_IRQSTATUS1 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQSTATUS1_OFFSET) +#define LPC313X_NAND_IRQMASK1 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQMASK1_OFFSET) +#define LPC313X_NAND_IRQSTATUSRAW1 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQSTATUSRAW1_OFFSET) +#define LPC313X_NAND_CONFIG (LPC313X_NAND_VBASE+LPC313X_NAND_CONFIG_OFFSET) +#define LPC313X_NAND_IOCONFIG (LPC313X_NAND_VBASE+LPC313X_NAND_IOCONFIG_OFFSET) +#define LPC313X_NAND_TIMING1 (LPC313X_NAND_VBASE+LPC313X_NAND_TIMING1_OFFSET) +#define LPC313X_NAND_TIMING2 (LPC313X_NAND_VBASE+LPC313X_NAND_TIMING2_OFFSET) +#define LPC313X_NAND_SETCMD (LPC313X_NAND_VBASE+LPC313X_NAND_SETCMD_OFFSET) +#define LPC313X_NAND_SETADDR (LPC313X_NAND_VBASE+LPC313X_NAND_SETADDR_OFFSET) +#define LPC313X_NAND_WRITEDATA (LPC313X_NAND_VBASE+LPC313X_NAND_WRITEDATA_OFFSET) +#define LPC313X_NAND_SETCE (LPC313X_NAND_VBASE+LPC313X_NAND_SETCE_OFFSET) +#define LPC313X_NAND_READDATA (LPC313X_NAND_VBASE+LPC313X_NAND_READDATA_OFFSET) +#define LPC313X_NAND_CHECKSTS (LPC313X_NAND_VBASE+LPC313X_NAND_CHECKSTS_OFFSET) +#define LPC313X_NAND_CONTROLFLOW (LPC313X_NAND_VBASE+LPC313X_NAND_CONTROLFLOW_OFFSET) +#define LPC313X_NAND_GPIO1 (LPC313X_NAND_VBASE+LPC313X_NAND_GPIO1_OFFSET) +#define LPC313X_NAND_GPIO2 (LPC313X_NAND_VBASE+LPC313X_NAND_GPIO2_OFFSET) +#define LPC313X_NAND_IRQSTATUS2 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQSTATUS2_OFFSET) +#define LPC313X_NAND_IRQMASK3 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQMASK3_OFFSET) +#define LPC313X_NAND_IRQSTATUSRAW2 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQSTATUSRAW2_OFFSET) +#define LPC313X_NAND_ECCERRSTATUS (LPC313X_NAND_VBASE+LPC313X_NAND_ECCERRSTATUS_OFFSET) + +/* NAND FLASH controller register bit definitions ***********************************************/ +/* NandIRQStatus1 register description (NandIRQStatus1, address 0x17000800) */ + +#define NAND_IRQSTATUS1_MNANDRYBN3 (1 << 31) /* Bit 31: mNAND_RYBN3 positive edge */ +#define NAND_IRQSTATUS1_MNANDRYBN2 (1 << 30) /* Bit 30: mNAND_RYBN2 positive edge */ +#define NAND_IRQSTATUS1_MNANDRYBN1 (1 << 29) /* Bit 29: mNAND_RYBN1 positive edge */ +#define NAND_IRQSTATUS1_MNANDRYBN0 (1 << 28) /* Bit 28: mNAND_RYBN0 positive edge */ +#define NAND_IRQSTATUS1_RAM1ERASED (1 << 27) /* Bit 27: RAM 1 erased */ +#define NAND_IRQSTATUS1_RAM0ERASED (1 << 26) /* Bit 26: RAM 0 erased */ +#define NAND_IRQSTATUS1_WRPG1DONE (1 << 25) /* Bit 25: Write page 1 done */ +#define NAND_IRQSTATUS1_WRPG0DONE (1 << 24) /* Bit 24: Write page 0 done */ +#define NAND_IRQSTATUS1_RDPG1DONE (1 << 23) /* Bit 23: Read page 1 done */ +#define NAND_IRQSTATUS1_RDPG0DONE (1 << 22) /* Bit 22: Read page 0 done */ +#define NAND_IRQSTATUS1_RAM0DECODE (1 << 21) /* Bit 21: RAM 0 decoded */ +#define NAND_IRQSTATUS1_RAM0ENCODE (1 << 20) /* Bit 20: RAM 0 encoded */ +#define NAND_IRQSTATUS1_RAM1DECODE (1 << 19) /* Bit 19: RAM 1 decoded */ +#define NAND_IRQSTATUS1_RAM1ENCODE (1 << 18) /* Bit 18: RAM 1 encoded */ +#define NAND_IRQSTATUS1_RAM00ERRS (1 << 17) /* Bit 17: RAM 0 decoded with 0 errors */ +#define NAND_IRQSTATUS1_RAM01ERR (1 << 16) /* Bit 16: RAM 0 decoded with 1 error (depends on mode) */ +#define NAND_IRQSTATUS1_RAM02ERR (1 << 15) /* Bit 15: RAM 0 decoded with 2 error */ +#define NAND_IRQSTATUS1_RAM03ERR (1 << 14) /* Bit 14: RAM 0 decoded with 3 error */ +#define NAND_IRQSTATUS1_RAM04ERR (1 << 13) /* Bit 13: RAM 0 decoded with 4 error */ +#define NAND_IRQSTATUS1_RAM05ERR (1 << 12) /* Bit 12: RAM 0 decoded with 5 error */ +#define NAND_IRQSTATUS1_RAM0UNCORR (1 << 11) /* Bit 11: RAM 0 uncorrectable */ +#define NAND_IRQSTATUS1_RAM10ERR (1 << 10) /* Bit 10: RAM 1 decoded with 0 errors */ +#define NAND_IRQSTATUS1_RAM11ERR (1 << 9) /* Bit 9: RAM 1 decoded with 1 error (depends on mode) */ +#define NAND_IRQSTATUS1_RAM12ERR (1 << 8) /* Bit 8: RAM 1 decoded with 2 error */ +#define NAND_IRQSTATUS1_RAM13ERR (1 << 7) /* Bit 7: RAM 1 decoded with 3 error */ +#define NAND_IRQSTATUS1_RAM14ERR (1 << 6) /* Bit 6: RAM 1 decoded with 4 error */ +#define NAND_IRQSTATUS1_RAM15ERR (1 << 5) /* Bit 5: RAM 1 decoded with 5 error */ +#define NAND_IRQSTATUS1_RAM1UNCORR (1 << 4) /* Bit 4: RAM 1 uncorrectable */ + +/* NandIRQMask1 register description (NandIRQMask1, address 0x17000804) */ + +#define NAND_IRQIRQMASK1_MNANDRYBN3 (1 << 31) /* Bit 31: mNAND_RYBN3 positive edge */ +#define NAND_IRQIRQMASK1_MNANDRYBN2 (1 << 30) /* Bit 30: mNAND_RYBN2 positive edge */ +#define NAND_IRQIRQMASK1_MNANDRYBN1 (1 << 29) /* Bit 29: mNAND_RYBN1 positive edge */ +#define NAND_IRQIRQMASK1_MNANDRYBN0 (1 << 28) /* Bit 28: mNAND_RYBN0 positive edge */ +#define NAND_IRQIRQMASK1_RAM1ERASED (1 << 27) /* Bit 27: RAM 1 erased */ +#define NAND_IRQIRQMASK1_RAM0ERASED (1 << 26) /* Bit 26: RAM 0 erased */ +#define NAND_IRQIRQMASK1_WRPG1DONE (1 << 25) /* Bit 25: Write page 1 done */ +#define NAND_IRQIRQMASK1_WRPG0DONE (1 << 24) /* Bit 24: Write page 0 done */ +#define NAND_IRQIRQMASK1_RDPG1DONE (1 << 23) /* Bit 23: Read page 1 done */ +#define NAND_IRQIRQMASK1_RDPG0DONE (1 << 22) /* Bit 22: Read page 0 done */ +#define NAND_IRQIRQMASK1_RAM0DECODE (1 << 21) /* Bit 21: RAM 0 decoded */ +#define NAND_IRQIRQMASK1_RAM0ENCODE (1 << 20) /* Bit 20: RAM 0 encoded */ +#define NAND_IRQIRQMASK1_RAM1DECODE (1 << 19) /* Bit 19: RAM 1 decoded */ +#define NAND_IRQIRQMASK1_RAM1ENCODE (1 << 18) /* Bit 18: RAM 1 encoded */ +#define NAND_IRQIRQMASK1_RAM00ERRS (1 << 17) /* Bit 17: RAM 0 decoded with 0 errors */ +#define NAND_IRQIRQMASK1_RAM01ERR (1 << 16) /* Bit 16: RAM 0 decoded with 1 error (depends on mode) */ +#define NAND_IRQIRQMASK1_RAM02ERR (1 << 15) /* Bit 15: RAM 0 decoded with 2 error */ +#define NAND_IRQIRQMASK1_RAM03ERR (1 << 14) /* Bit 14: RAM 0 decoded with 3 error */ +#define NAND_IRQIRQMASK1_RAM04ERR (1 << 13) /* Bit 13: RAM 0 decoded with 4 error */ +#define NAND_IRQIRQMASK1_RAM05ERR (1 << 12) /* Bit 12: RAM 0 decoded with 5 error */ +#define NAND_IRQIRQMASK1_RAM0UNCORR (1 << 11) /* Bit 11: RAM 0 uncorrectable */ +#define NAND_IRQIRQMASK1_RAM10ERR (1 << 10) /* Bit 10: RAM 1 decoded with 0 errors */ +#define NAND_IRQIRQMASK1_RAM11ERR (1 << 9) /* Bit 9: RAM 1 decoded with 1 error (depends on mode) */ +#define NAND_IRQIRQMASK1_RAM12ERR (1 << 8) /* Bit 8: RAM 1 decoded with 2 error */ +#define NAND_IRQIRQMASK1_RAM13ERR (1 << 7) /* Bit 7: RAM 1 decoded with 3 error */ +#define NAND_IRQIRQMASK1_RAM14ERR (1 << 6) /* Bit 6: RAM 1 decoded with 4 error */ +#define NAND_IRQIRQMASK1_RAM15ERR (1 << 5) /* Bit 5: RAM 1 decoded with 5 error */ +#define NAND_IRQIRQMASK1_RAM1UNCORR (1 << 4) /* Bit 4: RAM 1 uncorrectable */ + +/* NandIRQStatusRaw1 register description (NandIRQStatusRaw1, address 0x17000808) */ + +#define NAND_IRQSTATUSRAW1_MNANDRYBN3 (1 << 31) /* Bit 31: mNAND_RYBN3 positive edge */ +#define NAND_IRQSTATUSRAW1_MNANDRYBN2 (1 << 30) /* Bit 30: mNAND_RYBN2 positive edge */ +#define NAND_IRQSTATUSRAW1_MNANDRYBN1 (1 << 29) /* Bit 29: mNAND_RYBN1 positive edge */ +#define NAND_IRQSTATUSRAW1_MNANDRYBN0 (1 << 28) /* Bit 28: mNAND_RYBN0 positive edge */ +#define NAND_IRQSTATUSRAW1_RAM1ERASED (1 << 27) /* Bit 27: RAM 1 erased */ +#define NAND_IRQSTATUSRAW1_RAM0ERASED (1 << 26) /* Bit 26: RAM 0 erased */ +#define NAND_IRQSTATUSRAW1_WRPG1DONE (1 << 25) /* Bit 25: Write page 1 done */ +#define NAND_IRQSTATUSRAW1_WRPG0DONE (1 << 24) /* Bit 24: Write page 0 done */ +#define NAND_IRQSTATUSRAW1_RDPG1DONE (1 << 23) /* Bit 23: Read page 1 done */ +#define NAND_IRQSTATUSRAW1_RDPG0DONE (1 << 22) /* Bit 22: Read page 0 done */ +#define NAND_IRQSTATUSRAW1_RAM0DECODE (1 << 21) /* Bit 21: RAM 0 decoded */ +#define NAND_IRQSTATUSRAW1_RAM0ENCODE (1 << 20) /* Bit 20: RAM 0 encoded */ +#define NAND_IRQSTATUSRAW1_RAM1DECODE (1 << 19) /* Bit 19: RAM 1 decoded */ +#define NAND_IRQSTATUSRAW1_RAM1ENCODE (1 << 18) /* Bit 18: RAM 1 encoded */ +#define NAND_IRQSTATUSRAW1_RAM00ERRS (1 << 17) /* Bit 17: RAM 0 decoded with 0 errors */ +#define NAND_IRQSTATUSRAW1_RAM01ERR (1 << 16) /* Bit 16: RAM 0 decoded with 1 error (depends on mode) */ +#define NAND_IRQSTATUSRAW1_RAM02ERR (1 << 15) /* Bit 15: RAM 0 decoded with 2 error */ +#define NAND_IRQSTATUSRAW1_RAM03ERR (1 << 14) /* Bit 14: RAM 0 decoded with 3 error */ +#define NAND_IRQSTATUSRAW1_RAM04ERR (1 << 13) /* Bit 13: RAM 0 decoded with 4 error */ +#define NAND_IRQSTATUSRAW1_RAM05ERR (1 << 12) /* Bit 12: RAM 0 decoded with 5 error */ +#define NAND_IRQSTATUSRAW1_RAM0UNCORR (1 << 11) /* Bit 11: RAM 0 uncorrectable */ +#define NAND_IRQSTATUSRAW1_RAM10ERR (1 << 10) /* Bit 10: RAM 1 decoded with 0 errors */ +#define NAND_IRQSTATUSRAW1_RAM11ERR (1 << 9) /* Bit 9: RAM 1 decoded with 1 error (depends on mode) */ +#define NAND_IRQSTATUSRAW1_RAM12ERR (1 << 8) /* Bit 8: RAM 1 decoded with 2 error */ +#define NAND_IRQSTATUSRAW1_RAM13ERR (1 << 7) /* Bit 7: RAM 1 decoded with 3 error */ +#define NAND_IRQSTATUSRAW1_RAM14ERR (1 << 6) /* Bit 6: RAM 1 decoded with 4 error */ +#define NAND_IRQSTATUSRAW1_RAM15ERR (1 << 5) /* Bit 5: RAM 1 decoded with 5 error */ +#define NAND_IRQSTATUSRAW1_RAM1UNCORR (1 << 4) /* Bit 4: RAM 1 uncorrectable */ + +/* NandConfig register description (NandConfig, address 0x1700080c) */ + +#define NAND_CONFIG_ECC_MODE (1 << 12) /* Bit 12: ECC mode 0 */ +#define NAND_CONFIG_TL_SHIFT (10) /* Bits 10-11: Transfer limit */ +#define NAND_CONFIG_TL_MASK (3 <