armv7a/r: refact cp15_cache functions
Signed-off-by: ligd <liguiding1@xiaomi.com>
This commit is contained in:
ligd
Xiang Xiao
parent
c866b6be9a
commit
6d92810d5a
@ -36,11 +36,7 @@ endif
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# Common assembly language files
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CMN_ASRCS += arm_cpuhead.S arm_vectoraddrexcptn.S
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CMN_ASRCS += arm_vectors.S cp15_cache_size.S cp15_clean_dcache_all.S
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CMN_ASRCS += cp15_clean_dcache.S cp15_coherent_dcache.S
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CMN_ASRCS += cp15_flush_dcache_all.S cp15_flush_dcache.S
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CMN_ASRCS += cp15_invalidate_dcache_all.S cp15_invalidate_dcache.S
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CMN_ASRCS += arm_cpuhead.S arm_vectoraddrexcptn.S arm_vectors.S
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# Common C source files
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@ -49,7 +45,7 @@ CMN_CSRCS += arm_doirq.c arm_gicv2.c arm_gicv2_dump.c
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CMN_CSRCS += arm_initialstate.c arm_mmu.c arm_prefetchabort.c
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CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
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CMN_CSRCS += arm_syscall.c arm_tcbinfo.c arm_undefinedinsn.c
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CMN_CSRCS += arm_perf.c
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CMN_CSRCS += arm_perf.c cp15_cacheops.c
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ifeq ($(CONFIG_ARMV7A_HAVE_PTM), y)
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CMN_CSRCS += arm_timer.c
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@ -1,85 +0,0 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/cp15_cache_size.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "cp15.h"
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.file "cp15_cache_size.S"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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.globl cp15_cache_size
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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.text
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/****************************************************************************
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* Name: cp15_cache_size
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*
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* Description:
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* Get cp15 cache size in byte
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Cache size in byte
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*
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****************************************************************************/
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.globl cp15_cache_size
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.type cp15_cache_size, function
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cp15_cache_size:
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mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
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ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
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and r2, r3, r0, lsr #13 /* r2=NumSets (number of sets - 1) */
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add r2, #1
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ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
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and r1, r3, r0, lsr #3 /* r1=(number of ways - 1) */
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add r1, #1
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ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
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and r0, r3 /* r0=(Log2LineSize - 2) in word */
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add r0, #4 /* r0=Log2lineSize in byte */
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mul r2, r1, r2 /* r2=Sets*Ways */
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lsl r0, r2, r0 /* r0=Sets*Ways*LineSize */
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bx lr
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.size cp15_cache_size, . - cp15_cache_size
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.end
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245
arch/arm/src/armv7-a/cp15_cacheops.c
Normal file
245
arch/arm/src/armv7-a/cp15_cacheops.c
Normal file
@ -0,0 +1,245 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/cp15_cacheops.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/cache.h>
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#include <nuttx/irq.h>
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#include "cp15_cacheops.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define CP15_CACHE_INVALIDATE 0
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#define CP15_CACHE_CLEAN 1
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#define CP15_CACHE_CLEANINVALIDATE 2
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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static inline uint32_t ilog2(uint32_t u)
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{
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int i = 0;
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while (u >>= 1)
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{
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i++;
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}
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return i;
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}
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static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways)
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{
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uint32_t ccsidr = CP15_GET(CCSIDR);
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if (sets)
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{
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*sets = ((ccsidr >> 13) & 0x7fff) + 1;
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}
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if (ways)
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{
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*ways = ((ccsidr >> 3) & 0x3ff) + 1;
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}
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return (1 << ((ccsidr & 0x7) + 2)) * 4;
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}
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static void cp15_dcache_op_level(uint32_t level, int op)
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{
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uint32_t sets;
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uint32_t ways;
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uint32_t set;
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uint32_t way;
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uint32_t line;
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uint32_t way_shift;
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uint32_t set_shift;
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uint32_t val = level << 1;
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/* Select by CSSELR */
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CP15_SET(CSSELR, val);
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/* Get cache info */
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line = cp15_cache_get_info(&sets, &ways);
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way_shift = 32 - ilog2(ways);
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set_shift = ilog2(line);
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ARM_DSB();
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/* A: Log2(ways)
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* B: L+S
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* L: Log2(line)
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* S: Log2(sets)
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*
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* The bits are packed as follows:
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* 31 31-A B B-1 L L-1 4 3 1 0
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* |---|-------------|--------|-------|-----|-|
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* |Way| zeros | Set | zeros |level|0|
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* |---|-------------|--------|-------|-----|-|
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*/
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for (way = 0; way < ways; way++)
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{
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for (set = 0; set < sets; set++)
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{
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val = level << 1;
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val |= way << way_shift;
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val |= set << set_shift;
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switch (op)
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{
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case CP15_CACHE_INVALIDATE:
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cp15_invalidate_dcacheline_bysetway(val);
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break;
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case CP15_CACHE_CLEAN:
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cp15_clean_dcache_bysetway(val);
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break;
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case CP15_CACHE_CLEANINVALIDATE:
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cp15_cleaninvalidate_dcacheline(val);
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break;
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default:
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break;
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}
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}
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}
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ARM_ISB();
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}
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static void cp15_dcache_op(int op)
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{
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uint32_t clidr = CP15_GET(CLIDR);
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int level;
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for (level = 0; level < 7; level++)
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{
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uint32_t ctype = clidr & 0x7;
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switch (ctype)
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{
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case 0x2:
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case 0x3:
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case 0x4:
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cp15_dcache_op_level(level, op);
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break;
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default:
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break;
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}
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clidr >>= 3;
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if (clidr == 0)
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{
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break;
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}
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}
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}
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static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
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{
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uint32_t line;
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line = cp15_cache_get_info(NULL, NULL);
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start &= ~(line - 1);
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ARM_DSB();
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while (start < end)
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{
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switch (op)
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{
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case CP15_CACHE_INVALIDATE:
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cp15_invalidate_dcacheline_bymva(start);
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break;
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case CP15_CACHE_CLEAN:
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cp15_clean_dcache_bymva(start);
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break;
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case CP15_CACHE_CLEANINVALIDATE:
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cp15_cleaninvalidate_dcacheline_bymva(start);
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break;
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default:
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break;
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}
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start += line;
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}
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ARM_ISB();
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
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{
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cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
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cp15_invalidate_icache();
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}
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void cp15_invalidate_dcache(uintptr_t start, uintptr_t end)
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{
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cp15_dcache_op_mva(start, end, CP15_CACHE_INVALIDATE);
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}
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void cp15_invalidate_dcache_all(void)
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{
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cp15_dcache_op(CP15_CACHE_INVALIDATE);
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}
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void cp15_clean_dcache(uintptr_t start, uintptr_t end)
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{
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cp15_dcache_op_mva(start, end, CP15_CACHE_CLEAN);
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}
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void cp15_clean_dcache_all(void)
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{
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cp15_dcache_op(CP15_CACHE_CLEAN);
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}
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void cp15_flush_dcache(uintptr_t start, uintptr_t end)
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{
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cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
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}
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void cp15_flush_dcache_all(void)
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{
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cp15_dcache_op(CP15_CACHE_CLEANINVALIDATE);
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}
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uint32_t cp15_cache_size(void)
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{
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uint32_t sets;
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uint32_t ways;
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uint32_t line;
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line = cp15_cache_get_info(&sets, &ways);
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return sets * ways * line;
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}
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@ -1,116 +0,0 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/cp15_clean_dcache.S
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Portions of this file derive from Atmel sample code for the SAMA5D3
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* Cortex-A5 which also has a modified BSD-style license:
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*
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* Copyright (c) 2012, Atmel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
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* be used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* References:
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*
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* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
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* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
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* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
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* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
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* DDI 0406C.b (ID072512)
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "cp15.h"
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.file "cp15_clean_dcache.S"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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.globl cp15_clean_dcache
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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.text
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/****************************************************************************
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* Name: cp15_clean_dcache
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*
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* Description:
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* Clean the data cache within the specified region by flushing the
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* contents of the data cache to memory.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region + 1
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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.globl cp15_clean_dcache
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.type cp15_clean_dcache, function
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cp15_clean_dcache:
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mrc CP15_CTR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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and r3, r3, #0xf
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mov r2, #4
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mov r2, r2, lsl r3 /* Get the cache line size in bytes */
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sub r3, r2, #1 /* R3=Cache line size mask */
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bic r0, r0, r3 /* R0=aligned start address */
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/* Loop, cleaning each cache line by writing its contents to memory */
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1:
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mcr CP15_DCCMVAC(r0) /* Clean data cache line to PoC by VA */
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add r0, r0, r2 /* R12=Next cache line */
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cmp r0, r1 /* Loop until all cache lines have been cleaned */
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blo 1b
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dsb
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bx lr
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.size cp15_clean_dcache, . - cp15_clean_dcache
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.end
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@ -1,127 +0,0 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/cp15_clean_dcache_all.S
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
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* Author: Gregory Nutt <gnutt@nuttx.org>
|
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*
|
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* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_clean_dcache_all.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_clean_dcache_all
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_clean_dcache_all
|
||||
*
|
||||
* Description:
|
||||
* Clean the entire contents of D cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_clean_dcache_all
|
||||
.type cp15_clean_dcache_all, function
|
||||
|
||||
cp15_clean_dcache_all:
|
||||
|
||||
push {r4, r5}
|
||||
|
||||
mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
|
||||
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
|
||||
and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
|
||||
|
||||
ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
|
||||
and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
|
||||
add r5, #4 /* r4=Set/way operation line shfit */
|
||||
|
||||
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
|
||||
and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
|
||||
|
||||
add r4, r1, #1
|
||||
clz r4, r4
|
||||
add r4, #1 /* r4=Set/way operation Way shift */
|
||||
|
||||
way_loop:
|
||||
mov r3, r0 /* Init Sets */
|
||||
set_loop:
|
||||
mov r2, r1, lsl r4 /* r2 = way loop counter << way shift */
|
||||
orr r2, r3, lsl r5 /* r2 = set/way cache operation format */
|
||||
mcr CP15_DCCSW(r2) /* Data Cache Clean by Set/Way */
|
||||
subs r3, r3, #1 /* Subtraction set counter */
|
||||
bcs set_loop /* Keep looping if not */
|
||||
|
||||
subs r1, r1, #1 /* Subtraction the way counter */
|
||||
bcs way_loop /* Keep looping if not */
|
||||
|
||||
dsb
|
||||
pop {r4, r5}
|
||||
bx lr
|
||||
.size cp15_clean_dcache_all, . - cp15_clean_dcache_all
|
||||
.end
|
||||
@ -1,138 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-a/cp15_coherent_dcache.S
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_coherent_dcache.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_coherent_dcache
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_coherent_dcache
|
||||
*
|
||||
* Description:
|
||||
* Ensure that the I and D caches are coherent within specified region
|
||||
* by cleaning the D cache (i.e., flushing the D cache contents to memory
|
||||
* and invalidating the I cache. This is typically used when code has been
|
||||
* written to a memory region, and will be executed.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
* end - virtual end address of region + 1
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_coherent_dcache
|
||||
.type cp15_coherent_dcache, function
|
||||
|
||||
cp15_coherent_dcache:
|
||||
mrc CP15_CTR(r3) /* Read the Cache Type Register */
|
||||
lsr r3, r3, #16 /* Isolate the DMinLine field */
|
||||
and r3, r3, #0xf
|
||||
mov r2, #4
|
||||
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
|
||||
|
||||
sub r3, r2, #1 /* R3=Cache line size mask */
|
||||
bic r12, r0, r3 /* R12=aligned start address */
|
||||
|
||||
/* Loop, flushing each D cache line to memory */
|
||||
1:
|
||||
mcr CP15_DCCMVAU(r12) /* Clean data or unified cache line by VA to PoU */
|
||||
add r12, r12, r2 /* R12=Next cache line */
|
||||
cmp r12, r1 /* Loop until all cache lines have been cleaned */
|
||||
blo 1b
|
||||
|
||||
dsb
|
||||
|
||||
mrc CP15_CTR(r3) /* Read the Cache Type Register */
|
||||
and r3, r3, #0xf /* Isolate the IminLine field */
|
||||
mov r2, #4
|
||||
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
|
||||
|
||||
sub r3, r2, #1 /* R3=Cache line size mask */
|
||||
bic r12, r0, r3 /* R12=aligned start address */
|
||||
|
||||
/* Loop, invalidating each I cache line to memory */
|
||||
1:
|
||||
mcr CP15_ICIMVAU(r12) /* Invalidate instruction cache by VA to PoU */
|
||||
add r12, r12, r2 /* R12=Next cache line */
|
||||
cmp r12, r1 /* Loop until all cache lines have been invalidated */
|
||||
blo 1b
|
||||
|
||||
mov r0, #0
|
||||
mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */
|
||||
mcr CP15_BPIALL(r0) /* Invalidate entire branch predictor array Inner Shareable */
|
||||
|
||||
dsb
|
||||
isb
|
||||
bx lr
|
||||
.size cp15_coherent_dcache, . - cp15_coherent_dcache
|
||||
.end
|
||||
@ -1,116 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-a/cp15_flush_dcache.S
|
||||
*
|
||||
* Copyright (C) 2013, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_flush_dcache.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_flush_dcache
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_flush_dcache
|
||||
*
|
||||
* Description:
|
||||
* Flush the data cache within the specified region by cleaning and
|
||||
* invalidating the D cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
* end - virtual end address of region + 1
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_flush_dcache
|
||||
.type cp15_flush_dcache, function
|
||||
|
||||
cp15_flush_dcache:
|
||||
|
||||
mrc CP15_CTR(r3) /* Read the Cache Type Register */
|
||||
lsr r3, r3, #16 /* Isolate the DMinLine field */
|
||||
and r3, r3, #0xf
|
||||
mov r2, #4
|
||||
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
|
||||
|
||||
sub r3, r2, #1 /* R3=Cache line size mask */
|
||||
bic r0, r0, r3 /* R0=aligned start address */
|
||||
|
||||
/* Loop, cleaning and invaliding each D cache line in the address range */
|
||||
|
||||
1:
|
||||
mcr CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
|
||||
add r0, r0, r2 /* R12=Next cache line */
|
||||
cmp r0, r1 /* Loop until all cache lines have been cleaned */
|
||||
blo 1b
|
||||
|
||||
dsb
|
||||
bx lr
|
||||
.size cp15_flush_dcache, . - cp15_flush_dcache
|
||||
.end
|
||||
@ -1,128 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-a/cp15_flush_dcache_all.S
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_flush_dcache_all.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_flush_dcache_all
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_flush_dcache_all
|
||||
*
|
||||
* Description:
|
||||
* Flush the entire contents of D cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_flush_dcache_all
|
||||
.type cp15_flush_dcache_all, function
|
||||
|
||||
cp15_flush_dcache_all:
|
||||
|
||||
push {r4, r5}
|
||||
|
||||
mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
|
||||
|
||||
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
|
||||
and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
|
||||
|
||||
ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
|
||||
and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
|
||||
add r5, #4 /* r4=Set/way operation line shfit */
|
||||
|
||||
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
|
||||
and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
|
||||
|
||||
add r4, r1, #1
|
||||
clz r4, r4
|
||||
add r4, #1 /* r4=Set/way operation Way shift */
|
||||
|
||||
way_loop:
|
||||
mov r3, r0 /* Init Sets */
|
||||
set_loop:
|
||||
mov r2, r1, lsl r4 /* r2 = way loop counter << way shift */
|
||||
orr r2, r3, lsl r5 /* r2 = set/way cache operation format */
|
||||
mcr CP15_DCCISW(r2) /* Data Cache Clean and Invalidate by Set/Way */
|
||||
subs r3, r3, #1 /* Subtraction set counter */
|
||||
bcs set_loop /* Keep looping if not */
|
||||
|
||||
subs r1, r1, #1 /* Subtraction the way counter */
|
||||
bcs way_loop /* Keep looping if not */
|
||||
|
||||
dsb
|
||||
pop {r4, r5}
|
||||
bx lr
|
||||
.size cp15_flush_dcache_all, . - cp15_flush_dcache_all
|
||||
.end
|
||||
@ -1,123 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-a/cp15_invalidate_dcache.S
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_invalidate_dcache.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_invalidate_dcache
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_invalidate_dcache
|
||||
*
|
||||
* Description:
|
||||
* Invalidate the data cache within the specified region; we will be
|
||||
* performing a DMA operation in this region and we want to purge old data
|
||||
* in the cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
* end - virtual end address of region + 1
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_invalidate_dcache
|
||||
.type cp15_invalidate_dcache, function
|
||||
|
||||
cp15_invalidate_dcache:
|
||||
|
||||
mrc CP15_CTR(r3) /* Read the Cache Type Register */
|
||||
lsr r3, r3, #16 /* Isolate the DMinLine field */
|
||||
and r3, r3, #0xf
|
||||
mov r2, #4
|
||||
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
|
||||
|
||||
sub r3, r2, #1 /* R3=Cache line size mask */
|
||||
tst r0, r3
|
||||
bic r0, r0, r3 /* R0=aligned start address */
|
||||
|
||||
mcrne CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
|
||||
|
||||
tst r1, r3
|
||||
bic r1, r1, r3 /* R0=aligned end address */
|
||||
mcrne CP15_DCCIMVAC(r1) /* Clean and invalidate data cache line by VA to PoC */
|
||||
|
||||
/* Loop, invalidating each D cache line */
|
||||
1:
|
||||
mcr CP15_DCIMVAC(r0) /* Invalidate data cache line by VA to PoC */
|
||||
add r0, r0, r2 /* R12=Next cache line */
|
||||
cmp r0, r1 /* Loop until all cache lines have been invalidate */
|
||||
blo 1b
|
||||
|
||||
dsb
|
||||
bx lr
|
||||
.size cp15_invalidate_dcache, . - cp15_invalidate_dcache
|
||||
.end
|
||||
@ -1,128 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_invalidate_dcache_all.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_invalidate_dcache_all
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_invalidate_dcache_all
|
||||
*
|
||||
* Description:
|
||||
* Invalidate the entire contents of D cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_invalidate_dcache_all
|
||||
.type cp15_invalidate_dcache_all, function
|
||||
|
||||
cp15_invalidate_dcache_all:
|
||||
|
||||
push {r4, r5}
|
||||
|
||||
mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
|
||||
|
||||
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
|
||||
and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
|
||||
|
||||
ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
|
||||
and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
|
||||
add r5, #4 /* r4=Set/way operation line shfit */
|
||||
|
||||
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
|
||||
and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
|
||||
|
||||
add r4, r1, #1
|
||||
clz r4, r4
|
||||
add r4, #1 /* r4=Set/way operation Way shift */
|
||||
|
||||
way_loop:
|
||||
mov r3, r0 /* Init Sets */
|
||||
set_loop:
|
||||
mov r2, r1, lsl r4 /* r2 = way loop counter << way shift */
|
||||
orr r2, r3, lsl r5 /* r2 = set/way cache operation format */
|
||||
mcr CP15_DCISW(r2) /* Data Cache Invalidate by Set/Way */
|
||||
subs r3, r3, #1 /* Subtraction set counter */
|
||||
bcs set_loop /* Keep looping if not */
|
||||
|
||||
subs r1, r1, #1 /* Subtraction the way counter */
|
||||
bcs way_loop /* Keep looping if not */
|
||||
|
||||
dsb
|
||||
pop {r4, r5}
|
||||
bx lr
|
||||
.size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all
|
||||
.end
|
||||
@ -33,16 +33,11 @@ CMN_CSRCS += arm_cache.c arm_dataabort.c arm_doirq.c arm_gicv2.c
|
||||
CMN_CSRCS += arm_initialstate.c arm_prefetchabort.c
|
||||
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
|
||||
CMN_CSRCS += arm_syscall.c arm_tcbinfo.c arm_undefinedinsn.c
|
||||
CMN_CSRCS += arm_perf.c
|
||||
CMN_CSRCS += arm_perf.c cp15_cacheops.c
|
||||
|
||||
# Common C source files
|
||||
|
||||
CMN_ASRCS += arm_head.S arm_vectoraddrexcptn.S
|
||||
CMN_ASRCS += arm_vectors.S cp15_cache_size.S
|
||||
CMN_ASRCS += cp15_clean_dcache_all.S cp15_clean_dcache.S
|
||||
CMN_ASRCS += cp15_coherent_dcache.S cp15_flush_dcache_all.S
|
||||
CMN_ASRCS += cp15_flush_dcache.S cp15_invalidate_dcache_all.S
|
||||
CMN_ASRCS += cp15_invalidate_dcache.S
|
||||
CMN_ASRCS += arm_head.S arm_vectoraddrexcptn.S arm_vectors.S
|
||||
|
||||
ifeq ($(CONFIG_ARMV7R_HAVE_PTM), y)
|
||||
CMN_CSRCS += arm_timer.c
|
||||
|
||||
@ -1,84 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-r/cp15_cache_size.S
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_cache_size.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_cache_size
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_cache_size
|
||||
*
|
||||
* Description:
|
||||
* Get cp15 cache size in byte
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* Cache size in byte
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_cache_size
|
||||
.type cp15_cache_size, function
|
||||
|
||||
cp15_cache_size:
|
||||
|
||||
mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
|
||||
|
||||
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
|
||||
and r2, r3, r0, lsr #13 /* r2=NumSets (number of sets - 1) */
|
||||
add r2, #1
|
||||
|
||||
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
|
||||
and r1, r3, r0, lsr #3 /* r1=(number of ways - 1) */
|
||||
add r1, #1
|
||||
|
||||
ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
|
||||
and r0, r3 /* r0=(Log2LineSize - 2) in word */
|
||||
add r0, #4 /* r0=Log2lineSize in byte */
|
||||
|
||||
mul r2, r1, r2 /* r2=Sets*Ways */
|
||||
lsl r0, r2, r0 /* r0=Sets*Ways*LineSize */
|
||||
|
||||
bx lr
|
||||
|
||||
.size cp15_cache_size, . - cp15_cache_size
|
||||
.end
|
||||
245
arch/arm/src/armv7-r/cp15_cacheops.c
Normal file
245
arch/arm/src/armv7-r/cp15_cacheops.c
Normal file
@ -0,0 +1,245 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-r/cp15_cacheops.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/cache.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "cp15_cacheops.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define CP15_CACHE_INVALIDATE 0
|
||||
#define CP15_CACHE_CLEAN 1
|
||||
#define CP15_CACHE_CLEANINVALIDATE 2
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t ilog2(uint32_t u)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
while (u >>= 1)
|
||||
{
|
||||
i++;
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways)
|
||||
{
|
||||
uint32_t ccsidr = CP15_GET(CCSIDR);
|
||||
|
||||
if (sets)
|
||||
{
|
||||
*sets = ((ccsidr >> 13) & 0x7fff) + 1;
|
||||
}
|
||||
|
||||
if (ways)
|
||||
{
|
||||
*ways = ((ccsidr >> 3) & 0x3ff) + 1;
|
||||
}
|
||||
|
||||
return (1 << ((ccsidr & 0x7) + 2)) * 4;
|
||||
}
|
||||
|
||||
static void cp15_dcache_op_level(uint32_t level, int op)
|
||||
{
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
uint32_t set;
|
||||
uint32_t way;
|
||||
uint32_t line;
|
||||
uint32_t way_shift;
|
||||
uint32_t set_shift;
|
||||
uint32_t val = level << 1;
|
||||
|
||||
/* Select by CSSELR */
|
||||
|
||||
CP15_SET(CSSELR, val);
|
||||
|
||||
/* Get cache info */
|
||||
|
||||
line = cp15_cache_get_info(&sets, &ways);
|
||||
|
||||
way_shift = 32 - ilog2(ways);
|
||||
set_shift = ilog2(line);
|
||||
|
||||
ARM_DSB();
|
||||
|
||||
/* A: Log2(ways)
|
||||
* B: L+S
|
||||
* L: Log2(line)
|
||||
* S: Log2(sets)
|
||||
*
|
||||
* The bits are packed as follows:
|
||||
* 31 31-A B B-1 L L-1 4 3 1 0
|
||||
* |---|-------------|--------|-------|-----|-|
|
||||
* |Way| zeros | Set | zeros |level|0|
|
||||
* |---|-------------|--------|-------|-----|-|
|
||||
*/
|
||||
|
||||
for (way = 0; way < ways; way++)
|
||||
{
|
||||
for (set = 0; set < sets; set++)
|
||||
{
|
||||
val = level << 1;
|
||||
val |= way << way_shift;
|
||||
val |= set << set_shift;
|
||||
|
||||
switch (op)
|
||||
{
|
||||
case CP15_CACHE_INVALIDATE:
|
||||
cp15_invalidate_dcacheline_bysetway(val);
|
||||
break;
|
||||
case CP15_CACHE_CLEAN:
|
||||
cp15_clean_dcache_bysetway(val);
|
||||
break;
|
||||
case CP15_CACHE_CLEANINVALIDATE:
|
||||
cp15_cleaninvalidate_dcacheline(val);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ARM_ISB();
|
||||
}
|
||||
|
||||
static void cp15_dcache_op(int op)
|
||||
{
|
||||
uint32_t clidr = CP15_GET(CLIDR);
|
||||
int level;
|
||||
|
||||
for (level = 0; level < 7; level++)
|
||||
{
|
||||
uint32_t ctype = clidr & 0x7;
|
||||
|
||||
switch (ctype)
|
||||
{
|
||||
case 0x2:
|
||||
case 0x3:
|
||||
case 0x4:
|
||||
cp15_dcache_op_level(level, op);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
clidr >>= 3;
|
||||
if (clidr == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
|
||||
{
|
||||
uint32_t line;
|
||||
|
||||
line = cp15_cache_get_info(NULL, NULL);
|
||||
start &= ~(line - 1);
|
||||
|
||||
ARM_DSB();
|
||||
|
||||
while (start < end)
|
||||
{
|
||||
switch (op)
|
||||
{
|
||||
case CP15_CACHE_INVALIDATE:
|
||||
cp15_invalidate_dcacheline_bymva(start);
|
||||
break;
|
||||
case CP15_CACHE_CLEAN:
|
||||
cp15_clean_dcache_bymva(start);
|
||||
break;
|
||||
case CP15_CACHE_CLEANINVALIDATE:
|
||||
cp15_cleaninvalidate_dcacheline_bymva(start);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
start += line;
|
||||
}
|
||||
|
||||
ARM_ISB();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
|
||||
{
|
||||
cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
|
||||
cp15_invalidate_icache();
|
||||
}
|
||||
|
||||
void cp15_invalidate_dcache(uintptr_t start, uintptr_t end)
|
||||
{
|
||||
cp15_dcache_op_mva(start, end, CP15_CACHE_INVALIDATE);
|
||||
}
|
||||
|
||||
void cp15_invalidate_dcache_all(void)
|
||||
{
|
||||
cp15_dcache_op(CP15_CACHE_INVALIDATE);
|
||||
}
|
||||
|
||||
void cp15_clean_dcache(uintptr_t start, uintptr_t end)
|
||||
{
|
||||
cp15_dcache_op_mva(start, end, CP15_CACHE_CLEAN);
|
||||
}
|
||||
|
||||
void cp15_clean_dcache_all(void)
|
||||
{
|
||||
cp15_dcache_op(CP15_CACHE_CLEAN);
|
||||
}
|
||||
|
||||
void cp15_flush_dcache(uintptr_t start, uintptr_t end)
|
||||
{
|
||||
cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
|
||||
}
|
||||
|
||||
void cp15_flush_dcache_all(void)
|
||||
{
|
||||
cp15_dcache_op(CP15_CACHE_CLEANINVALIDATE);
|
||||
}
|
||||
|
||||
uint32_t cp15_cache_size(void)
|
||||
{
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
uint32_t line;
|
||||
|
||||
line = cp15_cache_get_info(&sets, &ways);
|
||||
|
||||
return sets * ways * line;
|
||||
}
|
||||
@ -1,116 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-r/cp15_clean_dcache.S
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_clean_dcache.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_clean_dcache
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_clean_dcache
|
||||
*
|
||||
* Description:
|
||||
* Clean the data cache within the specified region by flushing the
|
||||
* contents of the data cache to memory.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
* end - virtual end address of region + 1
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_clean_dcache
|
||||
.type cp15_clean_dcache, function
|
||||
|
||||
cp15_clean_dcache:
|
||||
|
||||
mrc CP15_CTR(r3) /* Read the Cache Type Register */
|
||||
lsr r3, r3, #16 /* Isolate the DMinLine field */
|
||||
and r3, r3, #0xf
|
||||
mov r2, #4
|
||||
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
|
||||
|
||||
sub r3, r2, #1 /* R3=Cache line size mask */
|
||||
bic r0, r0, r3 /* R0=aligned start address */
|
||||
|
||||
/* Loop, cleaning each cache line by writing its contents to memory */
|
||||
|
||||
1:
|
||||
mcr CP15_DCCMVAC(r0) /* Clean data cache line to PoC by VA */
|
||||
add r0, r0, r2 /* R12=Next cache line */
|
||||
cmp r0, r1 /* Loop until all cache lines have been cleaned */
|
||||
blo 1b
|
||||
|
||||
dsb
|
||||
bx lr
|
||||
.size cp15_clean_dcache, . - cp15_clean_dcache
|
||||
.end
|
||||
@ -1,129 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-r/cp15_clean_dcache_all.S
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_clean_dcache_all.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_clean_dcache_all
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_clean_dcache_all
|
||||
*
|
||||
* Description:
|
||||
* clean the entire contents of D cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_clean_dcache_all
|
||||
.type cp15_clean_dcache_all, function
|
||||
|
||||
cp15_clean_dcache_all:
|
||||
|
||||
push {r4, r5}
|
||||
|
||||
mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
|
||||
|
||||
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
|
||||
and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
|
||||
|
||||
ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
|
||||
and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
|
||||
add r5, #4 /* r4=Set/way operation line shfit */
|
||||
|
||||
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
|
||||
and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
|
||||
|
||||
add r4, r1, #1
|
||||
clz r4, r4
|
||||
add r4, #1 /* r4=Set/way operation Way shift */
|
||||
|
||||
way_loop:
|
||||
mov r3, r0 /* Init Sets */
|
||||
set_loop:
|
||||
mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
|
||||
orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
|
||||
mcr CP15_DCCSW(r2) /* Data Cache Clean by Set/Way */
|
||||
subs r3, r3, #1 /* Subtraction set counter */
|
||||
bcs set_loop /* Keep looping if not */
|
||||
|
||||
subs r1, r1, #1 /* Subtraction the way counter */
|
||||
bcs way_loop /* Keep looping if not */
|
||||
|
||||
dsb
|
||||
pop {r4, r5}
|
||||
bx lr
|
||||
.size cp15_clean_dcache_all, . - cp15_clean_dcache_all
|
||||
.end
|
||||
|
||||
@ -1,140 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-r/cp15_coherent_dcache.S
|
||||
*
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_coherent_dcache.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_coherent_dcache
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_coherent_dcache
|
||||
*
|
||||
* Description:
|
||||
* Ensure that the I and D caches are coherent within specified region
|
||||
* by cleaning the D cache (i.e., flushing the D cache contents to memory
|
||||
* and invalidating the I cache. This is typically used when code has been
|
||||
* written to a memory region, and will be executed.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
* end - virtual end address of region + 1
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_coherent_dcache
|
||||
.type cp15_coherent_dcache, function
|
||||
|
||||
cp15_coherent_dcache:
|
||||
mrc CP15_CTR(r3) /* Read the Cache Type Register */
|
||||
lsr r3, r3, #16 /* Isolate the DMinLine field */
|
||||
and r3, r3, #0xf
|
||||
mov r2, #4
|
||||
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
|
||||
|
||||
sub r3, r2, #1 /* R3=Cache line size mask */
|
||||
bic r12, r0, r3 /* R12=aligned start address */
|
||||
|
||||
/* Loop, flushing each D cache line to memory */
|
||||
1:
|
||||
mcr CP15_DCCMVAU(r12) /* Clean data or unified cache line by VA to PoU */
|
||||
add r12, r12, r2 /* R12=Next cache line */
|
||||
cmp r12, r1 /* Loop until all cache lines have been cleaned */
|
||||
blo 1b
|
||||
|
||||
dsb
|
||||
|
||||
mrc CP15_CTR(r3) /* Read the Cache Type Register */
|
||||
and r3, r3, #0xf /* Isolate the IminLine field */
|
||||
mov r2, #4
|
||||
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
|
||||
|
||||
sub r3, r2, #1 /* R3=Cache line size mask */
|
||||
bic r12, r0, r3 /* R12=aligned start address */
|
||||
|
||||
/* Loop, invalidating each I cache line to memory */
|
||||
1:
|
||||
mcr CP15_ICIMVAU(r12) /* Invalidate instruction cache by VA to PoU */
|
||||
add r12, r12, r2 /* R12=Next cache line */
|
||||
cmp r12, r1 /* Loop until all cache lines have been invalidated */
|
||||
blo 1b
|
||||
|
||||
mov r0, #0
|
||||
#ifdef CONFIG_SMP
|
||||
mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */
|
||||
#endif
|
||||
mcr CP15_BPIALL(r0) /* Invalidate all branch predictors */
|
||||
|
||||
dsb
|
||||
isb
|
||||
bx lr
|
||||
.size cp15_coherent_dcache, . - cp15_coherent_dcache
|
||||
.end
|
||||
@ -1,116 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-r/cp15_flush_dcache.S
|
||||
*
|
||||
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_flush_dcache.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_flush_dcache
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_flush_dcache
|
||||
*
|
||||
* Description:
|
||||
* Flush the data cache within the specified region by cleaning and
|
||||
* invalidating the D cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
* end - virtual end address of region + 1
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_flush_dcache
|
||||
.type cp15_flush_dcache, function
|
||||
|
||||
cp15_flush_dcache:
|
||||
|
||||
mrc CP15_CTR(r3) /* Read the Cache Type Register */
|
||||
lsr r3, r3, #16 /* Isolate the DMinLine field */
|
||||
and r3, r3, #0xf
|
||||
mov r2, #4
|
||||
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
|
||||
|
||||
sub r3, r2, #1 /* R3=Cache line size mask */
|
||||
bic r0, r0, r3 /* R0=aligned start address */
|
||||
|
||||
/* Loop, cleaning and invaliding each D cache line in the address range */
|
||||
|
||||
1:
|
||||
mcr CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
|
||||
add r0, r0, r2 /* R12=Next cache line */
|
||||
cmp r0, r1 /* Loop until all cache lines have been cleaned */
|
||||
blo 1b
|
||||
|
||||
dsb
|
||||
bx lr
|
||||
.size cp15_flush_dcache, . - cp15_flush_dcache
|
||||
.end
|
||||
@ -1,129 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-r/cp15_flush_dcache_all.S
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_flush_dcache_all.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_flush_dcache_all
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_flush_dcache_all
|
||||
*
|
||||
* Description:
|
||||
* Flush the entire contents of D cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_flush_dcache_all
|
||||
.type cp15_flush_dcache_all, function
|
||||
|
||||
cp15_flush_dcache_all:
|
||||
|
||||
push {r4, r5}
|
||||
|
||||
mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
|
||||
|
||||
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
|
||||
and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
|
||||
|
||||
ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
|
||||
and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
|
||||
add r5, #4 /* r4=Set/way operation line shfit */
|
||||
|
||||
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
|
||||
and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
|
||||
|
||||
add r4, r1, #1
|
||||
clz r4, r4
|
||||
add r4, #1 /* r4=Set/way operation Way shift */
|
||||
|
||||
way_loop:
|
||||
mov r3, r0 /* Init Sets */
|
||||
set_loop:
|
||||
mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
|
||||
orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
|
||||
mcr CP15_DCCISW(r2) /* Data Cache Clean and Invalidate by Set/Way */
|
||||
subs r3, r3, #1 /* Subtraction set counter */
|
||||
bcs set_loop /* Keep looping if not */
|
||||
|
||||
subs r1, r1, #1 /* Subtraction the way counter */
|
||||
bcs way_loop /* Keep looping if not */
|
||||
|
||||
dsb
|
||||
pop {r4, r5}
|
||||
bx lr
|
||||
.size cp15_flush_dcache_all, . - cp15_flush_dcache_all
|
||||
.end
|
||||
|
||||
@ -1,123 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-r/cp15_invalidate_dcache.S
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_invalidate_dcache.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_invalidate_dcache
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_invalidate_dcache
|
||||
*
|
||||
* Description:
|
||||
* Invalidate the data cache within the specified region; we will be
|
||||
* performing a DMA operation in this region and we want to purge old data
|
||||
* in the cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
* end - virtual end address of region + 1
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_invalidate_dcache
|
||||
.type cp15_invalidate_dcache, function
|
||||
|
||||
cp15_invalidate_dcache:
|
||||
|
||||
mrc CP15_CTR(r3) /* Read the Cache Type Register */
|
||||
lsr r3, r3, #16 /* Isolate the DMinLine field */
|
||||
and r3, r3, #0xf
|
||||
mov r2, #4
|
||||
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
|
||||
|
||||
sub r3, r2, #1 /* R3=Cache line size mask */
|
||||
tst r0, r3
|
||||
bic r0, r0, r3 /* R0=aligned start address */
|
||||
|
||||
mcrne CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
|
||||
|
||||
tst r1, r3
|
||||
bic r1, r1, r3 /* R0=aligned end address */
|
||||
mcrne CP15_DCCIMVAC(r1) /* Clean and invalidate data cache line by VA to PoC */
|
||||
|
||||
/* Loop, invalidating each D cache line */
|
||||
1:
|
||||
mcr CP15_DCIMVAC(r0) /* Invalidate data cache line by VA to PoC */
|
||||
add r0, r0, r2 /* R12=Next cache line */
|
||||
cmp r0, r1 /* Loop until all cache lines have been invalidate */
|
||||
blo 1b
|
||||
|
||||
dsb
|
||||
bx lr
|
||||
.size cp15_invalidate_dcache, . - cp15_invalidate_dcache
|
||||
.end
|
||||
@ -1,128 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Portions of this file derive from Atmel sample code for the SAMA5D3
|
||||
* Cortex-A5 which also has a modified BSD-style license:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* References:
|
||||
*
|
||||
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
|
||||
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
|
||||
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
|
||||
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
|
||||
* DDI 0406C.b (ID072512)
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
.file "cp15_invalidate_dcache_all.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_invalidate_dcache_all
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
.text
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_invalidate_dcache_all
|
||||
*
|
||||
* Description:
|
||||
* Invalidate the entire contents of D cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl cp15_invalidate_dcache_all
|
||||
.type cp15_invalidate_dcache_all, function
|
||||
|
||||
cp15_invalidate_dcache_all:
|
||||
|
||||
push {r4, r5}
|
||||
|
||||
mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
|
||||
|
||||
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
|
||||
and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
|
||||
|
||||
ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
|
||||
and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
|
||||
add r5, #4 /* r4=Set/way operation line shfit */
|
||||
|
||||
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
|
||||
and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
|
||||
|
||||
add r4, r1, #1
|
||||
clz r4, r4
|
||||
add r4, #1 /* r4=Set/way operation Way shift */
|
||||
|
||||
way_loop:
|
||||
mov r3, r0 /* Init Sets */
|
||||
set_loop:
|
||||
mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
|
||||
orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
|
||||
mcr CP15_DCISW(r2) /* Data Cache Invalidate by Set/Way */
|
||||
subs r3, r3, #1 /* Subtraction set counter */
|
||||
bcs set_loop /* Keep looping if not */
|
||||
|
||||
subs r1, r1, #1 /* Subtraction the way counter */
|
||||
bcs way_loop /* Keep looping if not */
|
||||
|
||||
dsb
|
||||
pop {r4, r5}
|
||||
bx lr
|
||||
.size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all
|
||||
.end
|
||||
Loading…
Reference in New Issue
Block a user