Support for the Atmel SAM4E family. From Mitko
This commit is contained in:
Gregory Nutt
parent
1db36fb2f4
commit
6e1523cc45
@ -6030,3 +6030,6 @@
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* include/nuttx/audio/i2s.h, arch/arm/src/sama5/sam_ssc.c, and
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drivers/audio/i2schar.c: Improvied I2S interface design: Simplified
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audio buffer queuing (2013-11-10).
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* arch/arm/src/sam34 and arch/arm/include/sam34: Basic support for
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the Atmal SAM4E family. From Mitko (2013-11-11).
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@ -49,6 +49,34 @@
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/* Get customizations for each supported chip */
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/* AT91SAM3U Family *****************************************************************/
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/* FEATURE SAM3U4E SAM3U2E SAM3U1E SAM3U4C SAM3U2C SAM3U1C
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* ----------- -------- -------- -------- -------- -------- --------
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* Flash 2x128KB 128KB 64KB 2x128KB 128KB 64KB
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* SRAM 32+16KB 16+16KB 16KB 32+16KB 16+16KB 16KB
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* NFC Yes Yes Yes Yes Yes Yes
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* NFC SRAM 4KB 4KB 4KB 4KB 4KB 4KB
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* Package LQFP144 LQFP144 LQFP144 LQFP100 LQFP100 LQFP100
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* LFBGA144 LFBGA144 LFBGA144 LFBGA100 LFBGA100 LFBGA100
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* No. PIOs 96 96 96 57 57 57
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* SHDN Pin Yes Yes Yes No No No
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* EMAC --- --- --- --- --- ---
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* EBI Yes Yes Yes Yes Yes Yes
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* EBI data 8/16 8/16 8/16 8 8 8
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* EBI ch 4 4 4 2 2 2
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* EBI addr 24 24 24 8 8 8
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* SDRAM --- --- --- --- --- ---
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* DMA 4 4 4 4 4 4
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* 12-bit ADC 8ch 8ch 8ch 4ch 4ch 4ch
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* 10-bit ADC 8ch 8ch 8ch 4ch 4ch 4ch
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* 32-bit Timer 1 1 1 1 1 1
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* 16-bit Timer 3 3 3 3 3 3
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* PDC Channels 17 17 17 17 17 17
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* USART 4 4 4 3 3 3
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* UART 2 2 2 1 1 1
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* SPI 1 1 1 1 1 1
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* SSC 1 1 1 1 1 1
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* HSMCI 8 bit 8 bit 8 bit 4 bit 4 bit 4 bit
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*/
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#if defined(CONFIG_ARCH_CHIP_ATSAM3U4E)
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@ -70,6 +98,106 @@
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# define SAM32_NUDPFS 0 /* No USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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#elif defined(CONFIG_ARCH_CHIP_ATSAM3U2E)
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/* Internal memory */
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# define SAM34_FLASH_SIZE (128*1024) /* 128KB */
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# define SAM34_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAM34_SRAM1_SIZE (16*1024) /* 16KB */
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# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
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/* Peripherals */
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# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
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# define SAM34_NMCI2 1 /* 1 memory card interface */
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# define SAM32_NSLCD 0 /* No segment LCD interface */
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# define SAM32_NAESA 0 /* No advanced encryption standard */
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# define SAM32_NUDPHS 1 /* One USB high speed device */
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# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
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# define SAM32_NUDPFS 0 /* No USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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#elif defined(CONFIG_ARCH_CHIP_ATSAM3U1E)
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/* Internal memory */
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# define SAM34_FLASH_SIZE (64*1024) /* 64KB */
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# define SAM34_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAM34_SRAM1_SIZE 0 /* No SRAM1 */
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# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
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/* Peripherals */
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# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
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# define SAM34_NMCI2 1 /* 1 memory card interface */
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# define SAM32_NSLCD 0 /* No segment LCD interface */
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# define SAM32_NAESA 0 /* No advanced encryption standard */
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# define SAM32_NUDPHS 1 /* One USB high speed device */
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# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
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# define SAM32_NUDPFS 0 /* No USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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#elif defined(CONFIG_ARCH_CHIP_ATSAM3U4C)
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/* Internal memory */
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# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
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# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAM34_SRAM1_SIZE (16*1024) /* 16KB */
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# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
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/* Peripherals */
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# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
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# define SAM34_NMCI2 1 /* 1 memory card interface */
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# define SAM32_NSLCD 0 /* No segment LCD interface */
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# define SAM32_NAESA 0 /* No advanced encryption standard */
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# define SAM32_NUDPHS 1 /* One USB high speed device */
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# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
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# define SAM32_NUDPFS 0 /* No USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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#elif defined(CONFIG_ARCH_CHIP_ATSAM3U2C)
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/* Internal memory */
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# define SAM34_FLASH_SIZE (128*1024) /* 128KB */
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# define SAM34_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAM34_SRAM1_SIZE (16*1024) /* 16KB */
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# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
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/* Peripherals */
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# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
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# define SAM34_NMCI2 1 /* 1 memory card interface */
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# define SAM32_NSLCD 0 /* No segment LCD interface */
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# define SAM32_NAESA 0 /* No advanced encryption standard */
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# define SAM32_NUDPHS 1 /* One USB high speed device */
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# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
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# define SAM32_NUDPFS 0 /* No USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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#elif defined(CONFIG_ARCH_CHIP_ATSAM3U1C)
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/* Internal memory */
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# define SAM34_FLASH_SIZE (64*1024) /* 64KB */
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# define SAM34_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAM34_SRAM1_SIZE 0 /* No SRAM1 */
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# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
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/* Peripherals */
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# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
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# define SAM34_NMCI2 1 /* 1 memory card interface */
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# define SAM32_NSLCD 0 /* No segment LCD interface */
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# define SAM32_NAESA 0 /* No advanced encryption standard */
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# define SAM32_NUDPHS 1 /* One USB high speed device */
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# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
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# define SAM32_NUDPFS 0 /* No USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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/* AT91SAM3X/3A Families ************************************************************/
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/* FEATURE SAM3X8E SAM3X8C SAM3X4E SAM3X4C SAM3A8C SAM3A4C
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* ------------ -------- -------- -------- -------- -------- --------
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@ -88,7 +216,7 @@
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* 12-bit ADC 16ch 16ch 16ch 16ch 16ch 16ch
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* 12-bit DAC 2ch 2ch 2ch 2ch 2ch 2ch
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* 32-bit Timer 9 9 9 9 9 9
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* PDC Channels 17 15 17 15 15 15
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* PDC Channels 17 17 17 15 15 15
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* USART 3 3 3 3 3 3
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* UART 2 1 2 1 1 1
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* SPI 1/4+3 1/4+3 1/4+3 1/4+3 1/4+3 1/4+3
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@ -557,6 +685,112 @@
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# define SAM32_NUDPFS 1 /* 1 USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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/* AT91SAM4E Family *****************************************************************/
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/* FEATURE SAM4E16E SAM4E8E SAM4E16C SAM4E8C
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* ----------- --------- -------- -------- --------
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* Flash 1024KB 512KB 1024KB 512KB
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* SRAM 128KB 128KB 128KB 128KB
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* SMC Yes Yes Yes Yes
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* GMCC 2KB 2KB 2KB 2KB
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* Package LQFP144 LQFP144 LQFP100 LQFP100
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* LFBGA144 LFBGA144 TFBGA100 TFBGA100
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* No. PIOs 117 117 79 79
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* SHDN Pin No No No No
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* EMAC MII MII MII MII
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* CAN 2 2 1 1
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* EBI Yes Yes No No
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* EBI data 8 8 --- ---
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* EBI ch 4 4 --- ---
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* EBI addr 24 24 --- ---
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* SDRAM --- --- --- ---
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* DMA 4 4 4 4
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* 16-bit ADC0 16ch 16ch 6ch 6ch
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* 16-bit ADC1 8ch 8ch 4ch 4ch
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* 12-bit DAC 2ch 2ch 2ch 2ch
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* Timer 9 9 3 3
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* PDC Channels 24+9 24+9 21+9 21+9
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* USART 2 2 2 2
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* UART 2 2 2 2
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* SPI 1 1 1 1
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* HSMCI 4 bit 4 bit 4 bit 4 bit
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*/
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#elif defined(CONFIG_ARCH_CHIP_ATSAM4E16E)
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/* Internal memory */
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# define SAM34_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
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# define SAM34_SRAM1_SIZE 0 /* None */
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# define SAM34_NFCSRAM_SIZE 0 /* None */
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/* Peripherals */
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# define SAM34_NDMACHAN 24 /* 24 PDC Channels */
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# define SAM34_NMCI2 1 /* 1 memory card interface */
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# define SAM32_NSLCD 0 /* No segment LCD interface */
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# define SAM32_NAESA 0 /* No advanced encryption standard */
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# define SAM32_NUDPHS 0 /* No USB high speed device */
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# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
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# define SAM32_NUDPFS 1 /* 1 USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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#elif defined(CONFIG_ARCH_CHIP_ATSAM4E8E)
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/* Internal memory */
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# define SAM34_FLASH_SIZE (512*1024) /* 512KB */
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# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
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# define SAM34_SRAM1_SIZE 0 /* None */
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# define SAM34_NFCSRAM_SIZE 0 /* None */
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/* Peripherals */
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# define SAM34_NDMACHAN 24 /* 24 PDC Channels */
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# define SAM34_NMCI2 1 /* 1 memory card interface */
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# define SAM32_NSLCD 0 /* No segment LCD interface */
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# define SAM32_NAESA 0 /* No advanced encryption standard */
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# define SAM32_NUDPHS 0 /* No USB high speed device */
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# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
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# define SAM32_NUDPFS 1 /* 1 USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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#elif defined(CONFIG_ARCH_CHIP_ATSAM4E16C)
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/* Internal memory */
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# define SAM34_FLASH_SIZE (1024*1024) /* 1024KB */
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# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
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# define SAM34_SRAM1_SIZE 0 /* None */
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# define SAM34_NFCSRAM_SIZE 0 /* None */
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/* Peripherals */
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# define SAM34_NDMACHAN 21 /* 21 PDC Channels */
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# define SAM34_NMCI2 1 /* 1 memory card interface */
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# define SAM32_NSLCD 0 /* No segment LCD interface */
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# define SAM32_NAESA 0 /* No advanced encryption standard */
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# define SAM32_NUDPHS 0 /* No USB high speed device */
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# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
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# define SAM32_NUDPFS 1 /* 1 USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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#elif defined(CONFIG_ARCH_CHIP_ATSAM4E8C)
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/* Internal memory */
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# define SAM34_FLASH_SIZE (512*1024) /* 512KB */
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# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
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# define SAM34_SRAM1_SIZE 0 /* None */
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# define SAM34_NFCSRAM_SIZE 0 /* None */
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/* Peripherals */
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# define SAM34_NDMACHAN 21 /* 21 PDC Channels */
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# define SAM34_NMCI2 1 /* 1 memory card interface */
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# define SAM32_NSLCD 0 /* No segment LCD interface */
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# define SAM32_NAESA 0 /* No advanced encryption standard */
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# define SAM32_NUDPHS 0 /* No USB high speed device */
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# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
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# define SAM32_NUDPFS 1 /* 1 USB full speed device */
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# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
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#else
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# error "Unknown SAM3/4 chip type"
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#endif
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@ -37,7 +37,6 @@
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_SAM34_IRQ_H
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#define __ARCH_ARM_INCLUDE_SAM34_IRQ_H
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@ -85,6 +84,8 @@
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# include <arch/sam34/sam4l_irq.h>
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#elif defined(CONFIG_ARCH_CHIP_SAM4S)
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# include <arch/sam34/sam4s_irq.h>
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#elif defined(CONFIG_ARCH_CHIP_SAM4E)
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# include <arch/sam34/sam4e_irq.h>
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#else
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# error Unrecognized SAM architecture
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#endif
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@ -117,4 +118,3 @@ extern "C" {
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#endif
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#endif /* __ARCH_ARM_INCLUDE_SAM34_IRQ_H */
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333
arch/arm/include/sam34/sam4e_irq.h
Executable file
333
arch/arm/include/sam34/sam4e_irq.h
Executable file
@ -0,0 +1,333 @@
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/****************************************************************************************
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* arch/arm/include/sam34/sam4e_irq.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM4E_IRQ_H
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#define __ARCH_ARM_INCLUDE_SAM34_SAM4E_IRQ_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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/****************************************************************************************
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* Definitions
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****************************************************************************************/
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/* SAM4E Peripheral Identifiers */
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#define SAM_PID_SUPC (0) /* Supply Controller */
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#define SAM_PID_RSTC (1) /* Reset Controller */
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#define SAM_PID_RTC (2) /* Real Time Clock */
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#define SAM_PID_RTT (3) /* Real Time Timer */
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#define SAM_PID_WDT (4) /* Watchdog Timer */
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#define SAM_PID_PMC (5) /* Power Management Controller */
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#define SAM_PID_EEFC (6) /* Enhanced Embedded Flash Controller */
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#define SAM_PID_UART0 (7) /* Universal Asynchronous Receiver Transmitter 0 */
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#define SAM_PID_SMC (8) /* Static Memory Controller */
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#define SAM_PID_PIOA (9) /* Parallel I/O Controller A */
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#define SAM_PID_PIOB (10) /* Parallel I/O Controller B */
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#define SAM_PID_PIOC (11) /* Parallel I/O Controller C */
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#define SAM_PID_PIOD (12) /* Parallel I/O Controller D */
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#define SAM_PID_PIOE (13) /* Parallel I/O Controller E */
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#define SAM_PID_USART0 (14) /* USART 0 */
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#define SAM_PID_USART1 (15) /* USART 1 */
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#define SAM_PID_HSMCI (16) /* High Speed Multimedia Card Interface */
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#define SAM_PID_TWI0 (17) /* Two-Wire Interface 0 */
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#define SAM_PID_TWI1 (18) /* Two-Wire Interface 1 */
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#define SAM_PID_SPI0 (19) /* Serial Peripheral Interface */
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#define SAM_PID_DMAC (20) /* DMAC */
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#define SAM_PID_TC0 (21) /* Timer Counter 0 */
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#define SAM_PID_TC1 (22) /* Timer Counter 1 */
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#define SAM_PID_TC2 (23) /* Timer Counter 2 */
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#define SAM_PID_TC3 (24) /* Timer Counter 3 */
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#define SAM_PID_TC4 (25) /* Timer Counter 4 */
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#define SAM_PID_TC5 (26) /* Timer Counter 5 */
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#define SAM_PID_TC6 (27) /* Timer Counter 6 */
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#define SAM_PID_TC7 (28) /* Timer Counter 7 */
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#define SAM_PID_TC8 (29) /* Timer Counter 8 */
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#define SAM_PID_AFEC0 (30) /* Analog Front End 0 */
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#define SAM_PID_AFEC1 (31) /* Analog Front End 1 */
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#define SAM_PID_DACC (32) /* Digital to Analog Converter */
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#define SAM_PID_ACC (33) /* Analog Comparator */
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#define SAM_PID_ARM (34) /* FPU signals: FPIXC, FPOFC, FPUFC, FPIOC, FPDZC,FPIDC, FPIXC */
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#define SAM_PID_UDP (35) /* USB Device */
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#define SAM_PID_PWM (36) /* PWM */
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#define SAM_PID_CAN0 (37) /* CAN0 */
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#define SAM_PID_CAN1 (38) /* CAN1 */
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#define SAM_PID_AES (39) /* AES */
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#define SAM_PID_EMAC (44) /* EMAC */
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#define SAM_PID_UART1 (45) /* UART */
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#define NR_PIDS (46) /* Number of peripheral identifiers */
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/* External interrupts (priority levels >= 256*/
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#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* Supply Controller */
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#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */
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#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */
|
||||
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */
|
||||
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */
|
||||
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */
|
||||
#define SAM_IRQ_EEFC (SAM_IRQ_EXTINT+SAM_PID_EEFC) /* Enhanced Embedded Flash Controller */
|
||||
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter 0 */
|
||||
#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */
|
||||
#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */
|
||||
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */
|
||||
#define SAM_IRQ_PIOD (SAM_IRQ_EXTINT+SAM_PID_PIOD) /* Parallel I/O Controller D */
|
||||
#define SAM_IRQ_PIOE (SAM_IRQ_EXTINT+SAM_PID_PIOE) /* Parallel I/O Controller E */
|
||||
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* USART 0 */
|
||||
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* USART 1 */
|
||||
#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */
|
||||
#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* Two-Wire Interface 0 */
|
||||
#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* Two-Wire Interface 1 */
|
||||
#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* Serial Peripheral Interface */
|
||||
#define SAM_IRQ_DMAC (SAM_IRQ_EXTINT+SAM_PID_DMAC) /* DMAC */
|
||||
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */
|
||||
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */
|
||||
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */
|
||||
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* Timer Counter 3 */
|
||||
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* Timer Counter 4 */
|
||||
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* Timer Counter 5 */
|
||||
#define SAM_IRQ_TC6 (SAM_IRQ_EXTINT+SAM_PID_TC6) /* Timer Counter 6 */
|
||||
#define SAM_IRQ_TC7 (SAM_IRQ_EXTINT+SAM_PID_TC7) /* Timer Counter 7 */
|
||||
#define SAM_IRQ_TC8 (SAM_IRQ_EXTINT+SAM_PID_TC8) /* Timer Counter 8 */
|
||||
#define SAM_IRQ_AFEC0 (SAM_IRQ_EXTINT+SAM_PID_AFEC0) /* Analog Front End 0 */
|
||||
#define SAM_IRQ_AFEC1 (SAM_IRQ_EXTINT+SAM_PID_AFEC1) /* Analog Front End 1 */
|
||||
#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+SAM_PID_DACC) /* Digital to Analog Converter */
|
||||
#define SAM_IRQ_ACC (SAM_IRQ_EXTINT+SAM_PID_ACC) /* Analog Comparator */
|
||||
#define SAM_IRQ_ARM (SAM_IRQ_EXTINT+SAM_PID_ARM) /* FPU signals: FPIXC, FPOFC, FPUFC, FPIOC, FPDZC,FPIDC, FPIXC */
|
||||
#define SAM_IRQ_UDP (SAM_IRQ_EXTINT+SAM_PID_UDP) /* USB Device */
|
||||
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PWM */
|
||||
#define SAM_IRQ_CAN0 (SAM_IRQ_EXTINT+SAM_PID_CAN0) /* CAN0 */
|
||||
#define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT+SAM_PID_CAN1) /* CAN1 */
|
||||
#define SAM_IRQ_AES (SAM_IRQ_EXTINT+SAM_PID_AES) /* AES */
|
||||
#define SAM_IRQ_EMAC (SAM_IRQ_EXTINT+SAM_PID_EMAC) /* EMAC */
|
||||
#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* UART */
|
||||
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
|
||||
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */
|
||||
|
||||
/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */
|
||||
|
||||
#ifdef CONFIG_GPIOA_IRQ
|
||||
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT)
|
||||
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
|
||||
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
|
||||
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
|
||||
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
|
||||
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
|
||||
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
|
||||
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
|
||||
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
|
||||
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
|
||||
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
|
||||
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
|
||||
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
|
||||
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
|
||||
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
|
||||
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
|
||||
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
|
||||
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
|
||||
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
|
||||
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
|
||||
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
|
||||
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
|
||||
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
|
||||
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
|
||||
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
|
||||
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
|
||||
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
|
||||
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
|
||||
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
|
||||
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
|
||||
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
|
||||
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
|
||||
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
|
||||
# define SAM_NGPIOAIRQS 32
|
||||
#else
|
||||
# define SAM_NGPIOAIRQS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIOB_IRQ
|
||||
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS)
|
||||
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
|
||||
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
|
||||
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
|
||||
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
|
||||
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
|
||||
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
|
||||
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
|
||||
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
|
||||
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
|
||||
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
|
||||
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
|
||||
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
|
||||
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
|
||||
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
|
||||
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
|
||||
# define SAM_NGPIOBIRQS 15
|
||||
#else
|
||||
# define SAM_NGPIOBIRQS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIOC_IRQ
|
||||
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
|
||||
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
|
||||
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
|
||||
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
|
||||
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
|
||||
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
|
||||
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
|
||||
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
|
||||
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
|
||||
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
|
||||
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
|
||||
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
|
||||
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
|
||||
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
|
||||
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
|
||||
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
|
||||
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
|
||||
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
|
||||
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
|
||||
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
|
||||
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
|
||||
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
|
||||
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
|
||||
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
|
||||
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
|
||||
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
|
||||
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
|
||||
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
|
||||
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
|
||||
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
|
||||
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
|
||||
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
|
||||
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
|
||||
# define SAM_NGPIOCIRQS 32
|
||||
#else
|
||||
# define SAM_NGPIOCIRQS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIOD_IRQ
|
||||
# define SAM_IRQ_GPIOD_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
|
||||
# define SAM_IRQ_PD0 (SAM_IRQ_GPIOD_PINS+0) /* GPIOD, PIN 0 */
|
||||
# define SAM_IRQ_PD1 (SAM_IRQ_GPIOD_PINS+1) /* GPIOD, PIN 1 */
|
||||
# define SAM_IRQ_PD2 (SAM_IRQ_GPIOD_PINS+2) /* GPIOD, PIN 2 */
|
||||
# define SAM_IRQ_PD3 (SAM_IRQ_GPIOD_PINS+3) /* GPIOD, PIN 3 */
|
||||
# define SAM_IRQ_PD4 (SAM_IRQ_GPIOD_PINS+4) /* GPIOD, PIN 4 */
|
||||
# define SAM_IRQ_PD5 (SAM_IRQ_GPIOD_PINS+5) /* GPIOD, PIN 5 */
|
||||
# define SAM_IRQ_PD6 (SAM_IRQ_GPIOD_PINS+6) /* GPIOD, PIN 6 */
|
||||
# define SAM_IRQ_PD7 (SAM_IRQ_GPIOD_PINS+7) /* GPIOD, PIN 7 */
|
||||
# define SAM_IRQ_PD8 (SAM_IRQ_GPIOD_PINS+8) /* GPIOD, PIN 8 */
|
||||
# define SAM_IRQ_PD9 (SAM_IRQ_GPIOD_PINS+9) /* GPIOD, PIN 9 */
|
||||
# define SAM_IRQ_PD10 (SAM_IRQ_GPIOD_PINS+10) /* GPIOD, PIN 10 */
|
||||
# define SAM_IRQ_PD11 (SAM_IRQ_GPIOD_PINS+11) /* GPIOD, PIN 11 */
|
||||
# define SAM_IRQ_PD12 (SAM_IRQ_GPIOD_PINS+12) /* GPIOD, PIN 12 */
|
||||
# define SAM_IRQ_PD13 (SAM_IRQ_GPIOD_PINS+13) /* GPIOD, PIN 13 */
|
||||
# define SAM_IRQ_PD14 (SAM_IRQ_GPIOD_PINS+14) /* GPIOD, PIN 14 */
|
||||
# define SAM_IRQ_PD15 (SAM_IRQ_GPIOD_PINS+15) /* GPIOD, PIN 15 */
|
||||
# define SAM_IRQ_PD16 (SAM_IRQ_GPIOD_PINS+16) /* GPIOD, PIN 16 */
|
||||
# define SAM_IRQ_PD17 (SAM_IRQ_GPIOD_PINS+17) /* GPIOD, PIN 17 */
|
||||
# define SAM_IRQ_PD18 (SAM_IRQ_GPIOD_PINS+18) /* GPIOD, PIN 18 */
|
||||
# define SAM_IRQ_PD19 (SAM_IRQ_GPIOD_PINS+19) /* GPIOD, PIN 19 */
|
||||
# define SAM_IRQ_PD20 (SAM_IRQ_GPIOD_PINS+20) /* GPIOD, PIN 20 */
|
||||
# define SAM_IRQ_PD21 (SAM_IRQ_GPIOD_PINS+21) /* GPIOD, PIN 21 */
|
||||
# define SAM_IRQ_PD22 (SAM_IRQ_GPIOD_PINS+22) /* GPIOD, PIN 22 */
|
||||
# define SAM_IRQ_PD23 (SAM_IRQ_GPIOD_PINS+23) /* GPIOD, PIN 23 */
|
||||
# define SAM_IRQ_PD24 (SAM_IRQ_GPIOD_PINS+24) /* GPIOD, PIN 24 */
|
||||
# define SAM_IRQ_PD25 (SAM_IRQ_GPIOD_PINS+25) /* GPIOD, PIN 25 */
|
||||
# define SAM_IRQ_PD26 (SAM_IRQ_GPIOD_PINS+26) /* GPIOD, PIN 26 */
|
||||
# define SAM_IRQ_PD27 (SAM_IRQ_GPIOD_PINS+27) /* GPIOD, PIN 27 */
|
||||
# define SAM_IRQ_PD28 (SAM_IRQ_GPIOD_PINS+28) /* GPIOD, PIN 28 */
|
||||
# define SAM_IRQ_PD29 (SAM_IRQ_GPIOD_PINS+29) /* GPIOD, PIN 29 */
|
||||
# define SAM_IRQ_PD30 (SAM_IRQ_GPIOD_PINS+30) /* GPIOD, PIN 30 */
|
||||
# define SAM_IRQ_PD31 (SAM_IRQ_GPIOD_PINS+31) /* GPIOD, PIN 31 */
|
||||
# define SAM_NGPIODIRQS 32
|
||||
#else
|
||||
# define SAM_NGPIODIRQS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIOE_IRQ
|
||||
# define SAM_IRQ_GPIOE_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
|
||||
# define SAM_IRQ_PE0 (SAM_IRQ_GPIOE_PINS+0) /* GPIOE, PIN 0 */
|
||||
# define SAM_IRQ_PE1 (SAM_IRQ_GPIOE_PINS+1) /* GPIOE, PIN 1 */
|
||||
# define SAM_IRQ_PE2 (SAM_IRQ_GPIOE_PINS+2) /* GPIOE, PIN 2 */
|
||||
# define SAM_IRQ_PE3 (SAM_IRQ_GPIOE_PINS+3) /* GPIOE, PIN 3 */
|
||||
# define SAM_IRQ_PE4 (SAM_IRQ_GPIOE_PINS+4) /* GPIOE, PIN 4 */
|
||||
# define SAM_IRQ_PE5 (SAM_IRQ_GPIOE_PINS+5) /* GPIOE, PIN 5 */
|
||||
# define SAM_NGPIOEIRQS 6
|
||||
#else
|
||||
# define SAM_NGPIOEIRQS 0
|
||||
#endif
|
||||
|
||||
/* Total number of IRQ numbers */
|
||||
|
||||
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
|
||||
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
|
||||
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Variables
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM4E_IRQ_H */
|
||||
@ -15,6 +15,31 @@ config ARCH_CHIP_ATSAM3U4E
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_CHIP_SAM3U
|
||||
|
||||
config ARCH_CHIP_ATSAM3U4C
|
||||
bool "ATSAM3U4C"
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_CHIP_SAM3U
|
||||
|
||||
config ARCH_CHIP_ATSAM3U2E
|
||||
bool "ATSAM3U2E"
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_CHIP_SAM3U
|
||||
|
||||
config ARCH_CHIP_ATSAM3U2C
|
||||
bool "ATSAM3U2C"
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_CHIP_SAM3U
|
||||
|
||||
config ARCH_CHIP_ATSAM3U1E
|
||||
bool "ATSAM3U1E"
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_CHIP_SAM3U
|
||||
|
||||
config ARCH_CHIP_ATSAM3U1C
|
||||
bool "ATSAM3U1C"
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_CHIP_SAM3U
|
||||
|
||||
config ARCH_CHIP_ATSAM3X8E
|
||||
bool "ATSAMSAM3X8E"
|
||||
select ARCH_CORTEXM3
|
||||
@ -163,6 +188,26 @@ config ARCH_CHIP_ATSAM4S8B
|
||||
select ARCH_CORTEXM4
|
||||
select ARCH_CHIP_SAM4S
|
||||
|
||||
config ARCH_CHIP_ATSAM4E16E
|
||||
bool "ATSAM4E16E"
|
||||
select ARCH_CORTEXM4
|
||||
select ARCH_CHIP_SAM4E
|
||||
|
||||
config ARCH_CHIP_ATSAM4E16C
|
||||
bool "ATSAM4E16C"
|
||||
select ARCH_CORTEXM4
|
||||
select ARCH_CHIP_SAM4E
|
||||
|
||||
config ARCH_CHIP_ATSAM4E8E
|
||||
bool "ATSAM4E8E"
|
||||
select ARCH_CORTEXM4
|
||||
select ARCH_CHIP_SAM4E
|
||||
|
||||
config ARCH_CHIP_ATSAM4E8C
|
||||
bool "ATSAM4E8C"
|
||||
select ARCH_CORTEXM4
|
||||
select ARCH_CHIP_SAM4E
|
||||
|
||||
endchoice # AT91SAM3/4 Chip Selection
|
||||
|
||||
config ARCH_CHIP_SAM3U
|
||||
|
||||
@ -681,7 +681,7 @@ static void ssc_bufsem_take(struct sam_ssc_s *priv)
|
||||
* there are no available buffer containers.
|
||||
*
|
||||
* Assumptions:
|
||||
* The caller does NOT have exclusive acces to the SSC state structure.
|
||||
* The caller does NOT have exclusive access to the SSC state structure.
|
||||
* That would result in a deadlock!
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user