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arch/arm/src/imxrt: This commit fixes more issues with the i.MX RT GPIO IRQ.

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imxrt_gpioirq.c
    - Add check for interrupt mask register before dispatching ISR. The GPIO_ISR bits are set independent of the GPIO_IMR bits.
  imxrt_irq.c
    - fixed a range check for extint in function imxrt_irqinfo().
This commit is contained in:
Jake Choy 2018-05-01 14:25:47 -06:00 committed by Gregory Nutt
parent b5411d96e6
commit 6e1d43dd11
2 changed files with 21 additions and 17 deletions
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32
arch/arm/src/imxrt/imxrt_gpioirq.c
View File

@ -164,7 +164,8 @@ static int imxrt_gpio1_0_15_interrupt(int irq, FAR void *context,
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO1_ISR) & 0x0000fffff;
status = getreg32(IMXRT_GPIO1_ISR) & getreg32(IMXRT_GPIO1_IMR) &
0x0000fffff;
/* Decode the pending interrupts */
@ -200,7 +201,8 @@ static int imxrt_gpio1_16_31_interrupt(int irq, FAR void *context,
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO1_ISR) & 0xffff0000;
status = getreg32(IMXRT_GPIO1_ISR) & getreg32(IMXRT_GPIO1_IMR) &
0xffff0000;
/* Decode the pending interrupts */
@ -236,7 +238,8 @@ static int imxrt_gpio2_0_15_interrupt(int irq, FAR void *context,
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO2_ISR) & 0x0000fffff;
status = getreg32(IMXRT_GPIO2_ISR) & getreg32(IMXRT_GPIO2_IMR) &
0x0000fffff;
/* Decode the pending interrupts */
@ -272,7 +275,8 @@ static int imxrt_gpio2_16_31_interrupt(int irq, FAR void *context,
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO2_ISR) & 0xffff0000;
status = getreg32(IMXRT_GPIO2_ISR) & getreg32(IMXRT_GPIO2_IMR) &
0xffff0000;
/* Decode the pending interrupts */
@ -308,7 +312,8 @@ static int imxrt_gpio3_0_15_interrupt(int irq, FAR void *context,
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO3_ISR) & 0x0000fffff;
status = getreg32(IMXRT_GPIO3_ISR) & getreg32(IMXRT_GPIO3_IMR) &
0x0000fffff;
/* Decode the pending interrupts */
@ -344,7 +349,8 @@ static int imxrt_gpio3_16_31_interrupt(int irq, FAR void *context,
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO3_ISR) & 0xffff0000;
status = getreg32(IMXRT_GPIO3_ISR) & getreg32(IMXRT_GPIO3_IMR) &
0xffff0000;
/* Decode the pending interrupts */
@ -380,7 +386,8 @@ static int imxrt_gpio4_0_15_interrupt(int irq, FAR void *context,
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO4_ISR) & 0x0000fffff;
status = getreg32(IMXRT_GPIO4_ISR) & getreg32(IMXRT_GPIO4_IMR) &
0x0000fffff;
/* Decode the pending interrupts */
@ -416,7 +423,8 @@ static int imxrt_gpio4_16_31_interrupt(int irq, FAR void *context,
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO4_ISR) & 0xffff0000;
status = getreg32(IMXRT_GPIO4_ISR) & getreg32(IMXRT_GPIO4_IMR) &
0xffff0000;
/* Decode the pending interrupts */
@ -594,9 +602,7 @@ int imxrt_gpioirq_enable(int irq)
ret = imxrt_gpio_info(irq, &regaddr, &pin);
if (ret >= 0)
{
regval = getreg32(regaddr);
regval |= (1 << pin);
putreg32(regval, regaddr);
modifyreg32(regaddr, 0, 1 << pin);
}
return ret;
@ -620,9 +626,7 @@ int imxrt_gpioirq_disable(int irq)
ret = imxrt_gpio_info(irq, &regaddr, &pin);
if (ret >= 0)
{
regval = getreg32(regaddr);
regval &= ~(1 << pin);
putreg32(regval, regaddr);
modifyreg32(regaddr, 1 << pin, 0);
}
return ret;

6
arch/arm/src/imxrt/imxrt_irq.c
View File

@ -296,14 +296,14 @@ static int imxrt_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= IMXRT_IRQ_EXTINT)
{
if (extint < IMXRT_IRQ_NEXTINT)
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else
#if IMXRT_IRQ_NEXTINT > 32
if (extint < 32)
if (extint < 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
@ -319,7 +319,7 @@ static int imxrt_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
else
#endif
#if IMXRT_IRQ_NEXTINT > 96
if (extint < 96)
if (extint < 128)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);