Add clock initializatin structure
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2462 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -1259,6 +1259,7 @@
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#define CGU_DYNSEL_ARM926LPITRANS (1 << 2) /* Bit 2: ARM926 instr transfers can enable high-speed */
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#define CGU_DYNSEL_DMAREADY (1 << 1) /* Bit 1: dma last transfers can enable high-speed */
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#define CGU_DYNSEL_DMATRANS (1 << 0) /* Bit 0: dma transfers can enable high-speed */
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#define CGU_DYNSEL_ALLBITS (0x1ff)
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/* CGU configuration register bit definitions ***************************************************/
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/* Power and oscillator control registers */
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@ -67,15 +67,15 @@
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#define CLKID_SYSBASE_LAST CLKID_INTCCLK
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#define _D0B(id) _RBIT(id,CLKID_SYSBASE_FIRST)
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#define CLKID_AHB0APB0_FIRST CLKID_AHB2APB0ASYNCPCLK /* Domain 1: AHB0APB0_BASE */
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#define CLKID_AHB0APB0_FIRST CLKID_AHB2APB0PCLK /* Domain 1: AHB0APB0_BASE */
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#define CLKID_AHB0APB0_LAST CLKID_RNGPCLK
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#define _D1B(id) _RBIT(id,CLKID_AHB0APB0_FIRST)
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#define CLKID_AHB0APB1_FIRST CLKID_AHB2APB1ASYNCPCLK /* Domain 2: AHB0APB1_BASE */
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#define CLKID_AHB0APB1_FIRST CLKID_AHB2APB1PCLK /* Domain 2: AHB0APB1_BASE */
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#define CLKID_AHB0APB1_LAST CLKID_I2C1PCLK
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#define _D2B(id) _RBIT(id,CLKID_AHB0APB1_FIRST)
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#define CLKID_AHB0APB2_FIRST CLKID_AHB2APB2ASYNCPCLK /* Domain 3: AHB0APB2_BASE */
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#define CLKID_AHB0APB2_FIRST CLKID_AHB2APB2PCLK /* Domain 3: AHB0APB2_BASE */
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#define CLKID_AHB0APB2_LAST CLKID_SPIPCLKGATED
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#define _D3B(id) _RBIT(id,CLKID_AHB0APB2_FIRST)
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@ -174,7 +174,8 @@
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#define FRACDIV_BASE11_CNT 0 /* No fractional divider available */
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#define CGU_NFRACDIV 24 /* Number of fractional dividers */
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#define CGU_NFRACDIV 24 /* Number of fractional dividers: 0-23 */
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#define CGU_NDYNFRACDIV 7 /* Number of dynamic fractional dividers: 0-6 */
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#define FDCNDX_INVALID -1 /* Indicates an invalid fractional
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* divider index */
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@ -404,6 +405,105 @@ enum lpc313x_resetid_e
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RESETID_INTCRST, /* 55 Interrupt Controller */
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};
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/* This structure describes one CGU fractional divider configuration */
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struct lpc313x_fdivconfig_s
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{
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uint8_t stretch; /* Fractional divider stretch enable. */
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uint8_t n; /* Fractional divider nominal nominator */
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uint16_t m; /* Fractional divider nominal denominator */
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};
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/* The structure describes the configuration of one CGU sub-domain */
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struct lpc313x_subdomainconfig_s
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{
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struct lpc313x_fdivconfig_s fdiv; /* Fractional divider settings */
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uint32_t clkset; /* Bitset of all clocks in the sub-domain */
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};
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/* CGU clock initilization structure. Describes the platform-specific
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* configuration of every clock domain.
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*/
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struct lpc313x_clkinit_s
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{
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struct
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{
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uint8_t finsel;
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struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE0_CNT];
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} domain0;
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struct
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{
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uint8_t finsel;
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struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE1_CNT];
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} domain1;
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struct
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{
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uint8_t finsel;
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struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE2_CNT];
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} domain2;
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struct
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{
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uint8_t finsel;
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struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE3_CNT];
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} domain3;
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struct
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{
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uint8_t finsel;
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struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE4_CNT];
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} domain4;
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struct
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{
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uint8_t finsel;
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struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE5_CNT];
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} domain5;
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struct
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{
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uint8_t finsel;
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struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE6_CNT];
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} domain6;
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struct
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{
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uint8_t finsel;
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struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE7_CNT];
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} domain7;
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struct
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{
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uint8_t finsel;
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} domain8;
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struct
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{
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uint8_t finsel;
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} domain9;
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struct
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{
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uint8_t finsel;
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struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE10_CNT];
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} domain10;
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struct
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{
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uint8_t finsel;
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} domain11;
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struct
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{
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uint16_t sel;
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struct lpc313x_fdivconfig_s cfg;
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} dynfdiv[CGU_NDYNFRACDIV];
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};
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/* This structure is used to pass PLL configuration data to
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* lpc313x_pllconfig()
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*/
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@ -40,7 +40,7 @@ CFLAGS += -I$(TOPDIR)/sched
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ASRCS =
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AOBJS = $(ASRCS:.S=$(OBJEXT))
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CSRCS = up_boot.c up_buttons.c up_leds.c up_mem.c up_spi.c
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CSRCS = up_boot.c up_buttons.c up_clkinit.c up_leds.c up_mem.c up_spi.c
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ifeq ($(CONFIG_EXAMPLES_NSH_ARCHINIT),y)
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CSRCS += up_nsh.c
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endif
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439
configs/ea3131/src/up_clkinit.c
Executable file
439
configs/ea3131/src/up_clkinit.c
Executable file
@ -0,0 +1,439 @@
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/****************************************************************************
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* configs/ea3131/src/up_clkinit.c
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* arch/arm/src/board/up_clkinit.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* References:
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* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
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* - NXP lpc313x.cdl.drivers.zip example driver code
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "lpc313x_cgu.h"
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#include "lpc313x_cgudrvr.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Sub-domain Clock Bitsets *************************************************/
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/* The following bitsets group clocks into bitsets associated with each
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* domain and fractional divider subdomain.
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*
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* Domain 0 (DOMAINID_SYS), Clocks 0 - 29, Fraction dividers 0-6. Clocks not
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* defined in the clock sets will be sourced with SYS_BASE_CLK.
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*/
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/* Domain 0, Fractional divider 0: */
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#define CGU_CLKSET_DOMAIN0_DIV0 \
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(_D0B(CLKID_APB0CLK)|_D0B(CLKID_APB1CLK)|_D0B(CLKID_APB2CLK)|\
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_D0B(CLKID_APB3CLK)|_D0B(CLKID_APB4CLK)|_D0B(CLKID_AHB2INTCCLK)|\
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_D0B(CLKID_AHB0CLK)|_D0B(CLKID_DMAPCLK)|_D0B(CLKID_DMACLKGATED)|\
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_D0B(CLKID_NANDFLASHS0CLK)|_D0B(CLKID_NANDFLASHPCLK)|\
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_D0B(CLKID_ARM926BUSIFCLK)|_D0B(CLKID_SDMMCHCLK)|_D0B(CLKID_USBOTGAHBCLK)|\
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_D0B(CLKID_ISRAM0CLK)|_D0B(CLKID_ISRAM1CLK)|_D0B(CLKID_ISROMCLK)|\
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_D0B(CLKID_MPMCCFGCLK)|_D0B(CLKID_MPMCCFGCLK2)|_D0B(CLKID_INTCCLK))
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/* Domain 0, Fractional divider 1: */
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#define CGU_CLKSET_DOMAIN0_DIV1 \
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(_D0B(CLKID_ARM926CORECLK))
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/* Domain 0, Fractional divider 2: */
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#define CGU_CLKSET_DOMAIN0_DIV2 \
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(_D0B(CLKID_NANDFLASHAESCLK)|_D0B(CLKID_NANDFLASHNANDCLK))
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/* Domain 0, Fractional divider 3: */
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#define CGU_CLKSET_DOMAIN0_DIV3 \
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(_D0B(CLKID_NANDFLASHECCCLK))
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/* Domain 0, Fractional divider 4: */
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#define CGU_CLKSET_DOMAIN0_DIV4 \
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(_D0B(CLKID_SDMMCCCLKIN))
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/* Domain 0, Fractional divider 5: */
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#define CGU_CLKSET_DOMAIN0_DIV5 \
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(_D0B(CLKID_CLOCKOUT))
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/* Domain 0, Fractional divider 6: */
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#define CGU_CLKSET_DOMAIN0_DIV6 \
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(_D0B(CLKID_EBICLK))
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/* Domain 1 (DOMAINID_AHB0APB0), Clocks 30-39, Fraction dividers 7-8. Clocks
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* not defined in the clock sets will be sourced with AHB_APB0_BASE_CLK.
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*/
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/* Domain 1, Fractional divider 7: */
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#define CGU_CLKSET_DOMAIN1_DIV7 \
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(_D1B(CLKID_ADCCLK))
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/* Domain 1, Fractional divider 8: */
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#define CGU_CLKSET_DOMAIN1_DIV8 \
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(_D1B(CLKID_AHB2APB0PCLK)|_D1B(CLKID_EVENTROUTERPCLK)|\
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_D1B(CLKID_ADCPCLK)|_D1B(CLKID_WDOGPCLK)|_D1B(CLKID_IOCONFPCLK)|\
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_D1B(CLKID_CGUPCLK)|_D1B(CLKID_SYSCREGPCLK)|_D1B(CLKID_OTPPCLK)|\
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_D1B(CLKID_RNGPCLK))
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/* Domain 2 (DOMAINID_AHB0APB1), Clocks 40-49, Fraction dividers 9-10. Clocks
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* not defined in the clock sets will be sourced with AHB_APB1_BASE_CLK.
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*/
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/* Domain 2, Fractional divider 9: */
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#define CGU_CLKSET_DOMAIN2_DIV9 \
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(_D2B(CLKID_AHB2APB1PCLK)|_D2B(CLKID_TIMER0PCLK)|_D2B(CLKID_TIMER1PCLK)|\
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_D2B(CLKID_TIMER2PCLK)|_D2B(CLKID_TIMER3PCLK)|_D2B(CLKID_PWMPCLK)|\
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_D2B(CLKID_PWMPCLKREGS)|_D2B(CLKID_I2C0PCLK)|_D2B(CLKID_I2C1PCLK))
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/* Domain 2, Fractional divider 10: */
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#define CGU_CLKSET_DOMAIN2_DIV10 \
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(_D2B(CLKID_PWMCLK))
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/* Domain 3 (DOMAINID_AHB0APB2), Clocks 50-57, Fraction dividers 11-13. Clocks
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* not defined in the clock sets will be sourced with AHB_APB2_BASE_CLK.
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*/
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/* Domain 3, Fractional divider 11: */
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#define CGU_CLKSET_DOMAIN3_DIV11 \
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( _D3B(CLKID_AHB2APB2PCLK)|_D3B(CLKID_PCMPCLK)|_D3B(CLKID_PCMAPBPCLK)|\
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_D3B(CLKID_UARTAPBCLK)|_D3B(CLKID_LCDPCLK)|_D3B(CLKID_SPIPCLK)|\
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_D3B(CLKID_SPIPCLKGATED))
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/* Domain 3, Fractional divider 12: */
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#define CGU_CLKSET_DOMAIN3_DIV12 \
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(_D3B(CLKID_LCDCLK))
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/* Domain 3, Fractional divider 13: */
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#define CGU_CLKSET_DOMAIN3_DIV13 \
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(0)
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/* Domain 4 (DOMAINID_AHB0APB3), Clocks 58-70, Fraction divider 14. Clocks
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* not defined in the clock sets will be sourced with AHB_APB3_BASE_CLK.
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*/
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#define CGU_CLKSET_DOMAIN4_DIV14 \
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(_D4B(CLKID_AHB2APB3PCLK)|_D4B(CLKID_I2SCFGPCLK)|_D4B(CLKID_EDGEDETPCLK)|\
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_D4B(CLKID_I2STXFIFO0PCLK)|_D4B(CLKID_I2STXIF0PCLK)|_D4B(CLKID_I2STXFIFO1PCLK)|\
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_D4B(CLKID_I2STXIF1PCLK)|_D4B(CLKID_I2SRXFIFO0PCLK)|_D4B(CLKID_I2SRXIF0PCLK)|\
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_D4B(CLKID_I2SRXFIFO1PCLK)|_D4B(CLKID_I2SRXIF1PCLK))
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/* Domain 5 (DOMAINID_PCM), Clock 71, Fraction divider 15. Clocks not
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* defined in the clock sets will be sourced with AHB_APB3_BASE_CLK.
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*/
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#define CGU_CLKSET_DOMAIN5_DIV15 \
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(_D5B(CLKID_PCMCLKIP))
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/* Domain 6 (DOMAINID_UART), Clock 72, Fraction divider 16. Clocks mpt
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* defined in the clock sets will be sourced with UART_BASE_CLK.
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*/
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#define CGU_CLKSET_DOMAIN6_DIV16 \
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(0)
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/* Domain 7 (DOMAINID_CLK1024FS), Clocks 73-86, Fraction dividers 17-22. Clocks
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* not defined in the clock sets will be sourced with CLK1024FS_BASE_CLK.
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*/
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/* Domain 7, Fractional divider 17: */
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#define CGU_CLKSET_DOMAIN7_DIV17 \
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( _D7B(CLKID_I2SEDGEDETECTCLK)|_D7B(CLKID_I2STXWS0)|_D7B(CLKID_I2STXWS1)|\
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_D7B(CLKID_I2SRXWS0)|_D7B(CLKID_I2SRXWS1))
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/* Domain 7, Fractional divider 18: */
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#define CGU_CLKSET_DOMAIN7_DIV18 \
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( _D7B(CLKID_I2STXBCK0N)|_D7B(CLKID_I2STXBCK1N))
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/* Domain 7, Fractional divider 19: */
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#define CGU_CLKSET_DOMAIN7_DIV19 \
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( _D7B(CLKID_I2STXCLK0)|_D7B(CLKID_CLK256FS))
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/* Domain 7, Fractional divider 20: */
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#define CGU_CLKSET_DOMAIN7_DIV20 \
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( _D7B(CLKID_I2SRXBCK0N)|_D7B(CLKID_I2SRXBCK1N))
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/* Domain 7, Fractional divider 21: */
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#define CGU_CLKSET_DOMAIN7_DIV21 \
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(0)
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/* Domain 7, Fractional divider 22: */
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#define CGU_CLKSET_DOMAIN7_DIV22 \
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(0)
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/* Domain 8 (DOMAINID_BCK0, clock 87, and domain 9 (DOMAINID_BCK1), clock 88,
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* are directly connected
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*/
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/* Domain 10 (DOMAINID_SPI), Clocks 89-90, Fraction divider 23. Clocks
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* not defined in the clock sets will be sourced with SPI_CLK_BASE_CLK.
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*/
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#define CGU_CLKSET_DOMAIN10_DIV23 \
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( _D10B(CLKID_SPICLK)|_D10B(CLKID_SPICLKGATED))
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/* Domain 11 (DOMAINID_SYSCLKO, clock 91, is directly connected */
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* Default clock configuration for the EA3131 board
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*
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* FFAST: 12MHz
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* MASTER PLL Freq: 180MHz;
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* AUDIOPLL Freq: 1024Fs, Fs = 44.1kHz
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*
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* Domain Input Subdomain Divider Ratio
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* 0 - DOMAIN_SYS MASTER PLL(HPLL1) DOMAIN0_DIV0 1/2
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* DOMAIN0_DIV1 1
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* DOMAIN0_DIV2 1/2
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* DOMAIN0_DIV3 1/4
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* DOMAIN0_DIV4 1/4
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* DOMAIN0_DIV5 1/2
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* DOMAIN0_DIV6 1/2
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*
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* 1 - DOMAIN_AHB0APB0 FFAST DOMAIN1_DIV7 1/38
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* DOMAIN1_DIV8 1/2
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*
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* 2 - DOMAIN_AHB0APB1 FFAST DOMAIN2_DIV9 1/2
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* DOMAIN2_DIV10 1/2
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*
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* 3 - DOMAIN_AHB0APB2 MASTER PLL(HPLL1) DOMAIN3_DIV11 1/2
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* DOMAIN3_DIV12 1/40
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* DOMAIN3_DIV13 1 (not used)
|
||||
*
|
||||
* 4 - DOMAIN_AHB0APB3 FFAST DOMAIN4_DIV14 1/2
|
||||
*
|
||||
* 5 - DOMAIN_PCM MASTER PLL(HPLL1) DOMAIN5_DIV15 1/2
|
||||
*
|
||||
* 6 - DOMAIN_UART FFAST DOMAIN6_DIV16 1
|
||||
*
|
||||
* 7 - DOMAIN_CLCK1024FS AUDIO PLL(HPLL0) DOMAIN7_DIV17 1/256
|
||||
* DOMAIN7_DIV18 1/4
|
||||
* DOMAIN7_DIV19 1
|
||||
* DOMAIN7_DIV20 1/4
|
||||
* DOMAIN7_DIV21 1/32
|
||||
* DOMAIN7_DIV22 1/2
|
||||
*
|
||||
* 8 - DOMAIN_I2SRXBCK0 I2SRX_BCK0 - -
|
||||
*
|
||||
* 9 - DOMAIN_I2SRXBCK1 I2SRX_BCK1 - -
|
||||
*
|
||||
* 10 - DOMAIN_SPI MASTER PLL(HPLL1) DOMAIN10_DIV23 1/2
|
||||
*
|
||||
* 11 - DOMAIN_SYSCLKO FFAST - -
|
||||
*/
|
||||
|
||||
const struct lpc313x_clkinit_s g_cgu_default_clks =
|
||||
{
|
||||
/* Domain 0 (DOMAINID_SYS), Clocks 0 - 29, Fraction dividers 0-6 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_HPPLL1,
|
||||
{
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN0_DIV0},
|
||||
{{0, 0, 0}, CGU_CLKSET_DOMAIN0_DIV1},
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN0_DIV2},
|
||||
{{1, 1, 4}, CGU_CLKSET_DOMAIN0_DIV3},
|
||||
{{1, 1, 4}, CGU_CLKSET_DOMAIN0_DIV4},
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN0_DIV5},
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN0_DIV6}
|
||||
}
|
||||
},
|
||||
|
||||
/* Domain 1 (DOMAINID_AHB0APB0), Clocks 30-39, Fraction dividers 7-8 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_FFAST,
|
||||
{
|
||||
{{1, 1, 38}, CGU_CLKSET_DOMAIN1_DIV7},
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN1_DIV8}
|
||||
}
|
||||
},
|
||||
|
||||
/* Domain 2 (DOMAINID_AHB0APB1), Clocks 40-49, Fraction dividers 9-10 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_FFAST,
|
||||
{
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN2_DIV9},
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN2_DIV10}
|
||||
}
|
||||
},
|
||||
|
||||
/* Domain 3 (DOMAINID_AHB0APB2), Clocks 50-57, Fraction dividers 11-13 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_HPPLL1,
|
||||
{
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN3_DIV11},
|
||||
{{1, 1, 40}, CGU_CLKSET_DOMAIN3_DIV12},
|
||||
{{0, 0, 0}, CGU_CLKSET_DOMAIN3_DIV13}
|
||||
}
|
||||
},
|
||||
|
||||
/* Domain 4 (DOMAINID_AHB0APB3), Clocks 58-70, Fraction divider 14 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_FFAST,
|
||||
{
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN4_DIV14}
|
||||
}
|
||||
},
|
||||
|
||||
/* Domain 5 (DOMAINID_PCM), Clock 71, Fraction divider 15 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_HPPLL1,
|
||||
{
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN5_DIV15}
|
||||
}
|
||||
},
|
||||
|
||||
/* Domain 6 (DOMAINID_UART), Clock 72, Fraction divider 16 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_FFAST,
|
||||
{
|
||||
{{0, 0, 0}, CGU_CLKSET_DOMAIN6_DIV16}
|
||||
}
|
||||
},
|
||||
|
||||
/* Domain 7 (DOMAINID_CLK1024FS), Clocks 73-86, Fraction dividers 17-22 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_HPPLL0,
|
||||
{
|
||||
{{1, 1, 256}, CGU_CLKSET_DOMAIN7_DIV17},
|
||||
{{1, 1, 4}, CGU_CLKSET_DOMAIN7_DIV18},
|
||||
{{0, 0, 0}, CGU_CLKSET_DOMAIN7_DIV19},
|
||||
{{1, 1, 4}, CGU_CLKSET_DOMAIN7_DIV20},
|
||||
{{1, 1, 32}, CGU_CLKSET_DOMAIN7_DIV21},
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN7_DIV22}
|
||||
}
|
||||
},
|
||||
|
||||
/* Domain 8 (DOMAINID_BCK0, clock 87 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_I2SRXBCK0
|
||||
},
|
||||
|
||||
/* Domain 9 (DOMAINID_BCK1, clock 88 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_I2SRXBCK1
|
||||
},
|
||||
|
||||
/* Domain 10 (DOMAINID_SPI), Clocks 89-90, Fraction divider 23 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_HPPLL1,
|
||||
{
|
||||
{{1, 1, 2}, CGU_CLKSET_DOMAIN10_DIV23}
|
||||
}
|
||||
},
|
||||
|
||||
/* Domain 11 (DOMAINID_SYSCLKO, clock 91 */
|
||||
|
||||
{
|
||||
CGU_FREQIN_FFAST
|
||||
},
|
||||
|
||||
/* Dynamic fractional divider configuration (7) */
|
||||
|
||||
{
|
||||
{
|
||||
CGU_DYNSEL_ALLBITS, {1, 1, 64}
|
||||
},
|
||||
{
|
||||
CGU_DYNSEL_ALLBITS, {0, 0, 0}
|
||||
},
|
||||
{
|
||||
CGU_DYNSEL_ALLBITS, {1, 1, 3}
|
||||
},
|
||||
{
|
||||
CGU_DYNSEL_ALLBITS, {1, 1, 6}
|
||||
},
|
||||
{
|
||||
CGU_DYNSEL_ALLBITS, {1, 1, 6}
|
||||
},
|
||||
{
|
||||
CGU_DYNSEL_ALLBITS, {1, 1, 6}
|
||||
},
|
||||
{
|
||||
CGU_DYNSEL_ALLBITS, {1, 1, 3}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_ledinit
|
||||
****************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user