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Misc changes to get a clean compilation after incorporating all of Bob Doison's changes

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This commit is contained in:
Gregory Nutt 2014-04-22 10:38:08 -06:00
parent 9f9f790d0a
commit 6e94a4e1e2
2 changed files with 27 additions and 38 deletions
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61
arch/arm/src/sam34/chip/sam_tc.h
View File

@ -133,10 +133,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC1_EMR (SAM_TC1_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC1_FMR (SAM_TC1_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC1_WPMR (SAM_TC1_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TC_CMR_OFFSET)
@ -157,10 +153,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC2_EMR (SAM_TC2_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC2_FMR (SAM_TC2_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC2_WPMR (SAM_TC2_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC3_CCR (SAM_TC3_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC3_CMR (SAM_TC3_BASE+SAM_TC_CMR_OFFSET)
@ -181,10 +173,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC3_EMR (SAM_TC3_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC3_FMR (SAM_TC3_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC3_WPMR (SAM_TC3_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC4_CCR (SAM_TC4_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC4_CMR (SAM_TC4_BASE+SAM_TC_CMR_OFFSET)
@ -205,10 +193,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC4_EMR (SAM_TC4_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC4_FMR (SAM_TC4_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC4_WPMR (SAM_TC4_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC5_CCR (SAM_TC5_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC5_CMR (SAM_TC5_BASE+SAM_TC_CMR_OFFSET)
@ -229,10 +213,6 @@
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC5_EMR (SAM_TC5_BASE+SAM_TC_EMR_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC5_FMR (SAM_TC5_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC5_WPMR (SAM_TC5_BASE+SAM_TC_WPMR_OFFSET)
#endif
#define SAM_TC6_CCR (SAM_TC6_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC6_CMR (SAM_TC6_BASE+SAM_TC_CMR_OFFSET)
@ -297,23 +277,32 @@
/* Timer common registers */
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TC0_BCR (SAM_TC0_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC0_BMR (SAM_TC0_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC0_QIER (SAM_TC0_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC0_QIDR (SAM_TC0_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC0_QIMR (SAM_TC0_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC0_QISR (SAM_TC0_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC0_FMR (SAM_TC0_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC0_WPMR (SAM_TC0_BASE+SAM_TC_WPMR_OFFSET)
# define SAM_TC0_BCR (SAM_TC012_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC0_BMR (SAM_TC012_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC0_QIER (SAM_TC012_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC0_QIDR (SAM_TC012_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC0_QIMR (SAM_TC012_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC0_QISR (SAM_TC012_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC0_FMR (SAM_TC012_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC0_WPMR (SAM_TC012_BASE+SAM_TC_WPMR_OFFSET)
# define SAM_TC1_BCR (SAM_TC3_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC1_BMR (SAM_TC3_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC1_QIER (SAM_TC3_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC1_QIDR (SAM_TC3_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC1_QIMR (SAM_TC3_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC1_QISR (SAM_TC3_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC1_FMR (SAM_TC3_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC1_WPMR (SAM_TC3_BASE+SAM_TC_WPMR_OFFSET)
# define SAM_TC1_BCR (SAM_TC345_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC1_BMR (SAM_TC345_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC1_QIER (SAM_TC345_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC1_QIDR (SAM_TC345_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC1_QIMR (SAM_TC345_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC1_QISR (SAM_TC345_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC1_FMR (SAM_TC345_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC1_WPMR (SAM_TC345_BASE+SAM_TC_WPMR_OFFSET)
# define SAM_TC2_BCR (SAM_TC678_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC2_BMR (SAM_TC678_BASE+SAM_TC_BMR_OFFSET)
# define SAM_TC2_QIER (SAM_TC678_BASE+SAM_TC_QIER_OFFSET)
# define SAM_TC2_QIDR (SAM_TC678_BASE+SAM_TC_QIDR_OFFSET)
# define SAM_TC2_QIMR (SAM_TC678_BASE+SAM_TC_QIMR_OFFSET)
# define SAM_TC2_QISR (SAM_TC678_BASE+SAM_TC_QISR_OFFSET)
# define SAM_TC2_FMR (SAM_TC678_BASE+SAM_TC_FMR_OFFSET)
# define SAM_TC2_WPMR (SAM_TC678_BASE+SAM_TC_WPMR_OFFSET)
#else
# define SAM_TC_BCR (SAM_TC_BASE+SAM_TC_BCR_OFFSET)
# define SAM_TC_BMR (SAM_TC_BASE+SAM_TC_BMR_OFFSET)

4
arch/arm/src/sam34/sam_timerisr.c
View File

@ -129,7 +129,7 @@ int up_timerisr(int irq, uint32_t *regs)
}
/****************************************************************************
* Function: up_timerinit
* Function: up_timerinitialize
*
* Description:
* This function is called during start-up to initialize
@ -137,7 +137,7 @@ int up_timerisr(int irq, uint32_t *regs)
*
****************************************************************************/
void up_timerinit(void)
void up_timerinitialize(void)
{
uint32_t regval;