Add ESP32 Ethernet device driver
This driver was implemented by Dong Heng<dongheng@espressif.com> and reviewed by Alan Carvalho de Assis
This commit is contained in:
Alan C. Assis
Abdelatif Guettouche
parent
e1d3627bb1
commit
6ea7b29088
@ -1,70 +0,0 @@
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/****************************************************************************
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* arch/xtensa/src/common/xtensa_etherstub.c
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "xtensa.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_netinitialize (stub)
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*
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* Description:
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* This is a stub version os up_netinitialize. Normally, up_netinitialize
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* is defined in board/xyz_network.c for board-specific Ethernet
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* implementations, or chip/xyx_ethernet.c for chip-specific Ethernet
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* implementations. The stub version here is used in the corner case where
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* the network is enable yet there is no Ethernet driver to be initialized.
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* In this case, up_initialize will still try to call up_netinitialize()
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* when one does not exist. This corner case would occur if, for example,
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* only a USB network interface is being used or perhaps if a SLIP is
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* being used).
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*
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* Use of this stub is deprecated. The preferred mechanism is to use
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* CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in
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* up_initialize(). Then this stub would not be needed.
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*
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****************************************************************************/
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void up_netinitialize(void)
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{
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}
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@ -21,9 +21,9 @@ config ESP32_BT
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config ESP32_EMAC
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bool "Ethernet MAC"
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default n
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depends on EXPERIMENTAL
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select NET
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---help---
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No yet implemented
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Enable ESP32 ethernet support.
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config ESP32_I2C
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bool
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@ -436,4 +436,39 @@ config ESP32_SPIFLASH_DEBUG
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will show input arguments and result.
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endmenu # ESP32_SPIFLASH
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menu "Ethernet configuration"
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depends on ESP32_EMAC
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config ESP32_ETH_NRXDESC
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int "RX description number"
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default 9
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---help---
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Descriptions of RX should be more than TX's.
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config ESP32_ETH_NTXDESC
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int "TX description number"
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default 8
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config ESP32_ETH_MDCPIN
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int "MDC Pin"
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default 23
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range 0 39
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config ESP32_ETH_MDIOPIN
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int "MDIO Pin"
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default 18
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range 0 39
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config ESP32_ETH_PHY_RSTPIN
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int "Reset PHY Pin"
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default 5
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range 0 39
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config ESP32_ETH_PHY_ADDR
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int "PHY address"
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default 1
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endmenu # ESP32_EMAC
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endif # ARCH_CHIP_ESP32
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@ -81,18 +81,6 @@ ifeq ($(CONFIG_FS_HOSTFS),y)
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CMN_CSRCS += xtensa_hostfs.c
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endif
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# Use of common/xtensa_etherstub.c is deprecated. The preferred mechanism
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# is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to
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# up_netinitialize() in xtensa_initialize.c. Then this stub would not be
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# needed.
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ifneq ($(CONFIG_LX6_ETHERNET),y)
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ifeq ($(CONFIG_NET),y)
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CMN_CSRCS += xtensa_etherstub.c
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endif
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endif
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# Required ESP32 files (arch/xtensa/src/lx6)
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CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c
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@ -115,6 +103,10 @@ ifeq ($(CONFIG_ESP32_SPIFLASH),y)
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CHIP_CSRCS += esp32_spiflash.c
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endif
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ifeq ($(CONFIG_ESP32_EMAC),y)
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CHIP_CSRCS += esp32_emac.c
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endif
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# Configuration-dependent ESP32 files
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ifeq ($(CONFIG_SMP),y)
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2301
arch/xtensa/src/esp32/esp32_emac.c
Normal file
2301
arch/xtensa/src/esp32/esp32_emac.c
Normal file
File diff suppressed because it is too large
Load Diff
74
arch/xtensa/src/esp32/esp32_emac.h
Normal file
74
arch/xtensa/src/esp32/esp32_emac.h
Normal file
@ -0,0 +1,74 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/esp32_emac.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_EMAC_H
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#define __ARCH_XTENSA_SRC_ESP32_ESP32_EMAC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: esp32_emac_init
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*
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* Description:
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* Initialize ESP32 ethernet device driver.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* 0 is returned on success. Otherwise, a negated errno value is
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* returned indicating the nature of the failure:
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*
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* -ENOMEM is returned if no memory resource.
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*
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****************************************************************************/
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int esp32_emac_init(void);
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#ifdef __cplusplus
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}
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#endif
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#undef EXTERN
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_EMAC_H */
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@ -65,6 +65,7 @@
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# define FUNCTION_2 (2 << FUNCTION_SHIFT)
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# define FUNCTION_3 (3 << FUNCTION_SHIFT)
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# define FUNCTION_4 (4 << FUNCTION_SHIFT)
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# define FUNCTION_5 (5 << FUNCTION_SHIFT)
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# define SPECIAL (7 << FUNCTION_SHIFT)
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#define INPUT_PULLUP (INPUT | PULLUP)
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@ -76,12 +77,14 @@
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# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2)
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# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3)
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# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4)
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# define INPUT_FUNCTION_5 (INPUT_FUNCTION | FUNCTION_5)
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#define OUTPUT_FUNCTION (OUTPUT | FUNCTION)
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# define OUTPUT_FUNCTION_0 (OUTPUT_FUNCTION | FUNCTION_0)
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# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1)
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# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2)
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# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3)
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# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4)
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# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5)
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/* Interrupt type used with esp32_gpioirqenable() */
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@ -1181,6 +1181,8 @@
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#define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC)
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#define DPORT_EMAC_CLK_EN (BIT(14))
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/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
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#define DPORT_WIFI_CLK_EN 0xFFFFFFFF
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@ -1192,6 +1194,8 @@
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/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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#define DPORT_EMAC_RST_EN (BIT(7))
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#define DPORT_WIFI_RST 0xFFFFFFFF
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#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S))
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#define DPORT_WIFI_RST_V 0xFFFFFFFF
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558
arch/xtensa/src/esp32/hardware/esp32_emac.h
Normal file
558
arch/xtensa/src/esp32/hardware/esp32_emac.h
Normal file
@ -0,0 +1,558 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/hardware/esp32_emac.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EMAC_H
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#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EMAC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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/****************************************************************************
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* Ethernet MAC Register Base Address
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****************************************************************************/
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#define EMAC_REG_BASE (0x3ff69000)
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/****************************************************************************
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* MAC Address Register Address
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****************************************************************************/
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#define MAC_ADDR0_REG (0x3ff5a004)
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#define MAC_ADDR1_REG (0x3ff5a008)
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/****************************************************************************
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* Ethernet MAC Registers Offsets
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****************************************************************************/
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/* Ethernet MAC DMA bus mode configuration */
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#define EMAC_DMA_BMR_OFFSET (0x0000)
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/* Ethernet MAC DMA start TX */
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#define EMAC_DMA_STR_OFFSET (0x0004)
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/* Ethernet MAC DMA start RX */
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#define EMAC_DMA_SRR_OFFSET (0x0008)
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/* Ethernet MAC DMA RX description base address */
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#define EMAC_DMA_RDBR_OFFSET (0x000c)
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/* Ethernet MAC DMA TX description base address */
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#define EMAC_DMA_TDBR_OFFSET (0x0010)
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/* Ethernet MAC DMA interrupt and other status */
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#define EMAC_DMA_SR_OFFSET (0x0014)
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/* Ethernet MAC DMA operation mode */
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#define EMAC_DMA_OMR_OFFSET (0x0018)
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/* Ethernet MAC DMA interrupt enable */
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#define EMAC_DMA_IER_OFFSET (0x001c)
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/* Ethernet MAC DMA drop frame and overflow count */
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#define EMAC_DMA_DFR_OFFSET (0x0020)
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/* Ethernet MAC RX watch dog timer */
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#define EMAC_DMA_RWDR_OFFSET (0x0024)
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/* Ethernet MAC current TX description address */
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#define EMAC_DMA_CTDAR_OFFSET (0x0048)
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/* Ethernet MAC current RX description address */
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#define EMAC_DMA_CRDAR_OFFSET (0x004c)
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/* Ethernet MAC current TX description buffer address */
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#define EMAC_DMA_CTBAR_OFFSET (0x0050)
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/* Ethernet MAC current RX description buffer address */
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#define EMAC_DMA_CRBAR_OFFSET (0x0054)
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/* Ethernet MAC RMII clock divide */
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#define EMAC_ECOCR_OFFSET (0x800)
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/* Ethernet MAC RMII clock half and whole divide */
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#define EMAC_EOCCR_OFFSET (0x804)
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/* Clock resource selection and enbale */
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#define EMAC_ECCR_OFFSET (0x808)
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/* Selection MII or RMII interface of PHY */
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#define EMAC_PIR_OFFSET (0x80C)
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/* RAM power-down enable */
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#define EMAC_PDR_OFFSET (0x810)
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/* Ethernet MAC configuration */
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#define EMAC_CR_OFFSET (0x1000)
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/* Ethernet MAC frame filter */
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#define EMAC_FFR_OFFSET (0x1004)
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/* Ethernet MAC access PHY chip address */
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#define EMAC_MAR_OFFSET (0x1010)
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/* Ethernet MAC access PHY chip data */
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#define EMAC_MDR_OFFSET (0x1014)
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/* Ethernet MAC frame flow control */
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#define EMAC_FCR_OFFSET (0x1018)
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/* Ethernet MAC status debugging */
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#define EMAC_DBGR_OFFSET (0x1024)
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/* Ethernet MAC remote wake-up frame filter */
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#define EMAC_RWUFFR_OFFSET (0x1028)
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/* Ethernet MAC PMT control and status */
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#define EMAC_PMTCSR_OFFSET (0x102c)
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/* Ethernet MAC LPI control and status */
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#define EMAC_LPICSR_OFFSET (0x1030)
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/* Ethernet MAC LPI timers control */
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#define EMAC_LPICR_OFFSET (0x1034)
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/* Ethernet MAC interrupt status */
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#define EMAC_ISR_OFFSET (0x1038)
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/* Ethernet MAC interrupt mask */
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#define EMAC_IMR_OFFSET (0x103c)
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/* Ethernet MAC address high 16 bits */
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#define EMAC_MA0HR_OFFSET (0x1040)
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/* Ethernet MAC address low 32 bits */
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#define EMAC_MA0LR_OFFSET (0x1044)
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/* Ethernet MAC address1 filter high 16 bits */
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#define EMAC_MA1HR_OFFSET (0x1048)
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/* Ethernet MAC address1 filter low 32 bits */
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#define EMAC_MA1LR_OFFSET (0x104c)
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/* Ethernet MAC address2 filter high 16 bits */
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#define EMAC_MA2HR_OFFSET (0x1050)
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/* Ethernet MAC address2 filter low 32 bits */
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#define EMAC_MA2LR_OFFSET (0x1054)
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/* Ethernet MAC address3 filter high 16 bits */
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#define EMAC_MA3HR_OFFSET (0x1058)
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/* Ethernet MAC address3 filter low 32 bits */
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#define EMAC_MA3LR_OFFSET (0x105c)
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/* Ethernet MAC address4 filter high 16 bits */
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#define EMAC_MA4HR_OFFSET (0x1060)
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/* Ethernet MAC address4 filter low 32 bits */
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#define EMAC_MA4LR_OFFSET (0x1064)
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/* Ethernet MAC address5 filter high 16 bits */
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#define EMAC_MA5HR_OFFSET (0x1068)
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/* Ethernet MAC address5 filter low 32 bits */
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#define EMAC_MA5LR_OFFSET (0x106c)
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/* Ethernet MAC address6 filter high 16 bits */
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#define EMAC_MA6HR_OFFSET (0x1070)
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/* Ethernet MAC address6 filter low 32 bits */
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#define EMAC_MA6LR_OFFSET (0x1074)
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/* Ethernet MAC address7 filter high 16 bits */
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#define EMAC_MA7HR_OFFSET (0x1078)
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/* Ethernet MAC address7 filter low 32 bits */
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#define EMAC_MA7LR_OFFSET (0x107c)
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/* Ethernet MAC link communication status */
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||||
#define EMAC_LCSR_OFFSET (0x10d8)
|
||||
|
||||
/* Ethernet MAC watch dog timeout */
|
||||
|
||||
#define EMAC_WDR_OFFSET (0x10dc)
|
||||
|
||||
/****************************************************************************
|
||||
* Register Bitfield Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register EMAC_DMA_BMR ****************************************************/
|
||||
|
||||
#define EMAC_MB_E (BIT(26)) /* Mixed burst */
|
||||
#define EMAC_AAB_E (BIT(25)) /* Address align burst */
|
||||
#define EMAC_PBLX8_E (BIT(24)) /* PBL value x8 */
|
||||
#define EMAC_SPBL_E (BIT(23)) /* Seperated PBL */
|
||||
#define EMAC_RXDMA_PBL_S (17) /* RX DMA PBL value shift */
|
||||
#define EMAC_RXDMA_PBL_V (0x3f) /* RX DMA PBL value max value */
|
||||
#define EMAC_FB_E (BIT(16)) /* Fixed burst */
|
||||
#define EMAC_PR_S (14) /* Priority ratio shift */
|
||||
#define EMAC_PR_V (0x3) /* Priority ratio max value */
|
||||
#define EMAC_PBL_S (8) /* Program burst length shift */
|
||||
#define EMAC_PBL_V (0x3f) /* Program burst length max value */
|
||||
#define EMAC_ADS_E (BIT(7)) /* Extend DMA description size */
|
||||
#define EMAC_DSL_S (2) /* Skip length shift */
|
||||
#define EMAC_DSL_V (0x1f) /* Skip length max value */
|
||||
#define EMAC_DAS_E (BIT(1)) /* DMA arbitration scheme */
|
||||
#define EMAC_SR_E (BIT(0)) /* Software reset */
|
||||
|
||||
/* Register EMAC_DMA_SR *****************************************************/
|
||||
|
||||
#define EMAC_TTI (BIT(29)) /* Timestamp triggers interrupt */
|
||||
#define EMAC_PMTI (BIT(28)) /* PMT interrupt */
|
||||
#define EMAC_EB_S (23) /* Error bits shift */
|
||||
#define EMAC_EB_V (0x7) /* Error bits max value */
|
||||
#define EMAC_DTFS_S (20) /* DMA TX FSM state shift */
|
||||
#define EMAC_DTFS_V (0x7) /* DMA TX FSM state max value */
|
||||
#define EMAC_DRFS_S (17) /* DMA RX FSM state shift */
|
||||
#define EMAC_DRFS_V (0x7) /* DMA RX FSM state max value */
|
||||
#define EMAC_NIS (BIT(16)) /* Normal interrupt summary */
|
||||
#define EMAC_AIS (BIT(15)) /* Abnormal interrupt summary */
|
||||
#define EMAC_ERI (BIT(14)) /* Early receive interrupt */
|
||||
#define EMAC_FBEI (BIT(13)) /* Fatal bus error interrupt */
|
||||
#define EMAC_ETI (BIT(10)) /* Early transmit interrupt */
|
||||
#define EMAC_RWDTO (BIT(9)) /* Receive watch dog timeout */
|
||||
#define EMAC_RPS (BIT(8)) /* Receive process stop */
|
||||
#define EMAC_RBU (BIT(7)) /* Receive buffer unavailable */
|
||||
#define EMAC_RI (BIT(6)) /* Receive interrupt */
|
||||
#define EMAC_TUF (BIT(5)) /* Transmit underflow */
|
||||
#define EMAC_ROF (BIT(4)) /* Receive overflow */
|
||||
#define EMAC_TJTO (BIT(3)) /* Transmit jabber timeout */
|
||||
#define EMAC_TBU (BIT(2)) /* Transmit buffer unavailable */
|
||||
#define EMAC_TPS (BIT(1)) /* Transmit process stop */
|
||||
#define EMAC_TI (BIT(0)) /* Transmit interrupt */
|
||||
|
||||
/* Register EMAC_DMA_OMR ****************************************************/
|
||||
|
||||
#define EMAC_DTIEF_D (BIT(26)) /* Disable drop TCPIP error frame */
|
||||
#define EMAC_FRF_E (BIT(25)) /* Forward received frame */
|
||||
#define EMAC_FRF_D (BIT(24)) /* Disable flush received frame*/
|
||||
#define EMAC_FFSF_E (BIT(21)) /* Forward FIFO stored frame */
|
||||
#define EMAC_FTF_E (BIT(20)) /* Flush TX FiFo */
|
||||
#define EMAC_TTC_S (14) /* TX threshold control shift */
|
||||
#define EMAC_TTC_V (0x7) /* TX threshold control max value */
|
||||
#define EMAC_SST_E (BIT(13)) /* Start Stop transmit */
|
||||
#define EMAC_FEF_E (BIT(7)) /* Forward error frame */
|
||||
#define EMAC_FSF_E (BIT(6)) /* Forward small(<64B) frame */
|
||||
#define EMAC_FLF_E (BIT(5)) /* Forward large frame */
|
||||
#define EMAC_RTC_S (3) /* RX threshold control shift */
|
||||
#define EMAC_RTC_V (0x3) /* RX threshold control max value */
|
||||
#define EMAC_OSF_E (BIT(2)) /* Operate second frame */
|
||||
#define EMAC_SSR_E (BIT(1)) /* Start Stop receive */
|
||||
|
||||
/* Register EMAC_EOCCR ******************************************************/
|
||||
|
||||
#define EMAC_OSEC_E (BIT(24)) /* OSC select external clock */
|
||||
#define EMAC_OHDF100M_S (18) /* Half divide frequency shift when 100MHz */
|
||||
#define EMAC_OHDF100M_V (0x3f) /* Half divide frequency max value when 100MHz */
|
||||
#define EMAC_ODF100M_S (12) /* Divide frequency shift when 100MHz */
|
||||
#define EMAC_ODF100M_V (0x3f) /* Divide frequency max value when 100MHz */
|
||||
#define EMAC_OHDF10M_S (6) /* Half divide frequency shift when 10MHz */
|
||||
#define EMAC_OHDF10M_V (0x3f) /* Half divide frequency max value when 10MHz */
|
||||
#define EMAC_ODF10M_S (0) /* Divide frequency shift when 10MHz */
|
||||
#define EMAC_ODF10M_V (0x3f) /* Divide frequency max value when 10MHz */
|
||||
|
||||
/* Register EMAC_ECCR *******************************************************/
|
||||
|
||||
#define EMAC_RXC_E (BIT(3)) /* RX clock */
|
||||
#define EMAC_TXC_E (BIT(2)) /* TX clock */
|
||||
#define EMAC_IAC_E (BIT(1)) /* Internal APLL clock */
|
||||
#define EMAC_EXC_E (BIT(0)) /* External XTAL clock */
|
||||
|
||||
/* Register EMAC_PIR ********************************************************/
|
||||
|
||||
#define EMAC_PIS_S (13) /* PHY interf. sel. shift */
|
||||
#define EMAC_PIS_MII (0) /* MII interface */
|
||||
#define EMAC_PIS_RMII (0x4 << EMAC_PIS_S) /* RMII interface */
|
||||
|
||||
/* Register EMAC_CR *********************************************************/
|
||||
|
||||
#define EMAC_SAIRC_S (28) /* Control frame src address shift */
|
||||
#define EMAC_SAIRC_V (0x7) /* Control frame src address max value */
|
||||
#define EMAC_PST2KF_E (BIT(27)) /* Pass smaller that 2K frame */
|
||||
#define EMAC_WD_D (BIT(23)) /* Disable watch dog */
|
||||
#define EMAC_JT_D (BIT(22)) /* Disable Jabber timer */
|
||||
#define EMAC_RLF_E (BIT(21)) /* Receive large frame */
|
||||
#define EMAC_TFMIFG_S (17) /* Time frame min IFG shift */
|
||||
#define EMAC_TFMIFG_V (0x7) /* Time frame min IFG max value */
|
||||
#define EMAC_DCRS_E (BIT(16)) /* Drop CRS */
|
||||
#define EMAC_SS_E (BIT(15)) /* Speed select */
|
||||
#define EMAC_100M_E (BIT(14)) /* 100MHz */
|
||||
#define EMAC_RXO_E (BIT(13)) /* Stop RX when trigger TX_EN */
|
||||
#define EMAC_LB_E (BIT(12)) /* Loop back */
|
||||
#define EMAC_FD_E (BIT(11)) /* Full duplex */
|
||||
#define EMAC_RIPCOFFLOAD_E (BIT(10)) /* Calculate ethernet payload */
|
||||
#define EMAC_TXR_E (BIT(9)) /* TX retry */
|
||||
#define EMAC_SPOFCS_E (BIT(7)) /* Strip pad or FCS */
|
||||
#define EMAC_BOL_S (5) /* Backoff limit shift */
|
||||
#define EMAC_BOL_V (0x3) /* Backoff limit max value */
|
||||
#define EMAC_DF_E (BIT(4)) /* Deferral check */
|
||||
#define EMAC_TX_E (BIT(3)) /* Enable EMAC TX */
|
||||
#define EMAC_RX_E (BIT(2)) /* Enable EMAC RX */
|
||||
#define EMAC_PLTF_S (0) /* Frame preamble bytes select shift */
|
||||
#define EMAC_PLTF_V (0x3) /* Frame preamble bytes select max value */
|
||||
|
||||
/* Register EMAC_FFR ********************************************************/
|
||||
|
||||
#define EMAC_RA_E (BIT(31)) /* Receive all frame */
|
||||
#define EMAC_SAF_E (BIT(9)) /* Src address filter */
|
||||
#define EMAC_SARF_E (BIT(8)) /* Src address reverse filter */
|
||||
#define EMAC_PCF_S (6) /* Proccess control frame shift */
|
||||
#define EMAC_PCF_V (0x3) /* Proccess control frame max value */
|
||||
#define EMAC_BF_D (BIT(5)) /* Disable pass broadcast frame */
|
||||
#define EMAC_PMF_E (BIT(4)) /* Pass multicast frame */
|
||||
#define EMAC_DAIF_E (BIT(3)) /* multicast and unicast reverse filter */
|
||||
#define EMAC_PA_E (BIT(0)) /* Pass all frame */
|
||||
|
||||
/* Register EMAC_MAR ********************************************************/
|
||||
|
||||
#define EMAC_PCA_S (11) /* PHY chip address shift */
|
||||
#define EMAC_PCA_V (0x1f) /* PHY chip address max value */
|
||||
#define EMAC_PCRA_S (6) /* PHY chip register address shift */
|
||||
#define EMAC_PCRA_V (0x1f) /* PHY chip register address max value */
|
||||
#define EMAC_SMICS_S (2) /* SMI clock source shift */
|
||||
#define EMAC_SMICS_V (0xf) /* SMI clock source max value */
|
||||
#define EMAC_HW_E (BIT(1)) /* Enable PHY write */
|
||||
#define EMAC_PIB (BIT(0)) /* PHY is busy */
|
||||
|
||||
/* Register EMAC_FCR ********************************************************/
|
||||
|
||||
#define EMAC_CFPT_S (16) /* Control frame pause time shift */
|
||||
#define EMAC_CFPT_V (0xffff) /* Control frame pause time max value */
|
||||
#define EMAC_PFPT_S (4) /* Pause frame pause threshold shift */
|
||||
#define EMAC_PFPT_V (0x3) /* Pause frame pause threshold max value */
|
||||
#define EMAC_PPFWAA_E (BIT(3)) /* Process pause frame when address approved */
|
||||
#define EMAC_RXFC_E (BIT(2)) /* Pause RX when receive pause frame */
|
||||
#define EMAC_TXFC_E (BIT(1)) /* TX flow control transmit pause frame */
|
||||
#define EMAC_FCBBA_E (BIT(0)) /* Start pause frame usage */
|
||||
|
||||
/* Register EMAC_DBGR *******************************************************/
|
||||
|
||||
#define EMAC_TXFF (BIT(25)) /* TX FiFo is full */
|
||||
#define EMAC_TXFNF (BIT(24)) /* TX FiFo is not full */
|
||||
#define EMAC_TXFA (BIT(23)) /* TX FiFo is active */
|
||||
#define EMAC_TXFS_S (20) /* TX FiFo status shift */
|
||||
#define EMAC_TXFS_V (0x3) /* TX FiFo status max value */
|
||||
#define EMAC_EPS (BIT(19)) /* MAC enters pause state */
|
||||
#define EMAC_TFCS_S (17) /* Transmit frame control status shift */
|
||||
#define EMAC_TFCS_V (0x3) /* Transmit frame control status max value */
|
||||
#define EMAC_TXCA (BIT(16)) /* Transmit control is active */
|
||||
#define EMAC_RFFL_S (8) /* RX FiFi fill level shift */
|
||||
#define EMAC_RFFL_V (0x3) /* RX FiFi fill level max value */
|
||||
#define EMAC_RXFS_S (5) /* RX FiFo status shift */
|
||||
#define EMAC_RXFS_V (0x3) /* RX FiFo status max value */
|
||||
#define EMAC_RXFA (BIT(4)) /* RX FiFo is active */
|
||||
#define EMAC_FCS_S (1) /* FiFo status shift */
|
||||
#define EMAC_FCS_V (0x3) /* FiFo status max value */
|
||||
#define EMAC_RXCA (BIT(0)) /* RX control is active */
|
||||
|
||||
/* RX DMA description TDES0 register ****************************************/
|
||||
|
||||
#define EMAC_RXDMA_OWN (BIT(31)) /* Own by Hardware */
|
||||
#define EMAC_RXDMA_DAFF (BIT(30)) /* Dest address filter Fail */
|
||||
#define EMAC_RXDMA_FL_S (16) /* Received frame length shift */
|
||||
#define EMAC_RXDMA_FL_V (0x1fff) /* Received frame length max value */
|
||||
#define EMAC_RXDMA_ES (BIT(15)) /* Error summary */
|
||||
#define EMAC_RXDMA_DE (BIT(14)) /* Description error */
|
||||
#define EMAC_RXDMA_SAFF (BIT(13)) /* Rsc address filter Fail */
|
||||
#define EMAC_RXDMA_LE (BIT(12)) /* Length error */
|
||||
#define EMAC_RXDMA_OE (BIT(11)) /* Overflow error */
|
||||
#define EMAC_RXDMA_VT (BIT(10)) /* VLAN tag */
|
||||
#define EMAC_RXDMA_FS (BIT(9)) /* First segment of frame */
|
||||
#define EMAC_RXDMA_LS (BIT(8)) /* Last segment of frame */
|
||||
#define EMAC_RXDMA_TSA (BIT(7)) /* Timestamp available */
|
||||
#define EMAC_RXDMA_RC (BIT(6)) /* Receive collision */
|
||||
#define EMAC_RXDMA_FT (BIT(5)) /* Frame type */
|
||||
#define EMAC_RXDMA_TO (BIT(4)) /* Receive timeout */
|
||||
#define EMAC_RXDMA_RE (BIT(3)) /* Receive error */
|
||||
#define EMAC_RXDMA_DBE (BIT(2)) /* Dribble bit error */
|
||||
#define EMAC_RXDMA_CE (BIT(1)) /* CRC error */
|
||||
#define EMAC_RXDMA_ESA (BIT(0)) /* Extended status available */
|
||||
|
||||
/* RX DMA description TDES1 register ****************************************/
|
||||
|
||||
#define EMAC_RXDMA_SRI (BIT(31)) /* Stop RI interrupt */
|
||||
#define EMAC_RXDMA_RER (BIT(15)) /* Receive end of ring */
|
||||
#define EMAC_RXDMA_RCH (BIT(14)) /* Second address chained */
|
||||
#define EMAC_RXDMA_RBS_S (0) /* Receive bufer size shift */
|
||||
#define EMAC_RXDMA_RBS_V (0x1fff) /* Receive bufer size max value */
|
||||
|
||||
/* TX DMA description TDES0 register ****************************************/
|
||||
|
||||
#define EMAC_TXDMA_OWN (BIT(31)) /* Own by Hardware */
|
||||
#define EMAC_TXDMA_CI (BIT(30)) /* Enable complete interrupt */
|
||||
#define EMAC_TXDMA_LS (BIT(29)) /* Last segment of frame */
|
||||
#define EMAC_TXDMA_FS (BIT(28)) /* First segment of frame */
|
||||
#define EMAC_TXDMA_DC (BIT(27)) /* Disable CRC generation */
|
||||
#define EMAC_TXDMA_DP (BIT(26)) /* Disable PAD generation */
|
||||
#define EMAC_TXDMA_ETTS (BIT(25)) /* Enable transmit timestamp */
|
||||
#define EMAC_TXDMA_RC (BIT(24)) /* Replace CRC of frame */
|
||||
#define EMAC_TXDMA_CCI_S (22) /* Control checksum operation shift */
|
||||
#define EMAC_TXDMA_CCI_V (0x3) /* Control checksum operation max value */
|
||||
#define EMAC_TXDMA_TER (BIT(21)) /* Transmit end of ring */
|
||||
#define EMAC_TXDMA_TCH (BIT(20)) /* Second address chained */
|
||||
#define EMAC_TXDMA_VIC_S (18) /* Control VLAN insertion shift */
|
||||
#define EMAC_TXDMA_VIC_V (0x3) /* Control VLAN insertion max value */
|
||||
#define EMAC_TXDMA_TTSS (BIT(17)) /* Transmit timestamp status */
|
||||
#define EMAC_TXDMA_IHE (BIT(16)) /* IP header error */
|
||||
#define EMAC_TXDMA_ES (BIT(15)) /* Error summary */
|
||||
#define EMAC_TXDMA_JT (BIT(14)) /* Jabber Timeout */
|
||||
#define EMAC_TXDMA_FF (BIT(13)) /* Frame is flushed */
|
||||
#define EMAC_TXDMA_IPE (BIT(12)) /* IP payload error */
|
||||
#define EMAC_TXDMA_LC (BIT(11)) /* Lose carrier */
|
||||
#define EMAC_TXDMA_NC (BIT(10)) /* No carrier */
|
||||
#define EMAC_TXDMA_TC (BIT(9)) /* Transmit collision */
|
||||
#define EMAC_TXDMA_EC (BIT(8)) /* Excessive collision */
|
||||
#define EMAC_TXDMA_VF (BIT(7)) /* VLAN frame */
|
||||
#define EMAC_TXDMA_CC_S (4) /* Collision counter shift */
|
||||
#define EMAC_TXDMA_CC_V (0xf) /* Collision counter max value */
|
||||
#define EMAC_TXDMA_ED (BIT(2)) /* Excessive deferral */
|
||||
#define EMAC_TXDMA_UE (BIT(1)) /* Underflow Error */
|
||||
#define EMAC_TXDMA_DB (BIT(0)) /* Deferred bit */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/* RX DMA description structure */
|
||||
|
||||
struct emac_rxdesc_s
|
||||
{
|
||||
/* RX description status */
|
||||
|
||||
uint32_t status;
|
||||
|
||||
/* RX description control */
|
||||
|
||||
uint32_t ctrl;
|
||||
|
||||
/* RX buffer pointer */
|
||||
|
||||
uint8_t *pbuf;
|
||||
|
||||
/* Next RX description */
|
||||
|
||||
struct emac_rxdesc_s *next;
|
||||
|
||||
/* RX description extend status */
|
||||
|
||||
uint32_t ext_status;
|
||||
|
||||
/* RX description reserved data */
|
||||
|
||||
uint32_t reserved;
|
||||
|
||||
/* Receive frame timestamp low */
|
||||
|
||||
uint32_t ts_l;
|
||||
|
||||
/* Receive frame timestamp high */
|
||||
|
||||
uint32_t ts_h;
|
||||
};
|
||||
|
||||
/* TX DMA description structure */
|
||||
|
||||
struct emac_txdesc_s
|
||||
{
|
||||
/* TX description control */
|
||||
|
||||
uint32_t ctrl;
|
||||
|
||||
/* RX description extend control */
|
||||
|
||||
uint32_t ext_ctrl;
|
||||
|
||||
/* TX buffer pointer */
|
||||
|
||||
uint8_t *pbuf;
|
||||
|
||||
/* Next TX description */
|
||||
|
||||
struct emac_txdesc_s *next;
|
||||
|
||||
/* RX description reserved data 0 */
|
||||
|
||||
uint32_t reserved0;
|
||||
|
||||
/* RX description reserved data 1 */
|
||||
|
||||
uint32_t reserved2;
|
||||
|
||||
/* Transmit frame timestamp low */
|
||||
|
||||
uint32_t ts_l;
|
||||
|
||||
/* Transmit frame timestamp high */
|
||||
|
||||
uint32_t ts_h;
|
||||
};
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EMAC_H */
|
||||
@ -21,6 +21,7 @@ Contents
|
||||
o Memory Map
|
||||
o Serial Console
|
||||
o Buttons and LEDs
|
||||
o Ethernet
|
||||
o SMP
|
||||
o OpenOCD for the ESP32
|
||||
o Executing and Debugging from FLASH and IRAM
|
||||
@ -215,6 +216,46 @@ Buttons and LEDs
|
||||
There are several on-board LEDs for that indicate the presence of power
|
||||
and USB activity. None of these are available for use by software.
|
||||
|
||||
Ethernet
|
||||
========
|
||||
|
||||
ESP32 has a 802.11 hardware MAC, so just connects to external PHY chip.
|
||||
Due to ESP32's GPIOs are not enough, so recommanded users to use RMII
|
||||
to connect ESP32 to PHY chip, current driver also only supports RMII option.
|
||||
|
||||
The RMII GPIO pins are fixed, but the SMI and functional GPIO pins are optional.
|
||||
|
||||
RMII GPIO pins are as following:
|
||||
|
||||
ESP32 GPIO PHY Chip GPIO
|
||||
IO25 <--> RXD[0]
|
||||
IO26 <--> RXD[1]
|
||||
IO27 <--> CRS_DV
|
||||
IO0 <--> REF_CLK
|
||||
IO19 <--> TXD[0]
|
||||
IO21 <--> TX_EN
|
||||
IO22 <--> TXD[1]
|
||||
|
||||
SMI GPIO pins (default option) are as following:
|
||||
|
||||
ESP32 GPIO PHY Chip GPIO
|
||||
IO18 <--> MDIO
|
||||
IO23 <--> MDC
|
||||
|
||||
Functional GPIO pins(default option) are as following:
|
||||
|
||||
ESP32 GPIO PHY Chip GPIO
|
||||
IO5 <--> Reset_N
|
||||
|
||||
Espressif has an offcial Ethernet development board:
|
||||
|
||||
https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-ethernet-kit.html
|
||||
|
||||
This driver has been tested according to this board and ESP32 core
|
||||
board + LAN8720 module. If users have some issue about using this driver,
|
||||
please refer the upper official document, specially the issue that GPIO0
|
||||
causes failing to bring the ESP32 chip up.
|
||||
|
||||
SMP
|
||||
===
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user