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DMA updates

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2568 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-04-02 00:45:28 +00:00
parent 1b81a8042a
commit 6ea90bb7b8
4 changed files with 836 additions and 163 deletions
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915
arch/arm/src/sam3u/sam3u_dmac.c
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File diff suppressed because it is too large Load Diff

12
arch/arm/src/sam3u/sam3u_dmac.h
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@ -374,12 +374,12 @@
# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */ # define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */
#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */ #define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */
#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT) #define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT)
# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* INCREMENTING */ # define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */
# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* FIXED */ # define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */ #define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */
#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT) #define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT)
# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* INCREMENTING */ # define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */
# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* FIXED */ # define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */ #define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */
/* DMAC Channel n [n = 0..3] Configuration Register */ /* DMAC Channel n [n = 0..3] Configuration Register */
@ -422,8 +422,8 @@ struct dma_linklist_s
uint32_t src; /* Source address */ uint32_t src; /* Source address */
uint32_t dest; /* Destination address */ uint32_t dest; /* Destination address */
uint32_t ctrla; /* Control A value */ uint32_t ctrla; /* Control A value */
uint32_t ctrlb; /* Congtrol B value */ uint32_t ctrlb; /* Control B value */
uint32_t desc; /* Descriptor address */ uint32_t next; /* Next descriptor address */
}; };
/**************************************************************************************** /****************************************************************************************

13
arch/arm/src/sam3u/sam3u_hsmci.c
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@ -122,10 +122,9 @@
#define DMA_FLAGS \ #define DMA_FLAGS \
(DMACH_FLAG_FIFO_8BYTES | DMACH_FLAG_FIFOCFG_LARGEST | \ (DMACH_FLAG_FIFO_8BYTES | DMACH_FLAG_FIFOCFG_LARGEST | \
(DMACHAN_PID_MCI0 << DMACH_FLAG_PERIPHPID_SHIFT) | \ (DMACHAN_PID_MCI0 << DMACH_FLAG_PERIPHPID_SHIFT) | \
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHLLIMODE | \ DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \
DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \ DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
DMACH_FLAG_MEMLLIMODE | DMACH_FLAG_MEMWIDTH_32BITS | \ DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_4)
DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_4)
/* FIFO sizes */ /* FIFO sizes */
@ -328,7 +327,7 @@ static void sam3u_dumpsamples(struct sam3u_dev_s *priv);
# define sam3u_dumpsamples(priv) # define sam3u_dumpsamples(priv)
#endif #endif
static void sam3u_dmacallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void sam3u_dmacallback(DMA_HANDLE handle, void *arg, int result);
/* Data Transfer Helpers ****************************************************/ /* Data Transfer Helpers ****************************************************/
@ -791,7 +790,7 @@ static void sam3u_dumpsamples(struct sam3u_dev_s *priv)
* *
****************************************************************************/ ****************************************************************************/
static void sam3u_dmacallback(DMA_HANDLE handle, uint8_t isr, void *arg) static void sam3u_dmacallback(DMA_HANDLE handle, void *arg, int result)
{ {
/* FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)arg; */ /* FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)arg; */
@ -2354,7 +2353,7 @@ static int sam3u_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
/* Start the DMA */ /* Start the DMA */
sam3u_sample(priv, SAMPLENDX_BEFORE_ENABLE); sam3u_sample(priv, SAMPLENDX_BEFORE_ENABLE);
sam3u_dmastart(priv->dma, sam3u_dmacallback, priv, false); sam3u_dmastart(priv->dma, sam3u_dmacallback, priv);
sam3u_sample(priv, SAMPLENDX_AFTER_SETUP); sam3u_sample(priv, SAMPLENDX_AFTER_SETUP);
ret = OK; ret = OK;
} }
@ -2421,7 +2420,7 @@ static int sam3u_dmasendsetup(FAR struct sdio_dev_s *dev,
/* Start the DMA */ /* Start the DMA */
sam3u_dmastart(priv->dma, sam3u_dmacallback, priv, false); sam3u_dmastart(priv->dma, sam3u_dmacallback, priv);
sam3u_sample(priv, SAMPLENDX_AFTER_SETUP); sam3u_sample(priv, SAMPLENDX_AFTER_SETUP);
/* Enable TX interrrupts */ /* Enable TX interrrupts */

31
arch/arm/src/sam3u/sam3u_internal.h
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@ -322,13 +322,13 @@
#define DMACH_FLAG_PERIPHPID_SHIFT (4) /* Bits 4-7: Peripheral PID */ #define DMACH_FLAG_PERIPHPID_SHIFT (4) /* Bits 4-7: Peripheral PID */
#define DMACH_FLAG_PERIPHPID_MASK (15 << DMACH_FLAG_PERIPHPID_SHIFT) #define DMACH_FLAG_PERIPHPID_MASK (15 << DMACH_FLAG_PERIPHPID_SHIFT)
#define DMACH_FLAG_PERIPHH2SEL (1 << 8) /* Bits 8: HW handshaking */ #define DMACH_FLAG_PERIPHH2SEL (1 << 8) /* Bits 8: HW handshaking */
#define DMACH_FLAG_PERIPHWIDTH_SHIFT (9) /* Bits 9-10: Peripheral width */ #define DMACH_FLAG_PERIPHISPERIPH (1 << 9) /* Bits 9: 0=memory; 1=peripheral */
#define DMACH_FLAG_PERIPHWIDTH_SHIFT (10) /* Bits 10-11: Peripheral width */
#define DMACH_FLAG_PERIPHWIDTH_MASK (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT) #define DMACH_FLAG_PERIPHWIDTH_MASK (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT)
# define DMACH_FLAG_PERIPHWIDTH_8BITS (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */ # define DMACH_FLAG_PERIPHWIDTH_8BITS (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */
# define DMACH_FLAG_PERIPHWIDTH_16BITS (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */ # define DMACH_FLAG_PERIPHWIDTH_16BITS (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */
# define DMACH_FLAG_PERIPHWIDTH_32BITS (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */ # define DMACH_FLAG_PERIPHWIDTH_32BITS (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */
#define DMACH_FLAG_PERIPHINCREMENT (1 << 11) /* Bit 11: Autoincrement peripheral address */ #define DMACH_FLAG_PERIPHINCREMENT (1 << 12) /* Bit 12: Autoincrement peripheral address */
#define DMACH_FLAG_PERIPHLLIMODE (1 << 12) /* Bit 12: Use link list descriptors */
#define DMACH_FLAG_PERIPHCHUNKSIZE (1 << 13) /* Bit 13: Peripheral chunk size */ #define DMACH_FLAG_PERIPHCHUNKSIZE (1 << 13) /* Bit 13: Peripheral chunk size */
# define DMACH_FLAG_PERIPHCHUNKSIZE_1 (0) /* Peripheral chunksize = 1 */ # define DMACH_FLAG_PERIPHCHUNKSIZE_1 (0) /* Peripheral chunksize = 1 */
# define DMACH_FLAG_PERIPHCHUNKSIZE_4 DMACH_FLAG_PERIPHCHUNKSIZE /* Peripheral chunksize = 4 */ # define DMACH_FLAG_PERIPHCHUNKSIZE_4 DMACH_FLAG_PERIPHCHUNKSIZE /* Peripheral chunksize = 4 */
@ -338,14 +338,14 @@
#define DMACH_FLAG_MEMPID_SHIFT (14) /* Bits 14-17: Memory PID */ #define DMACH_FLAG_MEMPID_SHIFT (14) /* Bits 14-17: Memory PID */
#define DMACH_FLAG_MEMPID_MASK (15 << DMACH_FLAG_PERIPHPID_SHIFT) #define DMACH_FLAG_MEMPID_MASK (15 << DMACH_FLAG_PERIPHPID_SHIFT)
#define DMACH_FLAG_MEMH2SEL (1 << 18) /* Bits 18: HW handshaking */ #define DMACH_FLAG_MEMH2SEL (1 << 18) /* Bits 18: HW handshaking */
#define DMACH_FLAG_MEMWIDTH_SHIFT (19) /* Bits 19-20: Memory width */ #define DMACH_FLAG_MEMISPERIPH (1 << 19) /* Bits 19: 0=memory; 1=peripheral */
#define DMACH_FLAG_MEMWIDTH_SHIFT (20) /* Bits 20-21: Memory width */
#define DMACH_FLAG_MEMWIDTH_MASK (3 << DMACH_FLAG_MEMWIDTH_SHIFT) #define DMACH_FLAG_MEMWIDTH_MASK (3 << DMACH_FLAG_MEMWIDTH_SHIFT)
# define DMACH_FLAG_MEMWIDTH_8BITS (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */ # define DMACH_FLAG_MEMWIDTH_8BITS (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */
# define DMACH_FLAG_MEMWIDTH_16BITS (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */ # define DMACH_FLAG_MEMWIDTH_16BITS (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */
# define DMACH_FLAG_MEMWIDTH_32BITS (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */ # define DMACH_FLAG_MEMWIDTH_32BITS (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */
#define DMACH_FLAG_MEMINCREMENT (1 << 21) /* Bit 21: Autoincrement memory address */ #define DMACH_FLAG_MEMINCREMENT (1 << 22) /* Bit 22: Autoincrement memory address */
#define DMACH_FLAG_MEMLLIMODE (1 << 22) /* Bit 22: Use link list descriptors */ #define DMACH_FLAG_MEMCHUNKSIZE (1 << 22) /* Bit 23: Memory chunk size */
#define DMACH_FLAG_MEMCHUNKSIZE (1 << 23) /* Bit 23: Memory chunk size */
# define DMACH_FLAG_MEMCHUNKSIZE_1 (0) /* Memory chunksize = 1 */ # define DMACH_FLAG_MEMCHUNKSIZE_1 (0) /* Memory chunksize = 1 */
# define DMACH_FLAG_MEMCHUNKSIZE_4 DMACH_FLAG_MEMCHUNKSIZE /* Memory chunksize = 4 */ # define DMACH_FLAG_MEMCHUNKSIZE_4 DMACH_FLAG_MEMCHUNKSIZE /* Memory chunksize = 4 */
@ -354,7 +354,7 @@
************************************************************************************/ ************************************************************************************/
typedef FAR void *DMA_HANDLE; typedef FAR void *DMA_HANDLE;
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t isr, void *arg); typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ /* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
@ -559,7 +559,10 @@ EXTERN void sam3u_dmafree(DMA_HANDLE handle);
* Name: sam3u_dmatxsetup * Name: sam3u_dmatxsetup
* *
* Description: * Description:
* Configure DMA for transmit (memory to periphal). * Configure DMA for transmit of one buffer (memory to peripheral). This
* function may be called multiple times to handle large and/or dis-
* continuous transfers. Calls to sam3u_dmatxsetup() and sam3u_dmatxsetup()
* must not be intermixed on the same transfer, however.
* *
****************************************************************************/ ****************************************************************************/
@ -570,11 +573,14 @@ EXTERN void sam3u_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
* Name: sam3u_dmarxsetup * Name: sam3u_dmarxsetup
* *
* Description: * Description:
* Configure DMA for receive (peripheral to memory). * Configure DMA for receipt of one buffer (peripheral to memory). This
* function may be called multiple times to handle large and/or dis-
* continuous transfers. Calls to sam3u_dmatxsetup() and sam3u_dmatxsetup()
* must not be intermixed on the same transfer, however.
* *
****************************************************************************/ ****************************************************************************/
EXTERN void sam3u_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, EXTERN int sam3u_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t nbytes); size_t nbytes);
/**************************************************************************** /****************************************************************************
@ -585,8 +591,7 @@ EXTERN void sam3u_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
* *
****************************************************************************/ ****************************************************************************/
EXTERN void sam3u_dmastart(DMA_HANDLE handle, dma_callback_t callback, EXTERN int sam3u_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
void *arg, bool half);
/**************************************************************************** /****************************************************************************
* Name: sam3u_dmastop * Name: sam3u_dmastop