Leverage the LPC54xx back to the LPC43xx (where it came from originally)
Squashed commit of the following:
arch/arm/src/lpc43xx: SDMMC driver now builds for the LPC43 (provided that the proper definitions appear in the board.h file).
arch/arm/src/lpc43xx: Update basic changes to the ported lpc54xx driver for lpc43xx clocking and GPIOs.
arch/arm/src/lpc43xx: Brings in the LPC54xx SD/MMC driver with absolutely no changes other than changing all occurences of 54 to 43.
arm/arm/src/lpc43xx: Add build support for the lpc54 SDMMC driver.
lpc54 SDMMC: Check for successful data transfer last. Checking first means that we miss errors.
This commit is contained in:
Gregory Nutt
parent
7add46bab5
commit
6ed875a63b
@ -254,6 +254,8 @@ config LPC43_SCT
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config LPC43_SDMMC
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bool "SD/MMC"
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default n
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select ARCH_HAVE_SDIO
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depends on EXPERIMENTAL
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config LPC43_SPI
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bool "SPI"
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@ -338,19 +340,6 @@ config LPC43_WWDT
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endmenu # LPC43xx Peripheral Support
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menu "ADC driver options"
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depends on LPC43_ADC0 || LPC43_ADC1
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config ADC0_MASK
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hex "ADC0 mask"
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default 0x01
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config ADC0_FREQ
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int "ADC0 frequency"
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default 4500000
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endmenu # ADC driver options
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config LPC43_GPIO_IRQ
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bool "GPIO interrupt support"
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default n
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@ -509,6 +498,32 @@ endif # LCP43_EXTSDRAM3
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endmenu # External Memory Configuration
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menu "SD/MMC Configuration"
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depends on LPC43_SDMMC
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config LPC43_SDMMC_PWRCTRL
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bool "Power-enable pin"
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default n
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---help---
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Select if the board supports a power-enable pin that must be selected
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to provide power to the SD card.
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config LPC43_SDMMC_DMA
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bool "Support DMA data transfers"
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default y
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select SDIO_DMA
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---help---
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Support DMA data transfers.
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config LPC43_SDMMC_REGDEBUG
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bool "Register level debug"
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default n
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depends on DEBUG_MEMCARD_INFO
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---help---
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Output detailed register-level SD/MMC debug information.
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endmenu # SD/MMC Configuration
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menu "Ethernet MAC configuration"
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depends on LPC43_ETHERNET
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@ -672,6 +687,19 @@ config LPC43_ETHERNET_REGDEBUG
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endmenu # Ethernet MAC configuration
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menu "ADC driver options"
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depends on LPC43_ADC0 || LPC43_ADC1
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config ADC0_MASK
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hex "ADC0 mask"
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default 0x01
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config ADC0_FREQ
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int "ADC0 frequency"
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default 4500000
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endmenu # ADC driver options
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menu "RS-485 Configuration"
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if LPC43_USART0
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@ -116,6 +116,10 @@ ifeq ($(CONFIG_LPC43_WWDT),y)
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CHIP_CSRCS += lpc43_wwdt.c
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endif
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ifeq ($(CONFIG_LPC43_SDMMC),y)
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CHIP_CSRCS += lpc43_sdmmc.c
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endif
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ifeq ($(CONFIG_LPC43_ETHERNET),y)
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CHIP_CSRCS += lpc43_ethernet.c
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endif
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@ -643,6 +643,31 @@
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# define BASE_VADC_CLKSEL_IDIVD (15 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVD */
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# define BASE_VADC_CLKSEL_IDIVE (16 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVE */
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/* Bits 29-31: Reserved */
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/* Output stage 13 control register (BASE_SDIO_CLK) */
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/* NOTE: Clocks 4-19 are identical */
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#define BASE_SDIO_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
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/* Bits 1-10: Reserved */
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#define BASE_SDIO_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
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/* Bits 12-23: Reserved */
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#define BASE_SDIO_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
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#define BASE_SDIO_CLK_CLKSEL_MASK (31 << BASE_SDIO_CLK_CLKSEL_SHIFT)
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# define BASE_SDIO_CLKSEL_32KHZOSC (0 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */
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# define BASE_SDIO_CLKSEL_IRC (1 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IRC (default) */
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# define BASE_SDIO_CLKSEL_ENET_RXCLK (2 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */
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# define BASE_SDIO_CLKSEL_ENET_TXCLK (3 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */
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# define BASE_SDIO_CLKSEL_GPCLKIN (4 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* GP_CLKIN */
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# define BASE_SDIO_CLKSEL_XTAL (6 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* Crystal oscillator */
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# define BASE_SDIO_CLKSEL_PLL0AUDIO (8 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */
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# define BASE_SDIO_CLKSEL_PLL1 (9 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* PLL1 */
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# define BASE_SDIO_CLKSEL_IDIVA (12 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVA */
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# define BASE_SDIO_CLKSEL_IDIVB (13 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVB */
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# define BASE_SDIO_CLKSEL_IDIVC (14 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVC */
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# define BASE_SDIO_CLKSEL_IDIVD (15 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVD */
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# define BASE_SDIO_CLKSEL_IDIVE (16 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVE */
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/* Bits 29-31: Reserved */
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/* Output stage 14 control register (BASE_SSP0_CLK) */
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/* NOTE: Clocks 4-19 are identical */
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@ -46,6 +46,11 @@
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* Pre-processor Definitions
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************************************************************************************************/
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#define LPC43_TXFIFO_DEPTH 32
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#define LPC43_TXFIFO_WIDTH 4
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#define LPC43_RXFIFO_DEPTH 32
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#define LPC43_RXFIFO_WIDTH 4
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/* MCI register offsets (with respect to the MCI base) ******************************************/
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#define LPC43_SDMMC_CTRL_OFFSET 0x0000 /* Control register */
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@ -156,12 +161,16 @@
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#define SDMMC_CLKDIV0_SHIFT (0) /* Bits 0-7: Clock divider 0 value */
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#define SDMMC_CLKDIV0_MASK (255 << SDMMC_CLKDIV0_SHIFT)
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# define SDMMC_CLKDIV0(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV0_SHIFT)
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#define SDMMC_CLKDIV1_SHIFT (8) /* Bits 8-15: Clock divider 1 value */
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#define SDMMC_CLKDIV1_MASK (255 << SDMMC_CLKDIV1_SHIFT)
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# define SDMMC_CLKDIV1(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV1_SHIFT)
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#define SDMMC_CLKDIV2_SHIFT (16) /* Bits 16-23: Clock divider 2 value */
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#define SDMMC_CLKDIV2_MASK (255 << SDMMC_CLKDIV2_SHIFT)
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# define SDMMC_CLKDIV2(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV2_SHIFT)
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#define SDMMC_CLKDIV3_SHIFT (24) /* Bits 24-31: Clock divider 3 value */
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#define SDMMC_CLKDIV3_MASK (255 << SDMMC_CLKDIV3_SHIFT)
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# define SDMMC_CLKDIV3(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV3_SHIFT)
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/* Clock source register CLKSRC */
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@ -217,7 +226,7 @@
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#define SDMMC_INT_SBE (1 << 13) /* Bit 13: Start-bit error */
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#define SDMMC_INT_ACD (1 << 14) /* Bit 14: Auto command done */
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#define SDMMC_INT_EBE (1 << 15) /* Bit 15: End-bit error (read)/Write no CRC */
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#define SDMMC_INT_SDIO (1 << 16) /* Bit 16: Mask SDIO interrupt */
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#define SDMMC_INT_SDIO (1 << 16) /* Bit 16: SDIO interrupt */
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/* Bits 17-31: Reserved */
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#define SDMMC_INT_ALL (0x1ffff)
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@ -227,6 +236,11 @@
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#define SDMMC_CMD_CMDINDEX_MASK (63 << SDMMC_CMD_CMDINDEX_SHIFT)
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#define SDMMC_CMD_RESPONSE (1 << 6) /* Bit 6: Response expected from card */
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#define SDMMC_CMD_LONGRESP (1 << 7) /* Bit 7: Long response expected from card */
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#define SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 6-7: Response expected */
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#define SDMMC_CMD_WAITRESP_MASK (3 << SDMMC_CMD_WAITRESP_SHIFT)
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# define SDMMC_CMD_NORESPONSE (0 << SDMMC_CMD_WAITRESP_SHIFT) /* x0: No response */
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# define SDMMC_CMD_SHORTRESPONSE (1 << SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */
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# define SDMMC_CMD_LONGRESPONSE (3 << SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */
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#define SDMMC_CMD_RESPCRC (1 << 8) /* Bit 8: Check response CRC */
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#define SDMMC_CMD_DATAXFREXPTD (1 << 9) /* Bit 9: Data transfer expected (read/write) */
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#define SDMMC_CMD_WRITE (1 << 10) /* Bit 10: Write to card */
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@ -285,9 +299,11 @@
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#define SDMMC_FIFOTH_TXWMARK_SHIFT (0) /* Bits 0-11: FIFO threshold level when transmitting */
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#define SDMMC_FIFOTH_TXWMARK_MASK (0xfff << SDMMC_FIFOTH_TXWMARK_SHIFT)
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# define SDMMC_FIFOTH_TXWMARK(n) ((uint32_t)(n) << SDMMC_FIFOTH_TXWMARK_SHIFT)
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/* Bits 12-15: Reserved */
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#define SDMMC_FIFOTH_RXWMARK_SHIFT (16) /* Bits 16-27: FIFO threshold level when receiving */
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#define SDMMC_FIFOTH_RXWMARK_MASK (0xfff << SDMMC_FIFOTH_RXWMARK_SHIFT)
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# define SDMMC_FIFOTH_RXWMARK(n) ((uint32_t)(n) << SDMMC_FIFOTH_RXWMARK_SHIFT)
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#define SDMMC_FIFOTH_DMABURST_SHIFT (28) /* Bits 28-30: Burst size for multiple transaction */
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#define SDMMC_FIFOTH_DMABURST_MASK (7 << SDMMC_FIFOTH_DMABURST_SHIFT)
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# define SDMMC_FIFOTH_DMABURST_1XFR (0 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 1 transfer */
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@ -323,6 +339,7 @@
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#define SDMMC_BMOD_FB (1 << 1) /* Bit 1: Fixed Burst */
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#define SDMMC_BMOD_DSL_SHIFT (2) /* Bits 2-6: Descriptor Skip Length */
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#define SDMMC_BMOD_DSL_MASK (31 << SDMMC_BMOD_DSL_SHIFT)
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# define SDMMC_BMOD_DSL(n) ((uint32_t)(n) << SDMMC_BMOD_DSL_SHIFT)
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#define SDMMC_BMOD_DE (1 << 7) /* Bit 7: SD/MMC DMA Enable */
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#define SDMMC_BMOD_PBL_SHIFT (8) /* Bits 8-10: Programmable Burst Length */
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#define SDMMC_BMOD_PBL_MASK (7 << SDMMC_BMOD_PBL_SHIFT)
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2732
arch/arm/src/lpc43xx/lpc43_sdmmc.c
Normal file
2732
arch/arm/src/lpc43xx/lpc43_sdmmc.c
Normal file
File diff suppressed because it is too large
Load Diff
88
arch/arm/src/lpc43xx/lpc43_sdmmc.h
Normal file
88
arch/arm/src/lpc43xx/lpc43_sdmmc.h
Normal file
@ -0,0 +1,88 @@
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/************************************************************************************
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* arch/arm/src/lpc43xx/lpc43_sdmmc.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_SDMMC_H
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#define __ARCH_ARM_SRC_LPC43XX_LPC43_SDMMC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdbool.h>
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#include "chip.h"
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#include "chip/lpc43_sdmmc.h"
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: lpc43_sdmmc_initialize
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*
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* Description:
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* Initialize the SD/MMC peripheral for normal operation.
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*
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* Input Parameters:
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* slotno - Not used.
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*
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* Returned Values:
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* A reference to an SDIO interface structure. NULL is returned on failures.
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*
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****************************************************************************/
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struct lpc43_sdmmc_dev_s; /* See include/nuttx/sdio.h */
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FAR struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_SDMMC_H */
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@ -1062,22 +1062,9 @@ static int lpc54_sdmmc_interrupt(int irq, void *context, FAR void *arg)
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}
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}
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/* Handle data end events. Note that RXDR may accompany DTO, DTO
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* will be set on received while there is still data in the FIFO.
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* So for the case of receiving, we don't actually even enable the
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* DTO interrupt.
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*/
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if ((pending & SDMMC_INT_DTO) != 0)
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{
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/* Finish the transfer */
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lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
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}
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/* Handle data block send/receive CRC failure */
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else if ((pending & SDMMC_INT_DCRC) != 0)
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if ((pending & SDMMC_INT_DCRC) != 0)
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{
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/* Terminate the transfer with an error */
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@ -1125,6 +1112,20 @@ static int lpc54_sdmmc_interrupt(int irq, void *context, FAR void *arg)
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mcerr("ERROR: Start bit, remaining: %d\n", priv->remaining);
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lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
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}
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/* Handle data end events. Note that RXDR may accompany DTO, DTO
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* will be set on received while there is still data in the FIFO.
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* So for the case of receiving, we don't actually even enable the
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* DTO interrupt.
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*/
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else if ((pending & SDMMC_INT_DTO) != 0)
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{
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/* Finish the transfer */
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lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
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}
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}
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/* Handle wait events *************************************************/
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@ -79,5 +79,10 @@ extern "C"
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struct lpc54_sdmmc_dev_s; /* See include/nuttx/sdio.h */
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FAR struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_SDMMC_H */
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Block a user