From 6f26d834b6d57c0aae503e9f2316bc7597d945cd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Apr 2014 14:51:53 -0600 Subject: [PATCH] LPC17xx, TIVA, and Kinetis interrupt initialization: use the NVIC ICTR register to determine how many interrupt lines/registers are supported by the MCU --- arch/arm/src/kinetis/kinetis_irq.c | 74 ++++++++++++++---------------- arch/arm/src/lpc17xx/lpc17_irq.c | 49 ++++++++++++++------ arch/arm/src/tiva/tiva_irq.c | 51 +++++++++++++------- 3 files changed, 103 insertions(+), 71 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index 3ab9d3cba9..f3b17c217a 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -315,12 +315,31 @@ static int kinetis_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, void up_irqinitialize(void) { - /* Disable all interrupts */ + int nintlines; + int i; - putreg32(0, NVIC_IRQ0_31_ENABLE); - putreg32(0, NVIC_IRQ32_63_ENABLE); - putreg32(0, NVIC_IRQ64_95_ENABLE); - putreg32(0, NVIC_IRQ96_127_ENABLE); + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based * vector table that requires special initialization. @@ -330,47 +349,22 @@ void up_irqinitialize(void) up_ramvec_initialize(); #endif - /* Set all interrrupts (and exceptions) to the default priority */ + /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ - putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ48_51_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ52_55_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ56_59_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ60_63_PRIORITY); - - putreg32(DEFPRIORITY32, NVIC_IRQ64_67_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ68_71_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ72_75_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ76_79_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ80_83_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ84_87_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ88_91_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ92_95_PRIORITY); - - putreg32(DEFPRIORITY32, NVIC_IRQ96_99_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ100_103_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ104_107_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ108_111_PRIORITY); /* K40 has 111 defined vectors */ -#if NR_VECTORS > 111 - putreg32(DEFPRIORITY32, NVIC_IRQ112_115_PRIORITY); /* K60 has 120 defined vectors */ - putreg32(DEFPRIORITY32, NVIC_IRQ116_119_PRIORITY); -#endif + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(DEFPRIORITY32, regaddr); + } /* currents_regs is non-NULL only while processing an interrupt */ diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c index 6b163d257f..9bb811cb99 100644 --- a/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/arch/arm/src/lpc17xx/lpc17_irq.c @@ -287,9 +287,31 @@ static int lpc17_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, void up_irqinitialize(void) { - /* Disable all interrupts */ + int nintlines; + int i; - putreg32(0, NVIC_IRQ0_31_ENABLE); + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based * vector table that requires special initialization. @@ -299,25 +321,22 @@ void up_irqinitialize(void) up_ramvec_initialize(); #endif - /* Set all interrrupts (and exceptions) to the default priority */ + /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ - putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(DEFPRIORITY32, regaddr); + } /* currents_regs is non-NULL only while processing an interrupt */ diff --git a/arch/arm/src/tiva/tiva_irq.c b/arch/arm/src/tiva/tiva_irq.c index 0052cb8dd5..8f115964b1 100644 --- a/arch/arm/src/tiva/tiva_irq.c +++ b/arch/arm/src/tiva/tiva_irq.c @@ -289,10 +289,31 @@ static int tiva_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, void up_irqinitialize(void) { - /* Disable all interrupts */ + int nintlines; + int i; - putreg32(0, NVIC_IRQ0_31_ENABLE); - putreg32(0, NVIC_IRQ32_63_ENABLE); + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based * vector table that requires special initialization. @@ -302,24 +323,22 @@ void up_irqinitialize(void) up_ramvec_initialize(); #endif - /* Set all interrrupts (and exceptions) to the default priority */ + /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ + + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(DEFPRIORITY32, regaddr); + } /* currents_regs is non-NULL only while processing an interrupt */