arch/arm/src/tiva/hardware/: Add VIMS header file.
This commit is contained in:
Gregory Nutt
parent
379a3b4bd5
commit
6f418dd9f3
@ -52,7 +52,7 @@
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* Pre-processor Definitions
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********************************************************************************************************************/
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/* FCFG1 Register Offsets *******************************************************************************************/
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/* AON IOC Register Offsets *****************************************************************************************/
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#define TIVA_AON_IOC_IOSTRMIN_OFFSET 0x0000
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#define TIVA_AON_IOC_IOSTRMED_OFFSET 0x0004
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@ -61,7 +61,7 @@
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#define TIVA_AON_IOC_CLK32KCTL_OFFSET 0x0010 /* SCLK_LF External Output Control */
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#define TIVA_AON_IOC_TCKCTL_OFFSET 0x0014 /* TCK IO Pin Control */
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/* FCFG1 Register Addresses *****************************************************************************************/
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/* AON IOC Register Addresses ***************************************************************************************/
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#define TIVA_AON_IOC_IOSTRMIN (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET)
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#define TIVA_AON_IOC_IOSTRMED (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET)
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@ -69,7 +69,7 @@
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#define TIVA_AON_IOC_IOCLATCH (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOCLATCH_OFFSET)
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#define TIVA_AON_IOC_CLK32KCTL (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET)
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/* FCFG1 Register Offsets *******************************************************************************************/
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/* AON IOC Bitfield Definitions *************************************************************************************/
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/* TIVA_AON_IOC_IOSTRMIN */
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96
arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h
Normal file
96
arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h
Normal file
@ -0,0 +1,96 @@
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/********************************************************************************************************************
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* arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_VIMS_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_VIMS_H
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/********************************************************************************************************************
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* Included Files
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********************************************************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/tiva_memorymap.h"
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/********************************************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************************************/
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/* VIMS Register Offsets ********************************************************************************************/
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#define TIVA_VIMS_STAT_OFFSET 0x0000 /* Status */
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#define TIVA_VIMS_CTL_OFFSET 0x0004 /* Status */
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/* VIMS Register Addresses ******************************************************************************************/
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#define TIVA_VIMS_STAT (TIVA_VIMS_BASE + TIVA_VIMS_STAT_OFFSET)
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#define TIVA_VIMS_CTL (TIVA_VIMS_BASE + TIVA_VIMS_CTL_OFFSET)
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/* VIMS Bitfield Definitions ****************************************************************************************/
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/* VIMS_STAT */
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#define VIMS_STAT_MODE_SHIFT (0) /* Bits 0-1: Current VMS mode */
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#define VIMS_STAT_MODE_MASK (3 << VIMS_STAT_MODE_SHIFT)
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# define VIMS_STAT_MODE_GPRAM (0 << VIMS_STAT_MODE_SHIFT) /* VIMS GPRAM mode */
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# define VIMS_STAT_MODE_CACHE (1 << VIMS_STAT_MODE_SHIFT) /* VIMS Cache mode */
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# define VIMS_STAT_MODE_OFF (3 << VIMS_STAT_MODE_SHIFT) /* VIMS Off mode */
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#define VIMS_STAT_INV (1 << 2) /* Bit 2: Invalidation of caching memory in-progress */
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#define VIMS_STAT_MODE_CHANGING (1 << 3) /* Bit 3: VIMS mode change status */
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#define VIMS_STAT_SYSBUS_LB_DIS (1 << 4) /* Bit 4: Sysbus flash line buffer control */
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#define VIMS_STAT_IDCODE_LB_DIS (1 << 5) /* Bit 5: Icode/Dcode flash line buffer status */
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/* VIMS_CTL */
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#define VIMS_CTL_MODE_SHIFT (0) /* Bits 0-1: Current VMS mode */
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#define VIMS_CTL_MODE_MASK (3 << VIMS_CTL_MODE_SHIFT)
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# define VIMS_CTL_MODE_GPRAM (0 << VIMS_CTL_MODE_SHIFT) /* VIMS GPRAM mode */
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# define VIMS_CTL_MODE_CACHE (1 << VIMS_CTL_MODE_SHIFT) /* VIMS Cache mode */
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# define VIMS_CTL_MODE_OFF (3 << VIMS_CTL_MODE_SHIFT) /* VIMS Off mode */
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#define VIMS_CTL_PREF_EN (1 << 2) /* Bit 2: Tag prefetch control */
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#define VIMS_CTL_ARB_CFG (1 << 3) /* Bit 3: Icode/Dcode and sysbus arbitation scheme */
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# define VIMS_CTL_ARB_STATIC (0)
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# define VIMS_CTL_ARB_ROUNDROBIN VIMS_CTL_ARB_CFG
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#define VIMS_CTL_SYSBUS_LB_DIS (1 << 4) /* Bit 4: Sysbus flash line buffer control */
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#define VIMS_CTL_IDCODE_LB_DIS (1 << 5) /* Bit 5: Icode/Dcode flash line buffer control */
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#define VIMS_CTL_DYN_CG_EN (1 << 29) /* Bit 29: Enable in-built clock gate */
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#define VIMS_CTL_STATS_EN (1 << 30) /* Bit 30: Enable statistic counters */
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#define VIMS_CTL_STATS_CLR (1 << 31) /* Bit 31: Clear statistics counters */
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#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_VIMS_H */
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@ -52,7 +52,7 @@
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* Pre-processor Definitions
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********************************************************************************************************************/
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/* FCFG1 Register Offsets *******************************************************************************************/
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/* AON IOC Register Offsets *****************************************************************************************/
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#define TIVA_AON_IOC_IOSTRMIN_OFFSET 0x0000
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#define TIVA_AON_IOC_IOSTRMED_OFFSET 0x0004
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@ -61,7 +61,7 @@
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#define TIVA_AON_IOC_CLK32KCTL_OFFSET 0x0010 /* SCLK_LF External Output Control */
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#define TIVA_AON_IOC_TCKCTL_OFFSET 0x0014 /* TCK IO Pin Control */
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/* FCFG1 Register Addresses *****************************************************************************************/
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/* AON IOC Register Addresses ***************************************************************************************/
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#define TIVA_AON_IOC_IOSTRMIN (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET)
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#define TIVA_AON_IOC_IOSTRMED (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET)
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@ -70,7 +70,7 @@
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#define TIVA_AON_IOC_CLK32KCTL (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET)
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#define TIVA_AON_IOC_TCKCTL (TIVA_TIVA_AON_IOC_BASE + TIVA_AON_IOC_TCKCTL_OFFSET)
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/* FCFG1 Register Offsets *******************************************************************************************/
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/* AON IOC Bitfield Definitions *************************************************************************************/
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/* TIVA_AON_IOC_IOSTRMIN */
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@ -0,0 +1,96 @@
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/********************************************************************************************************************
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* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_vims.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_VIMS_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_VIMS_H
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/********************************************************************************************************************
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* Included Files
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********************************************************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/tiva_memorymap.h"
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/********************************************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************************************/
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/* VIMS Register Offsets ********************************************************************************************/
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#define TIVA_VIMS_STAT_OFFSET 0x0000 /* Status */
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#define TIVA_VIMS_CTL_OFFSET 0x0004 /* Status */
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/* VIMS Register Addresses ******************************************************************************************/
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#define TIVA_VIMS_STAT (TIVA_VIMS_BASE + TIVA_VIMS_STAT_OFFSET)
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#define TIVA_VIMS_CTL (TIVA_VIMS_BASE + TIVA_VIMS_CTL_OFFSET)
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/* VIMS Bitfield Definitions ****************************************************************************************/
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/* VIMS_STAT */
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#define VIMS_STAT_MODE_SHIFT (0) /* Bits 0-1: Current VMS mode */
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#define VIMS_STAT_MODE_MASK (3 << VIMS_STAT_MODE_SHIFT)
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# define VIMS_STAT_MODE_GPRAM (0 << VIMS_STAT_MODE_SHIFT) /* VIMS GPRAM mode */
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# define VIMS_STAT_MODE_CACHE (1 << VIMS_STAT_MODE_SHIFT) /* VIMS Cache mode */
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# define VIMS_STAT_MODE_OFF (3 << VIMS_STAT_MODE_SHIFT) /* VIMS Off mode */
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#define VIMS_STAT_INV (1 << 2) /* Bit 2: Invalidation of caching memory in-progress */
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#define VIMS_STAT_MODE_CHANGING (1 << 3) /* Bit 3: VIMS mode change status */
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#define VIMS_STAT_SYSBUS_LB_DIS (1 << 4) /* Bit 4: Sysbus flash line buffer control */
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#define VIMS_STAT_IDCODE_LB_DIS (1 << 5) /* Bit 5: Icode/Dcode flash line buffer status */
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/* VIMS_CTL */
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#define VIMS_CTL_MODE_SHIFT (0) /* Bits 0-1: Current VMS mode */
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#define VIMS_CTL_MODE_MASK (3 << VIMS_CTL_MODE_SHIFT)
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# define VIMS_CTL_MODE_GPRAM (0 << VIMS_CTL_MODE_SHIFT) /* VIMS GPRAM mode */
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# define VIMS_CTL_MODE_CACHE (1 << VIMS_CTL_MODE_SHIFT) /* VIMS Cache mode */
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# define VIMS_CTL_MODE_OFF (3 << VIMS_CTL_MODE_SHIFT) /* VIMS Off mode */
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#define VIMS_CTL_PREF_EN (1 << 2) /* Bit 2: Tag prefetch control */
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#define VIMS_CTL_ARB_CFG (1 << 3) /* Bit 3: Icode/Dcode and sysbus arbitation scheme */
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# define VIMS_CTL_ARB_STATIC (0)
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# define VIMS_CTL_ARB_ROUNDROBIN VIMS_CTL_ARB_CFG
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#define VIMS_CTL_SYSBUS_LB_DIS (1 << 4) /* Bit 4: Sysbus flash line buffer control */
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#define VIMS_CTL_IDCODE_LB_DIS (1 << 5) /* Bit 5: Icode/Dcode flash line buffer control */
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#define VIMS_CTL_DYN_CG_EN (1 << 29) /* Bit 29: Enable in-built clock gate */
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#define VIMS_CTL_STATS_EN (1 << 30) /* Bit 30: Enable statistic counters */
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#define VIMS_CTL_STATS_CLR (1 << 31) /* Bit 31: Clear statistics counters */
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#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_VIMS_H */
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