Add Kinetis CMT and RTC header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3862 42af7a65-404d-4744-a932-0658087f49c3
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138
arch/arm/src/kinetis/kinetis_cmt.h
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138
arch/arm/src/kinetis/kinetis_cmt.h
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/************************************************************************************
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* arch/arm/src/kinetis/kinetis_cmt.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CMT_H
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#define __ARCH_ARM_SRC_KINETIS_KINETIS_CMT_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define KINETIS_CMT_CGH1_OFFSET 0x0000 /* CMT Carrier Generator High Data Register 1 */
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#define KINETIS_CMT_CGL1_OFFSET 0x0001 /* CMT Carrier Generator Low Data Register 1 */
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#define KINETIS_CMT_CGH2_OFFSET 0x0002 /* CMT Carrier Generator High Data Register 2 */
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#define KINETIS_CMT_CGL2_OFFSET 0x0003 /* CMT Carrier Generator Low Data Register 2 */
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#define KINETIS_CMT_OC_OFFSET 0x0004 /* CMT Output Control Register */
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#define KINETIS_CMT_MSC_OFFSET 0x0005 /* CMT Modulator Status and Control Register */
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#define KINETIS_CMT_CMD1_OFFSET 0x0006 /* CMT Modulator Data Register Mark High */
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#define KINETIS_CMT_CMD2_OFFSET 0x0007 /* CMT Modulator Data Register Mark Low */
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#define KINETIS_CMT_CMD3_OFFSET 0x0008 /* CMT Modulator Data Register Space High */
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#define KINETIS_CMT_CMD4_OFFSET 0x0009 /* CMT Modulator Data Register Space Low */
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#define KINETIS_CMT_PPS_OFFSET 0x000a /* CMT Primary Prescaler Register */
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#define KINETIS_CMT_DMA_OFFSET 0x000b /* CMT Direct Memory Access */
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/* Register Addresses ***************************************************************/
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#define KINETIS_CMT_CGH1 (KINETIS_CMT_BASE+KINETIS_CMT_CGH1_OFFSET)
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#define KINETIS_CMT_CGL1 (KINETIS_CMT_BASE+KINETIS_CMT_CGL1_OFFSET)
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#define KINETIS_CMT_CGH2 (KINETIS_CMT_BASE+KINETIS_CMT_CGH2_OFFSET)
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#define KINETIS_CMT_CGL2 (KINETIS_CMT_BASE+KINETIS_CMT_CGL2_OFFSET)
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#define KINETIS_CMT_OC (KINETIS_CMT_BASE+KINETIS_CMT_OC_OFFSET)
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#define KINETIS_CMT_MSC (KINETIS_CMT_BASE+KINETIS_CMT_MSC_OFFSET)
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#define KINETIS_CMT_CMD1 (KINETIS_CMT_BASE+KINETIS_CMT_CMD1_OFFSET)
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#define KINETIS_CMT_CMD2 (KINETIS_CMT_BASE+KINETIS_CMT_CMD2_OFFSET)
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#define KINETIS_CMT_CMD3 (KINETIS_CMT_BASE+KINETIS_CMT_CMD3_OFFSET)
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#define KINETIS_CMT_CMD4 (KINETIS_CMT_BASE+KINETIS_CMT_CMD4_OFFSET)
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#define KINETIS_CMT_PPS (KINETIS_CMT_BASE+KINETIS_CMT_PPS_OFFSET)
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#define KINETIS_CMT_DMA (KINETIS_CMT_BASE+KINETIS_CMT_DMA_OFFSET)
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/* Register Bit Definitions *********************************************************/
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/* CMT Carrier Generator High/Low Data Register 1 (8-bit Primary Carrier High Time
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* Data Value)
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*/
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/* CMT Carrier Generator High/Low Data Register 2 (8-bit Secondary Carrier High Time
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* Data Value)
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*/
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/* CMT Output Control Register (8-bit) */
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/* Bits 0-4: Reserved */
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#define CMT_OC_IROPEN (1 << 5) /* Bit 5: IRO Pin Enable */
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#define CMT_OC_CMTPOL (1 << 6) /* Bit 6: CMT Output Polarity */
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#define CMT_OC_IROL (1 << 7) /* Bit 7: IRO Latch Control */
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/* CMT Modulator Status and Control Register (8-bit) */
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#define CMT_MSC_MCGEN (1 << 0) /* Bit 0: Modulator and Carrier Generator Enable */
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#define CMT_MSC_EOCIE (1 << 1) /* Bit 1: End of Cycle Interrupt Enable */
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#define CMT_MSC_FSK (1 << 2) /* Bit 2: FSK Mode Select */
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#define CMT_MSC_BASE (1 << 3) /* Bit 3: Baseband Enable */
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#define CMT_MSC_EXSPC (1 << 4) /* Bit 4: Extended Space Enable */
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#define CMT_MSC_CMTDIV_SHIFT (5) /* Bits 5-6: CMT Clock Divide Prescaler */
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#define CMT_MSC_CMTDIV_MASK (3 << CMT_MSC_CMTDIV_SHIFT)
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# define CMT_MSC_CMTDIV_DIV1 (0 << CMT_MSC_CMTDIV_SHIFT) /* IF / 1 */
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# define CMT_MSC_CMTDIV_DIV2 (1 << CMT_MSC_CMTDIV_SHIFT) /* IF / 2 */
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# define CMT_MSC_CMTDIV_DIV4 (2 << CMT_MSC_CMTDIV_SHIFT) /* IF / 4 */
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# define CMT_MSC_CMTDIV_DIV8 (3 << CMT_MSC_CMTDIV_SHIFT) /* IF / 8 */
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#define CMT_MSC_EOCF (1 << 7) /* Bit 7: End Of Cycle Status Flag */
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/* CMT Modulator Data Register Mark High/Low (8-bit command data) */
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/* CMT Modulator Data Register Space High/Low (8-bit command data)*/
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/* CMT Primary Prescaler Register (8-bit) */
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#define CMT_PPS_SHIFT (0) /* Bits 0-3: Primary Prescaler Divider */
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#define CMT_PPS_MASK (15 << CMT_PPS_SHIFT)
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# define CMT_PPS_DIV(n) (((n)-1) << CMT_PPS_SHIFT) /* Bus clock / n, n=1..16 */
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/* Bits 4-7: Reserved */
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/* CMT Direct Memory Access (8-bit) */
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#define CMT_DMA_ENABLE (1 << 0) /* Bit 0: DMA Enable
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/* Bits 1-7: Reserved */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CMT_H */
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171
arch/arm/src/kinetis/kinetis_rtc.h
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171
arch/arm/src/kinetis/kinetis_rtc.h
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/************************************************************************************
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* arch/arm/src/kinetis/kinetis_rtc.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H
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#define __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define KINETIS_RTC_TSR_OFFSET 0x0000 /* RTC Time Seconds Register */
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#define KINETIS_RTC_TPR_OFFSET 0x0004 /* RTC Time Prescaler Register */
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#define KINETIS_RTC_TAR_OFFSET 0x0008 /* RTC Time Alarm Register */
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#define KINETIS_RTC_TCR_OFFSET 0x000c /* RTC Time Compensation Register */
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#define KINETIS_RTC_CR_OFFSET 0x0010 /* RTC Control Register */
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#define KINETIS_RTC_SR_OFFSET 0x0014 /* RTC Status Register */
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#define KINETIS_RTC_LR_OFFSET 0x0018 /* RTC Lock Register */
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#define KINETIS_RTC_IER_OFFSET 0x001c /* RTC Interrupt Enable Register */
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#define KINETIS_RTC_WAR_OFFSET 0x0800 /* RTC Write Access Register */
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#define KINETIS_RTC_RAR_OFFSET 0x0804 /* RTC Read Access Register */
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/* Register Addresses ***************************************************************/
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#define KINETIS_RTC_TSR (KINETIS_RTC_BASE+KINETIS_RTC_TSR_OFFSET)
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#define KINETIS_RTC_TPR (KINETIS_RTC_BASE+KINETIS_RTC_TPR_OFFSET)
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#define KINETIS_RTC_TAR (KINETIS_RTC_BASE+KINETIS_RTC_TAR_OFFSET)
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#define KINETIS_RTC_TCR (KINETIS_RTC_BASE+KINETIS_RTC_TCR_OFFSET)
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#define KINETIS_RTC_CR (KINETIS_RTC_BASE+KINETIS_RTC_CR_OFFSET)
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#define KINETIS_RTC_SR (KINETIS_RTC_BASE+KINETIS_RTC_SR_OFFSET)
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#define KINETIS_RTC_LR (KINETIS_RTC_BASE+KINETIS_RTC_LR_OFFSET)
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#define KINETIS_RTC_IER (KINETIS_RTC_BASE+KINETIS_RTC_IER_OFFSET)
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#define KINETIS_RTC_WAR (KINETIS_RTC_BASE+KINETIS_RTC_WAR_OFFSET)
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#define KINETIS_RTC_RAR (KINETIS_RTC_BASE+KINETIS_RTC_RAR_OFFSET)
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/* Register Bit Definitions *********************************************************/
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/* RTC Time Seconds Register (32-bits of time in seconds) */
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/* RTC Time Prescaler Register */
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#define RTC_TPR_SHIFT (0) /* Bits 0-15: Time Prescaler Register */
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#define RTC_TPR_MASK (0xffff << RTC_TPR_SHIFT)
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/* Bits 16-31: Reserved */
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/* RTC Time Alarm Register (32-bits of time alarm) */
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/* RTC Time Compensation Register (32-bits) */
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#define RTC_TCR_TCR_SHIFT (0) /* Bits 0-7: Time Compensation Register */
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#define RTC_TCR_TCR_MASK (0xff << RTC_TCR_CIR_MASK)
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#define RTC_TCR_CIR_SHIFT (8) /* Bits 8-15: Compensation Interval Register */
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#define RTC_TCR_CIR_MASK (0xff << RTC_TCR_CIR_SHIFT)
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#define RTC_TCR_TCV_SHIFT (16) /* Bits 16-23: Time Compensation Value */
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#define RTC_TCR_TCV_MASK (0xff << RTC_TCR_TCV_SHIFT)
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#define RTC_TCR_CIC_SHIFT (24) /* Bits 24-31: Compensation Interval Counter */
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#define RTC_TCR_CIC_MASK (0xff << RTC_TCR_CIC_SHIFT)
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/* RTC Control Register (32-bits) */
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#define RTC_CR_SWR (1 << 0) /* Bit 0: Software Reset */
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#define RTC_CR_WPE (1 << 1) /* Bit 1: Wakeup Pin Enable */
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#define RTC_CR_SUP (1 << 2) /* Bit 2: Supervisor Access */
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#define RTC_CR_UM (1 << 3) /* Bit 3: Update Mode */
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/* Bits 4-7: Reserved */
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#define RTC_CR_OSCE (1 << 8) /* Bit 8: Oscillator Enable */
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#define RTC_CR_CLKO (1 << 9) /* Bit 9: Clock Output */
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#define RTC_CR_SC16P (1 << 10) /* Bit 10: Oscillator 16pF load configure */
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#define RTC_CR_SC8P (1 << 11) /* Bit 11: Oscillator 8pF load configure */
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#define RTC_CR_SC4P (1 << 12) /* Bit 12: Oscillator 4pF load configure */
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#define RTC_CR_SC2P (1 << 13) /* Bit 13: Oscillator 2pF load configure */
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/* Bits 14-31: Reserved */
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/* RTC Status Register (32-bits) */
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#define RTC_SR_TIF (1 << 0) /* Bit 0: Time Invalid Flag */
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#define RTC_SR_TOF (1 << 1) /* Bit 1: Time Overflow Flag */
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/* Bit 3: Reserved */
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#define RTC_SR_TAF (1 << 2) /* Bit 2: Time Alarm Flag */
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#define RTC_SR_TCE (1 << 4) /* Bit 4: Time Counter Enable */
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/* Bits 5-31: Reserved */
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/* RTC Lock Register (32-bits) */
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/* Bits 0-2: Reserved */
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#define RTC_LR_TCL (1 << 3) /* Bit 3: Time Compensation Lock */
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#define RTC_LR_CRL (1 << 4) /* Bit 4: Control Register Lock */
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#define RTC_LR_SRL (1 << 5) /* Bit 5: Status Register Lock */
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#define RTC_LR_LRL (1 << 6) /* Bit 6: Lock Register Lock */
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/* Bits 7-31: Reserved */
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/* RTC Interrupt Enable Register (32-bits) */
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#define RTC_IER_TIIE (1 << 0) /* Bit 0: Time Invalid Interrupt Enable */
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#define RTC_IER_TOIE (1 << 1) /* Bit 1: Time Overflow Interrupt Enable */
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#define RTC_IER_TAIE (1 << 2) /* Bit 2: Time Alarm Interrupt Enable */
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/* Bit 3: Reserved */
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#define RTC_IER_TSIE (1 << 4) /* Bit 4: Time Seconds Interrupt Enable */
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/* Bits 5-31: Reserved */
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/* RTC Write Access Register (32-bits) */
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#define RTC_WAR_TSRW (1 << 0) /* Bit 0: Time Seconds Register Write */
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#define RTC_WAR_TPRW (1 << 1) /* Bit 1: Time Prescaler Register Write */
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#define RTC_WAR_TARW (1 << 2) /* Bit 2: Time Alarm Register Write */
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#define RTC_WAR_TCRW (1 << 3) /* Bit 3: Time Compensation Register Write */
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#define RTC_WAR_CRW (1 << 4) /* Bit 4: Control Register Write */
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#define RTC_WAR_SRW (1 << 5) /* Bit 5: Status Register Write */
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#define RTC_WAR_LRW (1 << 6) /* Bit 6: Lock Register Write */
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#define RTC_WAR_IERW (1 << 7) /* Bit 7: Interrupt Enable Register Write */
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/* Bits 8-31: Reserved */
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/* RTC Read Access Register */
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#define RTC_RAR_TSRR (1 << 0) /* Bit 0: Time Seconds Register Read */
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#define RTC_RAR_TPRR (1 << 1) /* Bit 1: Time Prescaler Register Read */
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#define RTC_RAR_TARR (1 << 2) /* Bit 2: Time Alarm Register Read */
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#define RTC_RAR_TCRR (1 << 3) /* Bit 3: Time Compensation Register Read */
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#define RTC_RAR_CRR (1 << 4) /* Bit 4: Control Register Read */
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#define RTC_RAR_SRR (1 << 5) /* Bit 5: Status Register Read */
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#define RTC_RAR_LRR (1 << 6) /* Bit 6: Lock Register Read */
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#define RTC_RAR_IERR (1 << 7) /* Bit 7: Interrupt Enable Register Read */
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/* Bits 8-31: Reserved */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H */
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