ESP32: Add initial serial driver. Taken from SAMV7; not fully converted. Does not yet compile.
This commit is contained in:
Gregory Nutt
parent
bc51fdb96c
commit
6f7c03bd71
@ -39,7 +39,8 @@
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#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000 + (i > 1 ? 0xe000 : 0))
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#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
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#define UART_FIFO_OFFSET 0x00
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#define UART_FIFO_REG(i) (REG_UART_BASE(i) + UART_FIFO_OFFSET)
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/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
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/* Description: This register stores one byte data read by rx fifo.*/
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@ -49,7 +50,8 @@
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#define UART_RXFIFO_RD_BYTE_V 0xFF
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#define UART_RXFIFO_RD_BYTE_S 0
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#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
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#define UART_INT_RAW_OFFSET 0x04
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#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + UART_INT_RAW_OFFSET)
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/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
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/* Description: This interrupt raw bit turns to high level when receiver
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@ -241,7 +243,8 @@
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#define UART_RXFIFO_FULL_INT_RAW_V 0x1
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#define UART_RXFIFO_FULL_INT_RAW_S 0
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#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
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#define UART_INT_ST_OFFSET 0x08
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#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + UART_INT_ST_OFFSET)
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/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
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/* Description: This is the status bit for at_cmd_det_int_raw when
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@ -432,7 +435,8 @@
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#define UART_RXFIFO_FULL_INT_ST_V 0x1
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#define UART_RXFIFO_FULL_INT_ST_S 0
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#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC)
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#define UART_INT_ENA_OFFSET 0x0c
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#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + UART_INT_ENA_OFFSET)
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/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
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/* Description: This is the enable bit for at_cmd_char_det_int_st register.*/
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@ -586,7 +590,8 @@
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#define UART_RXFIFO_FULL_INT_ENA_V 0x1
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#define UART_RXFIFO_FULL_INT_ENA_S 0
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#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
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#define UART_INT_CLR_OFFSET 0x10
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#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + UART_INT_CLR_OFFSET)
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/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
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/* Description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
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@ -744,7 +749,8 @@
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#define UART_RXFIFO_FULL_INT_CLR_V 0x1
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#define UART_RXFIFO_FULL_INT_CLR_S 0
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#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14)
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#define UART_CLKDIV_OFFSET 0x14
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#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + UART_CLKDIV_OFFSET)
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/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
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/* Description: The register value is the decimal part of the frequency
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@ -766,7 +772,8 @@
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#define UART_CLKDIV_V 0xFFFFF
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#define UART_CLKDIV_S 0
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#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18)
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#define UART_AUTOBAUD_OFFSET 0x18
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#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + UART_AUTOBAUD_OFFSET)
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/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */
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/* Description: when input pulse width is lower then this value igore this
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@ -786,7 +793,8 @@
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#define UART_AUTOBAUD_EN_V 0x1
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#define UART_AUTOBAUD_EN_S 0
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#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C)
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#define UART_STATUS_OFFSET 0x1c
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#define UART_STATUS_REG(i) (REG_UART_BASE(i) + UART_STATUS_OFFSET)
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/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */
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/* Description: This register represent the level value of the internal
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@ -895,7 +903,8 @@
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#define UART_RXFIFO_CNT_V 0xFF
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#define UART_RXFIFO_CNT_S 0
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#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)
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#define UART_CONF0_OFFSET 0x20
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#define UART_CONF0_REG(i) (REG_UART_BASE(i) + UART_CONF0_OFFSET)
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/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */
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/* Description: This register is used to select the clock.1.apb clock
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@ -1127,7 +1136,8 @@
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#define UART_PARITY_V 0x1
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#define UART_PARITY_S 0
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#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
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#define UART_CONF1_OFFSET 0x24
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#define UART_CONF1_REG(i) (REG_UART_BASE(i) + UART_CONF1_OFFSET)
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/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
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/* Description: This is the enble bit for uart receiver's timeout function.*/
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@ -1190,7 +1200,8 @@
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#define UART_RXFIFO_FULL_THRHD_V 0x7F
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#define UART_RXFIFO_FULL_THRHD_S 0
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#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)
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#define UART_LOWPULSE_OFFSET 0x28
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#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + UART_LOWPULSE_OFFSET)
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/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
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/* Description: This register stores the value of the minimum duration time
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@ -1202,7 +1213,8 @@
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#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF
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#define UART_LOWPULSE_MIN_CNT_S 0
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#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C)
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#define UART_HIGHPULSE_OFFSET 0x2c
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#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + UART_HIGHPULSE_OFFSET)
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/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
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/* Description: This register stores the value of the maxinum duration time
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@ -1214,7 +1226,8 @@
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#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF
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#define UART_HIGHPULSE_MIN_CNT_S 0
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#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
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#define UART_RXD_CNT_OFFSET 0x30
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#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + UART_RXD_CNT_OFFSET)
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/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
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/* Description: This register stores the count of rxd edge change. it is
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@ -1226,7 +1239,8 @@
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#define UART_RXD_EDGE_CNT_V 0x3FF
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#define UART_RXD_EDGE_CNT_S 0
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#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)
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#define UART_FLOW_CONF_OFFSET 0x34
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#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + UART_FLOW_CONF_OFFSET)
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/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */
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/* Description: Set this bit to send xoff char. it is cleared by hardware
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@ -1288,7 +1302,8 @@
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#define UART_SW_FLOW_CON_EN_V 0x1
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#define UART_SW_FLOW_CON_EN_S 0
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#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
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#define UART_SLEEP_CONF_OFFSET 0x38
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#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + UART_SLEEP_CONF_OFFSET)
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/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
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/* Description: When the input rxd edge changes more than this register
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@ -1300,7 +1315,8 @@
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#define UART_ACTIVE_THRESHOLD_V 0x3FF
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#define UART_ACTIVE_THRESHOLD_S 0
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#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C)
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#define UART_SWFC_CONF_OFFSET 0x3c
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#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + UART_SWFC_CONF_OFFSET)
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/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */
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/* Description: This register stores the xoff flow control char.*/
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@ -1340,7 +1356,8 @@
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#define UART_XON_THRESHOLD_V 0xFF
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#define UART_XON_THRESHOLD_S 0
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#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40)
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#define UART_IDLE_CONF_OFFSET 0x40
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#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + UART_IDLE_CONF_OFFSET)
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/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */
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/* Description: This register is used to configure the num of 0 send after
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@ -1374,7 +1391,8 @@
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#define UART_RX_IDLE_THRHD_V 0x3FF
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#define UART_RX_IDLE_THRHD_S 0
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#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44)
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#define UART_RS485_CONF_OFFSET 0x44
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#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + UART_RS485_CONF_OFFSET)
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/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
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/* Description: This register is used to delay the transmitter's internal
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@ -1441,6 +1459,7 @@
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#define UART_RS485_EN_V 0x1
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#define UART_RS485_EN_S 0
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#define UART_AT_CMD_PRECNT_OFFSET 0x48
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#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48)
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/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
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@ -1455,7 +1474,8 @@
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#define UART_PRE_IDLE_NUM_V 0xFFFFFF
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#define UART_PRE_IDLE_NUM_S 0
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#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c)
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#define UART_AT_CMD_POSTCNT_OFFSET 0x4c
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#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + UART_AT_CMD_POSTCNT_OFFSET)
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/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
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/* Description: This register is used to configure the duration time between
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@ -1468,6 +1488,7 @@
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#define UART_POST_IDLE_NUM_V 0xFFFFFF
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#define UART_POST_IDLE_NUM_S 0
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#define UART_AT_CMD_GAPTOUT_OFFSET 0x50
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#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50)
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/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */
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@ -1481,7 +1502,8 @@
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#define UART_RX_GAP_TOUT_V 0xFFFFFF
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#define UART_RX_GAP_TOUT_S 0
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#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54)
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#define UART_AT_CMD_CHAR_OFFSET 0x54
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#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + UART_AT_CMD_CHAR_OFFSET)
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/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
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/* Description: This register is used to configure the num of continous
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@ -1503,7 +1525,8 @@
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#define UART_AT_CMD_CHAR_V 0xFF
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#define UART_AT_CMD_CHAR_S 0
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#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58)
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#define UART_MEM_CONF_OFFSET 0x58
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#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + UART_MEM_CONF_OFFSET)
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/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
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/* Description: refer to txfifo_empty_thrhd 's describtion.*/
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@ -1583,7 +1606,8 @@
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#define UART_MEM_PD_V 0x1
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#define UART_MEM_PD_S 0
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#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c)
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#define UART_MEM_TX_STATUS_OFFSET 0x5c
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#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + UART_MEM_TX_STATUS_OFFSET)
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/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */
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/* Description: */
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@ -1593,7 +1617,8 @@
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#define UART_MEM_TX_STATUS_V 0xFFFFFF
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#define UART_MEM_TX_STATUS_S 0
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#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60)
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#define UART_MEM_RX_STATUS_OFFSET 0x60
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#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + UART_MEM_RX_STATUS_OFFSET)
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/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */
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/* Description: */
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@ -1603,7 +1628,8 @@
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#define UART_MEM_RX_STATUS_V 0xFFFFFF
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#define UART_MEM_RX_STATUS_S 0
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#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
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#define UART_MEM_CNT_STATUS_OFFSET 0x64
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#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + UART_MEM_CNT_STATUS_OFFSET)
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/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */
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/* Description: refer to the txfifo_cnt's describtion.*/
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@ -1621,6 +1647,7 @@
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#define UART_RX_MEM_CNT_V 0x7
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#define UART_RX_MEM_CNT_S 0
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#define UART_POSPULSE_OFFSET 0x68
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#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68)
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/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
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@ -1633,7 +1660,8 @@
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#define UART_POSEDGE_MIN_CNT_V 0xFFFFF
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#define UART_POSEDGE_MIN_CNT_S 0
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#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c)
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#define UART_NEGPULSE_OFFSET 0x6c
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#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + UART_NEGPULSE_OFFSET)
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/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
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/* Description: This register stores the count of rxd negedge edge. it is
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@ -1645,6 +1673,7 @@
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#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF
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#define UART_NEGEDGE_MIN_CNT_S 0
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#define UART_DATE_OFFSET 0x78
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#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78)
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/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */
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@ -1655,7 +1684,8 @@
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#define UART_DATE_V 0xFFFFFFFF
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#define UART_DATE_S 0
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#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C)
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#define UART_ID_OFFSET 0x7c
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#define UART_ID_REG(i) (REG_UART_BASE(i) + UART_ID_OFFSET)
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/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */
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/* Description: */
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@ -161,6 +161,7 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr)
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uintptr_t regaddr;
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uint32_t func;
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uint32_t cntrl;
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unsigned int pinmode;
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DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO);
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@ -212,17 +213,18 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr)
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func |= FUN_IE;
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if ((attr & (INPUT | OUTPUT)) != 0)
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pinmode = (attr & PINMODE_MASK);
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if (pinmode == INPUT | pinmode == OUTPUT)
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{
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func |= (uint32_t)(2 << MCU_SEL_S);
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}
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else if (attr == SPECIAL)
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else if ((attr & FUNCTION_MASK) == SPECIAL)
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{
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func |= (uint32_t)((((pin) == 1 || (pin) == 3) ? 0 : 1) << MCU_SEL_S);
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}
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else
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else /* if ((attr & FUNCTION) != 0) */
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{
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func |= (uint32_t)((attr >> 5) << MCU_SEL_S);
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func |= (uint32_t)((attr >> FUNCTION_SHIFT) << MCU_SEL_S);
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}
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if ((attr & OPEN_DRAIN) != 0)
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@ -42,22 +42,46 @@
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/* Bit-encoded input to esp32_configgpio() **********************************/
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/* Encoded pin attributes used with esp32_configgpio() */
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/* Encoded pin attributes used with esp32_configgpio()
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*
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* 8 7 6 5 4 3 2 1 0
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* -- -- -- -- -- -- -- -- --
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* FN FN FN OD PD PU F O I
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*/
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#define INPUT 0x01
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#define OUTPUT 0x02
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#define PULLUP 0x04
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#define INPUT_PULLUP 0x05
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#define PULLDOWN 0x08
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#define INPUT_PULLDOWN 0x09
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#define OPEN_DRAIN 0x10
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#define OUTPUT_OPEN_DRAIN 0x12
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#define SPECIAL 0xf0
|
||||
#define FUNCTION_0 0x00
|
||||
#define FUNCTION_1 0x20
|
||||
#define FUNCTION_2 0x40
|
||||
#define FUNCTION_3 0x70
|
||||
#define FUNCTION_4 0x80
|
||||
#define PINMODE_SHIFT 0
|
||||
#define PINMODE_MASK (7 << PINMODE_SHIFT)
|
||||
# define INPUT (1 << 0)
|
||||
# define OUTPUT (1 << 1)
|
||||
# define FUNCTION (1 << 2)
|
||||
|
||||
#define PULLUP (1 << 3)
|
||||
#define PULLDOWN (1 << 4)
|
||||
#define OPEN_DRAIN (1 << 5)
|
||||
#define FUNCTION_SHIFT 6
|
||||
#define FUNCTION_MASK (7 << FUNCTION_SHIFT)
|
||||
# define FUNCTION_0 (0 << FUNCTION_SHIFT)
|
||||
# define FUNCTION_1 (1 << FUNCTION_SHIFT)
|
||||
# define FUNCTION_2 (2 << FUNCTION_SHIFT)
|
||||
# define FUNCTION_3 (3 << FUNCTION_SHIFT)
|
||||
# define FUNCTION_4 (4 << FUNCTION_SHIFT)
|
||||
# define SPECIAL (7 << FUNCTION_SHIFT)
|
||||
|
||||
#define INPUT_PULLUP (INPUT | PULLUP)
|
||||
#define INPUT_PULLDOWN (INPUT | PULLDOWN)
|
||||
#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN)
|
||||
#define INPUT_FUNCTION (INPUT | FUNCTION)
|
||||
# define INPUT_FUNCTION_0 (INPUT_FUNCTION | FUNCTION_0)
|
||||
# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1)
|
||||
# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2)
|
||||
# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3)
|
||||
# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4)
|
||||
#define OUTPUT_FUNCTION (OUTPUT | FUNCTION)
|
||||
# define OUTPUT_FUNCTION_0 (OUTPUT_FUNCTION | FUNCTION_0)
|
||||
# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1)
|
||||
# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2)
|
||||
# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3)
|
||||
# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4)
|
||||
|
||||
/* Interrupt type used with esp32_gpioirqenable() */
|
||||
|
||||
@ -78,7 +102,7 @@
|
||||
|
||||
/* Must be big enough to hold the the above encodings */
|
||||
|
||||
typedef uint8_t gpio_pinattr_t;
|
||||
typedef uint16_t gpio_pinattr_t;
|
||||
typedef uint8_t gpio_intrtype_t;
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
1212
arch/xtensa/src/esp32/esp32_serial.c
Normal file
1212
arch/xtensa/src/esp32/esp32_serial.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -38,6 +38,14 @@
|
||||
|
||||
#include "chip/gpio_reg.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
|
||||
#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT signal */
|
||||
#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user