From 6fef2aabd964f9857327397f6f505047b80993b5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 23 May 2015 17:02:13 -0600 Subject: [PATCH] SAML21: Add missing support for GCLK8 --- configs/saml21-xplained/include/board.h | 29 ++++++++++++++++--------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/configs/saml21-xplained/include/board.h b/configs/saml21-xplained/include/board.h index a721c7e327..3b2934be3b 100644 --- a/configs/saml21-xplained/include/board.h +++ b/configs/saml21-xplained/include/board.h @@ -166,7 +166,7 @@ * DFLL output frequency (Fdfll) is given by: * * Fdfll = DFLLmul * Frefclk - * = 6 * 8000000 = 48MHz + * = 12 * 4000000 = 48MHz * * Where the reference clock is Generic Clock Channel 0 output of GLCK1. * GCLCK1 provides OSC16M, undivided. @@ -224,7 +224,7 @@ #define BOARD_DFLL48M_MAXCOARSESTEP (0x1f / 4) #define BOARD_DFLL48M_MAXFINESTEP (0xff / 4) -#define BOARD_DFLL48M_FREQUENCY (48000000) +#define BOARD_DFLL48M_FREQUENCY (BOARD_DFLL48M_MULTIPLIER * BOARD_OSC16M_FREQUENCY) /* Fractional Digital Phase Locked Loop configuration. * @@ -248,18 +248,18 @@ #undef BOARD_FDPLL96M_ENABLE #undef BOARD_FDPLL96M_RUNINSTDBY -#define BOARD_FDPLL96M_ONDEMAND 1 +#define BOARD_FDPLL96M_ONDEMAND 1 #undef BOARD_FDPLL96M_LBYPASS #undef BOARD_FDPLL96M_WUF #undef BOARD_FDPLL96M_LPEN -#define BOARD_FDPLL96M_FILTER OSCCTRL_DPLLCTRLB_FILTER_DEFAULT -#define BOARD_FDPLL96M_REFCLK OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K -#define BOARD_FDPLL96M_REFCLK_CLKGEN 1 +#define BOARD_FDPLL96M_FILTER OSCCTRL_DPLLCTRLB_FILTER_DEFAULT +#define BOARD_FDPLL96M_REFCLK OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K +#define BOARD_FDPLL96M_REFCLK_CLKGEN 1 #undef BOARD_FDPLL96M_LOCKTIME_ENABLE -#define BOARD_FDPLL96M_LOCKTIME OSCCTRL_DPLLCTRLB_LTIME_NONE -#define BOARD_FDPLL96M_LOCKTIME_CLKGEN 1 -#define BOARD_FDPLL96M_REFDIV 1 -#define BOARD_FDPLL96M_PRESCALER OSCCTRL_DPLLPRESC_DIV1 +#define BOARD_FDPLL96M_LOCKTIME OSCCTRL_DPLLCTRLB_LTIME_NONE +#define BOARD_FDPLL96M_LOCKTIME_CLKGEN 1 +#define BOARD_FDPLL96M_REFDIV 1 +#define BOARD_FDPLL96M_PRESCALER OSCCTRL_DPLLPRESC_DIV1 #define BOARD_FDPLL96M_REFFREQ 32768 #define BOARD_FDPLL96M_FREQUENCY 48000000 @@ -353,6 +353,15 @@ #undef BOARD_GCLK7_OUTPUT_ENABLE #define BOARD_GCLK7_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK7_PRESCALER) +/* Configure GCLK generator 8 */ + +#undef BOARD_GCLK8_ENABLE +#undef BOARD_GCLK8_RUN_IN_STANDBY +#define BOARD_GCLK8_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M +#define BOARD_GCLK8_PRESCALER 1 +#undef BOARD_GCLK8_OUTPUT_ENABLE +#define BOARD_GCLK8_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK8_PRESCALER) + /* The source of the main clock is always GCLK_MAIN. Also called GCLKGEN[0], this is * the clock feeding the Power Manager. The Power Manager, in turn, generates main * clock which is divided down to produce the CPU, AHB, and APB clocks.