boards/arm/stm32[f7|l4]: fix SPI chip select GPIO access
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
This commit is contained in:
Petro Karashchenko
Xiang Xiao
parent
5ce181e6b7
commit
700e09103a
@ -85,33 +85,18 @@
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#define GPIO_SPI_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
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GPIO_OUTPUT_SET)
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#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15)
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#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
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#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
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#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
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#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
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#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
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#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
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#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
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#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
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#define GPIO_SPI3_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN5)
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#define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6)
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#define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7)
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/* Logical SPI Chip Selects used to index */
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#define NUCLEO_SPI_BUS1_CS0 0
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#define NUCLEO_SPI_BUS1_CS1 1
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#define NUCLEO_SPI_BUS1_CS2 2
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#define NUCLEO_SPI_BUS1_CS3 3
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#define NUCLEO_SPI_BUS2_CS0 4
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#define NUCLEO_SPI_BUS2_CS1 5
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#define NUCLEO_SPI_BUS2_CS2 6
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#define NUCLEO_SPI_BUS2_CS3 7
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#define NUCLEO_SPI_BUS3_CS0 8
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#define NUCLEO_SPI_BUS3_CS1 9
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#define NUCLEO_SPI_BUS3_CS2 10
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#define NUCLEO_SPI_BUS3_CS3 11
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#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15)
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#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
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#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
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#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
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#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
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#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
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#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
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#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
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#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
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#define GPIO_SPI3_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN5)
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#define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6)
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#define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7)
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#if defined(CONFIG_STM32F4_SDMMC1) || defined(CONFIG_STM32F4_SDMMC2)
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# define HAVE_SDIO
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@ -93,47 +93,83 @@
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* Private Data
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****************************************************************************/
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/* Indexed by NUCLEO_SPI_BUSx_CSx */
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static const uint32_t g_spigpio[] =
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#if defined(CONFIG_STM32F4_SPI1)
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static const uint32_t g_spi1gpio[] =
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{
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#if defined(GPIO_SPI1_CS0)
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GPIO_SPI1_CS0,
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GPIO_SPI1_CS0,
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#else
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0,
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#endif
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#if defined(GPIO_SPI1_CS1)
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GPIO_SPI1_CS1,
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GPIO_SPI1_CS1,
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#else
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0,
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#endif
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#if defined(GPIO_SPI1_CS2)
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GPIO_SPI1_CS2,
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GPIO_SPI1_CS2,
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#else
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0,
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#endif
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#if defined(GPIO_SPI1_CS3)
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GPIO_SPI1_CS3,
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#endif
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#if defined(GPIO_SPI2_CS0)
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GPIO_SPI2_CS0,
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#endif
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#if defined(GPIO_SPI2_CS1)
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GPIO_SPI2_CS1,
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#endif
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#if defined(GPIO_SPI2_CS2)
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GPIO_SPI2_CS2,
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#endif
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#if defined(GPIO_SPI2_CS3)
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GPIO_SPI2_CS3,
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#endif
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#if defined(GPIO_SPI3_CS0)
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GPIO_SPI3_CS0,
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#endif
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#if defined(GPIO_SPI3_CS1)
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GPIO_SPI3_CS1,
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#endif
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#if defined(GPIO_SPI3_CS2)
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GPIO_SPI3_CS2,
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#endif
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#if defined(GPIO_SPI3_CS3)
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GPIO_SPI3_CS3,
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GPIO_SPI1_CS3
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#else
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0
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#endif
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};
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#endif
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#if defined(CONFIG_STM32F4_SPI2)
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static const uint32_t g_spi2gpio[] =
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{
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#if defined(GPIO_SPI2_CS0)
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GPIO_SPI2_CS0,
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#else
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0,
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#endif
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#if defined(GPIO_SPI2_CS1)
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GPIO_SPI2_CS1,
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#else
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0,
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#endif
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#if defined(GPIO_SPI2_CS2)
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GPIO_SPI2_CS2,
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#else
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0,
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#endif
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#if defined(GPIO_SPI2_CS3)
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GPIO_SPI2_CS3
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#else
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0
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#endif
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};
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#endif
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#if defined(CONFIG_STM32F4_SPI3)
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static const uint32_t g_spi3gpio[] =
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{
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#if defined(GPIO_SPI3_CS0)
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GPIO_SPI3_CS0,
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#else
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0,
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#endif
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#if defined(GPIO_SPI3_CS1)
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GPIO_SPI3_CS1,
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#else
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0,
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#endif
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#if defined(GPIO_SPI3_CS2)
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GPIO_SPI3_CS2,
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#else
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0,
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#endif
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#if defined(GPIO_SPI3_CS3)
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GPIO_SPI3_CS3
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#else
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0
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#endif
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};
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#endif
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#if defined(CONFIG_NUCLEO_SPI_TEST)
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# if defined(CONFIG_STM32F4_SPI1)
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@ -161,22 +197,45 @@ struct spi_dev_s *spi3;
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void weak_function stm32_spidev_initialize(void)
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{
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int i;
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/* Configure SPI CS GPIO for output */
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for (i = 0; i < ARRAYSIZE(g_spigpio); i++)
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#if defined(CONFIG_STM32F4_SPI1)
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for (int i = 0; i < ARRAYSIZE(g_spi1gpio); i++)
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{
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stm32_configgpio(g_spigpio[i]);
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if (g_spi1gpio[i] != 0)
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{
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stm32_configgpio(g_spi1gpio[i]);
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}
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}
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#endif
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#if defined(CONFIG_STM32F4_SPI2)
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for (int i = 0; i < ARRAYSIZE(g_spi2gpio); i++)
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{
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if (g_spi2gpio[i] != 0)
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{
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stm32_configgpio(g_spi2gpio[i]);
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}
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}
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#endif
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#if defined(CONFIG_STM32F4_SPI3)
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for (int i = 0; i < ARRAYSIZE(g_spi3gpio); i++)
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{
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if (g_spi3gpio[i] != 0)
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{
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stm32_configgpio(g_spi3gpio[i]);
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}
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}
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#endif
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}
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/****************************************************************************
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* Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status
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* Name: stm32_spi1/2/3/4/5/6select and stm32_spi1/2/3/4/5/6status
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*
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* Description:
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* The external functions, stm32_spi1/2/3select and
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* stm32_spi1/2/3status must be provided by board-specific logic.
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* The external functions, stm32_spi1/2/3/4/5/6select and
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* stm32_spi1/2/3/4/5/6status must be provided by board-specific logic.
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* They are implementations of the select and status methods of
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* the SPI interface defined by struct spi_ops_s
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* (see include/nuttx/spi/spi.h). All other methods
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@ -185,7 +244,7 @@ void weak_function stm32_spidev_initialize(void)
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*
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* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
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* pins.
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* 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status()
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* 2. Provide stm32_spi1/2/3/4/5/6select() and stm32_spi1/2/3/4/5/6status()
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* functions in your board-specific logic. These functions will
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* perform chip selection and status operations using GPIOs in
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* the way your board is configured.
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@ -200,13 +259,17 @@ void weak_function stm32_spidev_initialize(void)
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#ifdef CONFIG_STM32F4_SPI1
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void stm32_spi1select(FAR struct spi_dev_s *dev,
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uint32_t devid,
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bool selected)
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uint32_t devid, bool selected)
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{
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spiinfo("devid: %d CS: %s\n",
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(int)devid, selected ? "assert" : "de-assert");
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uint32_t index = SPIDEVID_INDEX(devid);
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stm32_gpiowrite(g_spigpio[devid], !selected);
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spiinfo("devid: %d CS: %s\n",
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(int)devid, selected ? "assert" : "de-assert");
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if (g_spi1gpio[index] != 0)
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{
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stm32_gpiowrite(g_spi1gpio[index], !selected);
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}
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}
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uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
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@ -217,17 +280,20 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
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#ifdef CONFIG_STM32F4_SPI2
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void stm32_spi2select(FAR struct spi_dev_s *dev,
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uint32_t devid,
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bool selected)
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uint32_t devid, bool selected)
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{
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spiinfo("devid: %d CS: %s\n",
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(int)devid, selected ? "assert" : "de-assert");
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uint32_t index = SPIDEVID_INDEX(devid);
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stm32_gpiowrite(g_spigpio[devid], !selected);
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spiinfo("devid: %d CS: %s\n",
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(int)devid, selected ? "assert" : "de-assert");
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if (g_spi2gpio[index] != 0)
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{
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stm32_gpiowrite(g_spi2gpio[index], !selected);
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}
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}
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uint8_t stm32_spi2status(FAR struct spi_dev_s *dev,
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uint32_t devid)
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uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
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{
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return 0;
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}
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@ -235,34 +301,31 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev,
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#ifdef CONFIG_STM32F4_SPI3
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void stm32_spi3select(FAR struct spi_dev_s *dev,
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uint32_t devid,
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bool selected)
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uint32_t devid, bool selected)
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{
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spiinfo("devid: %d CS: %s\n",
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(int)devid, selected ? "assert" : "de-assert");
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uint32_t index = SPIDEVID_INDEX(devid);
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stm32_gpiowrite(g_spigpio[devid], !selected);
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spiinfo("devid: %d CS: %s\n",
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(int)devid, selected ? "assert" : "de-assert");
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if (g_spi3gpio[index] != 0)
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{
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stm32_gpiowrite(g_spi3gpio[index], !selected);
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}
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}
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uint8_t stm32_spi3status(FAR struct spi_dev_s *dev,
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uint32_t devid)
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uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_STM32F4_SPI4
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# ifndef NUCLEO_SPI_BUS4_CS0
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# error "NUCLEO_SPI_BUS4_CSn Are not defined"
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# endif
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void stm32_spi4select(FAR struct spi_dev_s *dev,
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uint32_t devid,
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bool selected)
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uint32_t devid, bool selected)
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{
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spiinfo("devid: %d CS: %s\n",
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(int)devid, selected ? "assert" : "de-assert");
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stm32_gpiowrite(g_spigpio[devid], !selected);
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(int)devid, selected ? "assert" : "de-assert");
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}
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uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid)
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@ -272,18 +335,11 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid)
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#endif
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#ifdef CONFIG_STM32F4_SPI5
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# ifndef NUCLEO_SPI_BUS5_CS0
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# error "NUCLEO_SPI_BUS4_CSn Are not defined"
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# endif
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void stm32_spi5select(FAR struct spi_dev_s *dev,
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uint32_t devid,
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bool selected)
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uint32_t devid, bool selected)
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{
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spiinfo("devid: %d CS: %s\n",
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(int)devid, selected ? "assert" : "de-assert");
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stm32_gpiowrite(g_spigpio[devid], !selected);
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(int)devid, selected ? "assert" : "de-assert");
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}
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uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid)
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@ -293,27 +349,21 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid)
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#endif
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#ifdef CONFIG_STM32F4_SPI6
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# ifndef NUCLEO_SPI_BUS6_CS
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# error "NUCLEO_SPI_BUS4_CSn Are not defined"
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# endif
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void stm32_spi5select(FAR struct spi_dev_s *dev,
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uint32_t devid,
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bool selected)
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void stm32_spi6select(FAR struct spi_dev_s *dev,
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uint32_t devid, bool selected)
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{
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spiinfo("devid: %d CS: %s\n",
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(int)devid, selected ? "assert" : "de-assert");
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stm32_gpiowrite(g_spigpio[devid], !selected);
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(int)devid, selected ? "assert" : "de-assert");
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}
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uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid)
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uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, uint32_t devid)
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{
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return 0;
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}
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#endif
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/****************************************************************************
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* Name: stm32_spi1cmddata
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* Name: stm32_spi1/2/3/4/5/6cmddata
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*
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* Description:
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* Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
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@ -372,7 +422,7 @@ int stm32_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
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#endif
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#ifdef CONFIG_STM32F4_SPI6
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int stm32_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
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int stm32_spi6cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
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{
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return -ENODEV;
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}
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@ -85,33 +85,18 @@
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#define GPIO_SPI_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
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GPIO_OUTPUT_SET)
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#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15)
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#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
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#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
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#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
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#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
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#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
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#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
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#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
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#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
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#define GPIO_SPI3_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN5)
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#define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6)
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#define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7)
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/* Logical SPI Chip Selects used to index */
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#define NUCLEO_SPI_BUS1_CS0 0
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#define NUCLEO_SPI_BUS1_CS1 1
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#define NUCLEO_SPI_BUS1_CS2 2
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#define NUCLEO_SPI_BUS1_CS3 3
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#define NUCLEO_SPI_BUS2_CS0 4
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#define NUCLEO_SPI_BUS2_CS1 5
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#define NUCLEO_SPI_BUS2_CS2 6
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#define NUCLEO_SPI_BUS2_CS3 7
|
||||
#define NUCLEO_SPI_BUS3_CS0 8
|
||||
#define NUCLEO_SPI_BUS3_CS1 9
|
||||
#define NUCLEO_SPI_BUS3_CS2 10
|
||||
#define NUCLEO_SPI_BUS3_CS3 11
|
||||
#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15)
|
||||
#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
|
||||
#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
|
||||
#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
|
||||
#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
|
||||
#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
|
||||
#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
|
||||
#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
|
||||
#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
|
||||
#define GPIO_SPI3_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN5)
|
||||
#define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6)
|
||||
#define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7)
|
||||
|
||||
#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2)
|
||||
# define HAVE_SDIO
|
||||
|
||||
@ -93,47 +93,83 @@
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* Indexed by NUCLEO_SPI_BUSx_CSx */
|
||||
|
||||
static const uint32_t g_spigpio[] =
|
||||
#if defined(CONFIG_STM32F7_SPI1)
|
||||
static const uint32_t g_spi1gpio[] =
|
||||
{
|
||||
#if defined(GPIO_SPI1_CS0)
|
||||
GPIO_SPI1_CS0,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI1_CS1)
|
||||
GPIO_SPI1_CS1,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI1_CS2)
|
||||
GPIO_SPI1_CS2,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI1_CS3)
|
||||
GPIO_SPI1_CS3,
|
||||
GPIO_SPI1_CS3
|
||||
#else
|
||||
0
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_SPI2)
|
||||
static const uint32_t g_spi2gpio[] =
|
||||
{
|
||||
#if defined(GPIO_SPI2_CS0)
|
||||
GPIO_SPI2_CS0,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI2_CS1)
|
||||
GPIO_SPI2_CS1,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI2_CS2)
|
||||
GPIO_SPI2_CS2,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI2_CS3)
|
||||
GPIO_SPI2_CS3,
|
||||
GPIO_SPI2_CS3
|
||||
#else
|
||||
0
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_SPI3)
|
||||
static const uint32_t g_spi3gpio[] =
|
||||
{
|
||||
#if defined(GPIO_SPI3_CS0)
|
||||
GPIO_SPI3_CS0,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI3_CS1)
|
||||
GPIO_SPI3_CS1,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI3_CS2)
|
||||
GPIO_SPI3_CS2,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI3_CS3)
|
||||
GPIO_SPI3_CS3,
|
||||
GPIO_SPI3_CS3
|
||||
#else
|
||||
0
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_SPI_TEST)
|
||||
# if defined(CONFIG_STM32F7_SPI1)
|
||||
@ -161,34 +197,57 @@ struct spi_dev_s *spi3;
|
||||
|
||||
void weak_function stm32_spidev_initialize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure SPI CS GPIO for output */
|
||||
|
||||
for (i = 0; i < ARRAYSIZE(g_spigpio); i++)
|
||||
#if defined(CONFIG_STM32F7_SPI1)
|
||||
for (int i = 0; i < ARRAYSIZE(g_spi1gpio); i++)
|
||||
{
|
||||
stm32_configgpio(g_spigpio[i]);
|
||||
if (g_spi1gpio[i] != 0)
|
||||
{
|
||||
stm32_configgpio(g_spi1gpio[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_SPI2)
|
||||
for (int i = 0; i < ARRAYSIZE(g_spi2gpio); i++)
|
||||
{
|
||||
if (g_spi2gpio[i] != 0)
|
||||
{
|
||||
stm32_configgpio(g_spi2gpio[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_SPI3)
|
||||
for (int i = 0; i < ARRAYSIZE(g_spi3gpio); i++)
|
||||
{
|
||||
if (g_spi3gpio[i] != 0)
|
||||
{
|
||||
stm32_configgpio(g_spi3gpio[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status
|
||||
* Name: stm32_spi1/2/3/4/5/6select and stm32_spi1/2/3/4/5/6status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status
|
||||
* must be provided by board-specific logic. They are implementations of
|
||||
* the select and status methods of the SPI interface defined by struct
|
||||
* spi_ops_s (see include/nuttx/spi/spi.h). All other methods
|
||||
* (including stm32_spibus_initialize())
|
||||
* The external functions, stm32_spi1/2/3/4/5/6select and
|
||||
* stm32_spi1/2/3/4/5/6status must be provided by board-specific logic.
|
||||
* They are implementations of the select and status methods of the SPI
|
||||
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
|
||||
* All other methods (including stm32_spibus_initialize())
|
||||
* are provided by common STM32 logic. To use this common SPI logic on
|
||||
* your board:
|
||||
*
|
||||
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions
|
||||
* in your board-specific logic. These functions will perform chip
|
||||
* selection and status operations using GPIOs in the way your board is
|
||||
* configured.
|
||||
* 2. Provide stm32_spi1/2/3/4/5/6select() and stm32_spi1/2/3/4/5/6status()
|
||||
* functions in your board-specific logic. These functions will perform
|
||||
* chip selection and status operations using GPIOs in the way your
|
||||
* board is configured.
|
||||
* 3. Add a calls to stm32_spibus_initialize() in your low level
|
||||
* application initialization logic
|
||||
* 4. The handle returned by stm32_spibus_initialize() may then be used to
|
||||
@ -202,9 +261,15 @@ void weak_function stm32_spidev_initialize(void)
|
||||
void stm32_spi1select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid, bool selected)
|
||||
{
|
||||
uint32_t index = SPIDEVID_INDEX(devid);
|
||||
|
||||
spiinfo("devid: %d CS: %s\n",
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
stm32_gpiowrite(g_spigpio[devid], !selected);
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
|
||||
if (g_spi1gpio[index] != 0)
|
||||
{
|
||||
stm32_gpiowrite(g_spi1gpio[index], !selected);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
@ -217,9 +282,15 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
void stm32_spi2select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid, bool selected)
|
||||
{
|
||||
uint32_t index = SPIDEVID_INDEX(devid);
|
||||
|
||||
spiinfo("devid: %d CS: %s\n",
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
stm32_gpiowrite(g_spigpio[devid], !selected);
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
|
||||
if (g_spi2gpio[index] != 0)
|
||||
{
|
||||
stm32_gpiowrite(g_spi2gpio[index], !selected);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
@ -232,9 +303,15 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
void stm32_spi3select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid, bool selected)
|
||||
{
|
||||
uint32_t index = SPIDEVID_INDEX(devid);
|
||||
|
||||
spiinfo("devid: %d CS: %s\n",
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
stm32_gpiowrite(g_spigpio[devid], !selected);
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
|
||||
if (g_spi3gpio[index] != 0)
|
||||
{
|
||||
stm32_gpiowrite(g_spi3gpio[index], !selected);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
@ -244,16 +321,11 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI4
|
||||
# ifndef NUCLEO_SPI_BUS4_CS0
|
||||
# error "NUCLEO_SPI_BUS4_CSn Are not defined"
|
||||
# endif
|
||||
|
||||
void stm32_spi4select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid, bool selected)
|
||||
{
|
||||
spiinfo("devid: %d CS: %s\n",
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
stm32_gpiowrite(g_spigpio[devid], !selected);
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
}
|
||||
|
||||
uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
@ -263,16 +335,11 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI5
|
||||
# ifndef NUCLEO_SPI_BUS5_CS0
|
||||
# error "NUCLEO_SPI_BUS4_CSn Are not defined"
|
||||
# endif
|
||||
|
||||
void stm32_spi5select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid, bool selected)
|
||||
{
|
||||
spiinfo("devid: %d CS: %s\n",
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
stm32_gpiowrite(g_spigpio[devid], !selected);
|
||||
}
|
||||
|
||||
uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
@ -282,25 +349,21 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI6
|
||||
# ifndef NUCLEO_SPI_BUS6_CS
|
||||
# error "NUCLEO_SPI_BUS4_CSn Are not defined"
|
||||
# endif
|
||||
void stm32_spi5select(FAR struct spi_dev_s *dev,
|
||||
void stm32_spi6select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid, bool selected)
|
||||
{
|
||||
spiinfo("devid: %d CS: %s\n",
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
stm32_gpiowrite(g_spigpio[devid], !selected);
|
||||
}
|
||||
|
||||
uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_spi1cmddata
|
||||
* Name: stm32_spi1/2/3/4/5/6cmddata
|
||||
*
|
||||
* Description:
|
||||
* Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
|
||||
@ -359,7 +422,7 @@ int stm32_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI6
|
||||
int stm32_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
||||
int stm32_spi6cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
@ -88,33 +88,18 @@
|
||||
#define GPIO_SPI_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
|
||||
GPIO_OUTPUT_SET)
|
||||
|
||||
#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN14)
|
||||
#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
|
||||
#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
|
||||
#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
|
||||
#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
|
||||
#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
|
||||
#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
|
||||
#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
|
||||
#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
|
||||
#define GPIO_SPI3_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN5)
|
||||
#define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6)
|
||||
#define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7)
|
||||
|
||||
/* Logical SPI Chip Selects used to index */
|
||||
|
||||
#define NUCLEO_SPI_BUS1_CS0 0
|
||||
#define NUCLEO_SPI_BUS1_CS1 1
|
||||
#define NUCLEO_SPI_BUS1_CS2 2
|
||||
#define NUCLEO_SPI_BUS1_CS3 3
|
||||
#define NUCLEO_SPI_BUS2_CS0 4
|
||||
#define NUCLEO_SPI_BUS2_CS1 5
|
||||
#define NUCLEO_SPI_BUS2_CS2 6
|
||||
#define NUCLEO_SPI_BUS2_CS3 7
|
||||
#define NUCLEO_SPI_BUS3_CS0 8
|
||||
#define NUCLEO_SPI_BUS3_CS1 9
|
||||
#define NUCLEO_SPI_BUS3_CS2 10
|
||||
#define NUCLEO_SPI_BUS3_CS3 11
|
||||
#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN14)
|
||||
#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15)
|
||||
#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14)
|
||||
#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN2)
|
||||
#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7)
|
||||
#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN1)
|
||||
#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2)
|
||||
#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3)
|
||||
#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4)
|
||||
#define GPIO_SPI3_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN5)
|
||||
#define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6)
|
||||
#define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7)
|
||||
|
||||
#if defined(CONFIG_STM32L4_SDMMC1) || defined(CONFIG_STM32L4_SDMMC2)
|
||||
# define HAVE_SDIO
|
||||
|
||||
@ -93,47 +93,83 @@
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* Indexed by NUCLEO_SPI_BUSx_CSx */
|
||||
|
||||
static const uint32_t g_spigpio[] =
|
||||
#if defined(CONFIG_STM32L4_SPI1)
|
||||
static const uint32_t g_spi1gpio[] =
|
||||
{
|
||||
#if defined(GPIO_SPI1_CS0)
|
||||
GPIO_SPI1_CS0,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI1_CS1)
|
||||
GPIO_SPI1_CS1,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI1_CS2)
|
||||
GPIO_SPI1_CS2,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI1_CS3)
|
||||
GPIO_SPI1_CS3,
|
||||
GPIO_SPI1_CS3
|
||||
#else
|
||||
0
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_SPI2)
|
||||
static const uint32_t g_spi2gpio[] =
|
||||
{
|
||||
#if defined(GPIO_SPI2_CS0)
|
||||
GPIO_SPI2_CS0,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI2_CS1)
|
||||
GPIO_SPI2_CS1,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI2_CS2)
|
||||
GPIO_SPI2_CS2,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI2_CS3)
|
||||
GPIO_SPI2_CS3,
|
||||
GPIO_SPI2_CS3
|
||||
#else
|
||||
0
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_SPI3)
|
||||
static const uint32_t g_spi3gpio[] =
|
||||
{
|
||||
#if defined(GPIO_SPI3_CS0)
|
||||
GPIO_SPI3_CS0,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI3_CS1)
|
||||
GPIO_SPI3_CS1,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI3_CS2)
|
||||
GPIO_SPI3_CS2,
|
||||
#else
|
||||
0,
|
||||
#endif
|
||||
#if defined(GPIO_SPI3_CS3)
|
||||
GPIO_SPI3_CS3,
|
||||
GPIO_SPI3_CS3
|
||||
#else
|
||||
0
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_SPI_TEST)
|
||||
# if defined(CONFIG_STM32L4_SPI1)
|
||||
@ -161,18 +197,41 @@ struct spi_dev_s *spi3;
|
||||
|
||||
void weak_function stm32_spidev_initialize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure SPI CS GPIO for output */
|
||||
|
||||
for (i = 0; i < ARRAYSIZE(g_spigpio); i++)
|
||||
#if defined(CONFIG_STM32L4_SPI1)
|
||||
for (int i = 0; i < ARRAYSIZE(g_spi1gpio); i++)
|
||||
{
|
||||
stm32l4_configgpio(g_spigpio[i]);
|
||||
if (g_spi1gpio[i] != 0)
|
||||
{
|
||||
stm32l4_configgpio(g_spi1gpio[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_SPI2)
|
||||
for (int i = 0; i < ARRAYSIZE(g_spi2gpio); i++)
|
||||
{
|
||||
if (g_spi2gpio[i] != 0)
|
||||
{
|
||||
stm32l4_configgpio(g_spi2gpio[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_SPI3)
|
||||
for (int i = 0; i < ARRAYSIZE(g_spi3gpio); i++)
|
||||
{
|
||||
if (g_spi3gpio[i] != 0)
|
||||
{
|
||||
stm32l4_configgpio(g_spi3gpio[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status
|
||||
* Name: stm32_spi1/2/3select and stm32_spi1/2/3status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status
|
||||
@ -201,9 +260,15 @@ void weak_function stm32_spidev_initialize(void)
|
||||
void stm32_spi1select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid, bool selected)
|
||||
{
|
||||
uint32_t index = SPIDEVID_INDEX(devid);
|
||||
|
||||
spiinfo("devid: %d CS: %s\n",
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
stm32l4_gpiowrite(g_spigpio[devid], !selected);
|
||||
|
||||
if (g_spi1gpio[index] != 0)
|
||||
{
|
||||
stm32l4_gpiowrite(g_spi1gpio[index], !selected);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
@ -216,9 +281,15 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
void stm32_spi2select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid, bool selected)
|
||||
{
|
||||
uint32_t index = SPIDEVID_INDEX(devid);
|
||||
|
||||
spiinfo("devid: %d CS: %s\n",
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
stm32l4_gpiowrite(g_spigpio[devid], !selected);
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
|
||||
if (g_spi2gpio[index] != 0)
|
||||
{
|
||||
stm32l4_gpiowrite(g_spi2gpio[index], !selected);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
@ -231,9 +302,15 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
void stm32_spi3select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid, bool selected)
|
||||
{
|
||||
uint32_t index = SPIDEVID_INDEX(devid);
|
||||
|
||||
spiinfo("devid: %d CS: %s\n",
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
stm32l4_gpiowrite(g_spigpio[devid], !selected);
|
||||
(int)devid, selected ? "assert" : "de-assert");
|
||||
|
||||
if (g_spi3gpio[index] != 0)
|
||||
{
|
||||
stm32l4_gpiowrite(g_spi3gpio[index], !selected);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
@ -243,7 +320,7 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_spi1cmddata
|
||||
* Name: stm32_spi1/2/3cmddata
|
||||
*
|
||||
* Description:
|
||||
* Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user