arch/mips/src/pic32mz/pic32mz-head.S: Add showprogress macro
This commit is contained in:
Ouss4
Gregory Nutt
parent
300fe5e354
commit
701b6897d7
@ -81,25 +81,27 @@
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*
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* 5) Idle thread stack:
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* Start: _ebss
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* End(+1): _ebss+CONFIG_IDLETHREAD_STACKSIZE
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* End(+1): _ebss + CONFIG_IDLETHREAD_STACKSIZE
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* 6) Optional interrupt stack
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* Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE
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* End(+1): _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
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* Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE
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* End(+1): _ebss + CONFIG_IDLETHREAD_STACKSIZE +
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(CONFIG_ARCH_INTERRUPTSTACK & ~3)
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* 6a) Heap (without interrupt stack)
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* Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE
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* Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE
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* End(+1): to the end of memory
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* 6b) Heap (with interrupt stack)
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* Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
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* Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE +
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(CONFIG_ARCH_INTERRUPTSTACK & ~3)
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* End(+1): to the end of memory
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*/
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#define PIC32MZ_STACK_BASE _ebss
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#define PIC32MZ_STACK_TOP _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
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#define PIC32MZ_STACK_TOP _ebss + CONFIG_IDLETHREAD_STACKSIZE - 4
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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# define PIC32MZ_INTSTACK_BASE PIC32MZ_STACK_TOP
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# define PIC32MZ_INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~3)
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# define PIC32MZ_INTSTACK_TOP PIC32MZ_STACK_TOP+PIC32MZ_INTSTACK_SIZE
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# define PIC32MZ_INTSTACK_TOP PIC32MZ_STACK_TOP + PIC32MZ_INTSTACK_SIZE
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# define PIC32MZ_HEAP_BASE PIC32MZ_INTSTACK_TOP
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#else
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# define PIC32MZ_HEAP_BASE PIC32MZ_STACK_TOP
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@ -145,6 +147,28 @@
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# define PIC32MZ_INDEXSTORETAG_D 9
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#endif
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/****************************************************************************
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* Assembly Language Macros
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****************************************************************************/
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/****************************************************************************
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* Name: showprogress
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*
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* Description:
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* Print a character on the UART to show boot status. This macro will
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* modify t0 and a0.
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*
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****************************************************************************/
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.macro showprogress, code
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#ifdef CONFIG_DEBUG_FEATURES
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la t0, up_lowputc
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la a0, \code
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jalr ra, t0
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nop
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#endif
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.endm
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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@ -170,10 +194,16 @@
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.global nx_start
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.global pic32mz_exception
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.global pic32mz_decodeirq
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.global pic32mz_lowinit
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#ifdef CONFIG_PIC32MZ_NMIHANDLER
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.global pic32mz_donmi
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#endif
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#ifdef CONFIG_DEBUG_FEATURES
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.global pic32mz_consoleinit
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.global up_lowputc
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#endif
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/* This file contains 32-bit assembly code */
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.set nomips16
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@ -441,6 +471,12 @@ __start:
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mtc0 t3, PIC32MZ_CP0_SRSCTL /* Restore SRSCtl */
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ehb
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la t0, pic32mz_consoleinit
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jalr ra, t0
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nop
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showprogress 'A'
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#if defined (CONFIG_MIPS32_ICACHE) || defined (CONFIG_MIPS32_DCACHE)
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/* Initialize K0 Cache. The cache resets in an indeterminate state.
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* We need to clear the tags and invalidate any data.
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@ -456,7 +492,7 @@ __start:
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mtc0 zero, PIC32MZ_CP0_TAGLO
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ehb
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#ifdef CONFIG_MIPS32_ICACHE
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# ifdef CONFIG_MIPS32_ICACHE
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/* Init I-Cache (Copy content of TagLo) */
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li t0, PIC32MZ_KSEG0_IBASE
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@ -465,9 +501,9 @@ __start:
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addu t0, t0, PIC32MZ_ILINE_SIZE
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bne t0, t1, .icacheloop
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cache PIC32MZ_INDEXSTORETAG_I, -4(t0)
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#endif
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# endif
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#ifdef CONFIG_MIPS32_DCACHE
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# ifdef CONFIG_MIPS32_DCACHE
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/* Init D-Cache (Copy content of TagLo) */
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li t0, PIC32MZ_KSEG0_DBASE
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@ -476,12 +512,14 @@ __start:
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addu t0, t0, PIC32MZ_DLINE_SIZE
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bne t0, t1, .dcacheloop
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cache PIC32MZ_INDEXSTORETAG_D, -4(t0)
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#endif
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# endif
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/* Force memory synchronization */
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sync
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showprogress 'B'
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#endif /* CONFIG_MIPS32_ICACHE || CONFIG_MIPS32_DCACHE */
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/* Set the cache algorithm.
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@ -496,6 +534,8 @@ __start:
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ori t0, K0_CACHE_ALGORITHM
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mtc0 t0, PIC32MZ_CP0_CONFIG
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showprogress 'C'
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/* Clear uninitialized data sections */
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la t0, _sbss
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@ -514,6 +554,8 @@ __start:
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bltu t0, t1, .Lbssloop
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nop
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showprogress 'D'
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/* Copy initialized data from program flash to data memory */
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la t0, _data_loaddr
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@ -532,6 +574,8 @@ __start:
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bltu t1, t2, .Ldataloop
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nop
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showprogress 'E'
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/* If there are no RAM functions, skip the next two sections --
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* copying RAM functions from program flash to data memory and
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* initializing bus matrix registers.
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@ -570,6 +614,9 @@ __start:
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la t1, _bmxdupba_address
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la t2, PIC32MZ_BMX_DUPBA
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sw t1, 0(t2)
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showprogress 'F'
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.Lnoramfuncs:
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#endif
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@ -643,6 +690,9 @@ __start:
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or t0, t0, CP0_CONFIG3_ISAONEXC /* Specify microMIPS mode on exceptions */
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mtc0 t0, MIPS32_CP0_CONFIG3 /* Update CONFIG3 register */
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#endif
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showprogress 'G'
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showprogress '\n'
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/* Start NuttX. We do this via a thunk in the text section so that
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* a normal jump and link can be used, enabling the startup code
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