From 7035723aebd23c10aa9783b31f19909aa90131ae Mon Sep 17 00:00:00 2001 From: Jussi Kivilinna Date: Thu, 4 May 2017 07:09:19 -0600 Subject: [PATCH] STM32F7 serial: Allow configuring Rx DMA buffer size --- arch/arm/src/stm32f7/Kconfig | 12 ++++++++++++ arch/arm/src/stm32f7/stm32_serial.c | 25 ++++++++++++++++++++----- 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 95e931abc2..123277ba13 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1614,6 +1614,18 @@ config UART8_RXDMA ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +config STM32F7_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + default 32 + depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half this number of bytes. + + Value given here will be rounded up to next multiple of 32 bytes. + config SERIAL_DISABLE_REORDERING bool "Disable reordering of ttySx devices." depends on STM32F7_USART1 || STM32F7_USART2 || STM32F7_USART3 || STM32F7_UART4 || STM32F7_UART5 || STM32F7_USART6 || STM32F7_UART7 || STM32F7_UART8 diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index 5c2b8b74bc..ce6e7db9a7 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -159,15 +159,30 @@ /* The DMA buffer size when using RX DMA to emulate a FIFO. * - * When streaming data, the generic serial layer will be called - * every time the FIFO receives half this number of bytes. + * When streaming data, the generic serial layer will be called every time + * the FIFO receives half this number of bytes. * - * This buffer size should be an even multiple of the Cortex-M7 - * D-Cache line size so that it can be individually invalidated. + * This buffer size should be an even multiple of the Cortex-M7 D-Cache line + * size, ARMV7M_DCACHE_LINESIZE, so that it can be individually invalidated. + * + * Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE + * would be zero! */ +# if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0 +# undef ARMV7M_DCACHE_LINESIZE +# define ARMV7M_DCACHE_LINESIZE 32 +# endif + +# if !defined(CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# endif + # define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -# define RXDMA_BUFFER_SIZE ((32 + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \ + + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* DMA priority */