Incremental progress on STM32 MMCSD driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2245 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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d170816334
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7088acf110
@ -55,6 +55,25 @@
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* Pre-Processor Definitions
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****************************************************************************/
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/* Friendly CLKCR bit re-definitions ****************************************/
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#define SDIO_CLKCR_RISINGEDGE (0)
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#define SDIO_CLKCR_FALLINGEDGE SDIO_CLKCR_NEGEDGE
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/* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz */
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#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
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#define STM32_CLCKCR_INIT \
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(SDIO_INIT_CLKDIV|SDIO_CLKCR_RISINGEDGE|SDIO_CLKCR_WIDBUS_D1)
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/* HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz */
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#define SDIO_TRANSFER_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#define STM32_CLCKCR_TRANSFER \
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(SDIO_TRANSFER_CLKDIV|SDIO_CLKCR_RISINGEDGE|SDIO_CLKCR_WIDBUS_D1)
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#define STM32_CLKCR_WIDETRANSFER \
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(SDIO_TRANSFER_CLKDIV|SDIO_CLKCR_RISINGEDGE|SDIO_CLKCR_WIDBUS_D4)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -66,12 +85,20 @@ struct stm32_dev_s
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struct sdio_dev_s dev; /* Standard, base MMC/SD interface */
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/* STM32-specific extensions */
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ubyte type; /* Card type (see MMCSD_CARDTYPE_ definitions) */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Low-level helpers ********************************************************/
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static inline void stm32_setclkcr(uint32 clkcr);
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static inline void stm32_enableint(uint32 bitset);
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static inline void stm32_disableint(uint32 bitset);
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/* SDIO interface methods ***************************************************/
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/* Initialization/setup */
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@ -87,7 +114,7 @@ static int stm32_attach(FAR struct sdio_dev_s *dev);
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/* Command/Status/Data Transfer */
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static void stm32_sendcmd(FAR struct sdio_dev_s *dev, ubyte cmd,
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static void stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32 cmd,
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uint32 arg, FAR const ubyte *data);
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static int stm32_senddata(FAR struct sdio_dev_s *dev,
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FAR const ubyte *buffer);
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@ -175,6 +202,91 @@ struct stm32_dev_s g_mmcsd =
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Low-level Helpers
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_setclkcr
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*
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* Description:
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* Modify oft-changed bits in the CLKCR register. Only the following bit-
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* fields are changed:
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*
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* CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, and HWFC_EN
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*
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* Input Parameters:
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* clkcr - A new CLKCR setting for the above mentions bits (other bits
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* are ignored.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void stm32_setclkcr(uint32 clkcr)
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{
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uint32 regval = getreg32(STM32_SDIO_CLKCR);
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/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
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regval &= ~(SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS|
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SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN);
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/* Replace with user provided settings */
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clkcr &= (SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS|
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SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN);
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regval |= clkcr;
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putreg32(regval, STM32_SDIO_CLKCR);
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}
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/****************************************************************************
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* Name: stm32_enableint
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*
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* Description:
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* Enable SDIO interrupts
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*
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* Input Parameters:
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* bitset - The set of bits in the SDIO MASK register to set
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void stm32_enableint(uint32 bitset)
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{
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uint32 regval;
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regval = getreg32(STM32_SDIO_MASK);
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regval |= bitset;
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putreg32(regval, STM32_SDIO_MASK);
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}
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/****************************************************************************
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* Name: stm32_disableint
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*
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* Description:
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* Disable SDIO interrupts
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*
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* Input Parameters:
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* bitset - The set of bits in the SDIO MASK register to clear
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void stm32_disableint(uint32 bitset)
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{
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uint32 regval;
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regval = getreg32(STM32_SDIO_MASK);
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regval &= ~bitset;
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putreg32(regval, STM32_SDIO_MASK);
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}
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/****************************************************************************
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* SDIO Interface Methods
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_reset
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*
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@ -300,7 +412,7 @@ static int stm32_attach(FAR struct sdio_dev_s *dev)
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*
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* Input Parameters:
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* dev - An instance of the MMC/SD device interface
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* cmd - The command to send
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* cmd - The command to send (32-bits, encoded)
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* arg - 32-bit argument required with some commands
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* data - A reference to data required with some commands
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*
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@ -309,9 +421,53 @@ static int stm32_attach(FAR struct sdio_dev_s *dev)
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*
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****************************************************************************/
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static void stm32_sendcmd(FAR struct sdio_dev_s *dev, ubyte cmd,
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static void stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32 cmd,
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uint32 arg, FAR const ubyte *data)
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{
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uint32 regval;
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uint32 cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
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/* Set the SDIO Argument value */
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putreg32(arg, STM32_SDIO_ARG);
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/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
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regval = getreg32(STM32_SDIO_CMD);
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regval &= ~(SDIO_CMD_CMDINDEX_MASK|SDIO_CMD_WAITRESP_MASK|
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SDIO_CMD_WAITINT|SDIO_CMD_WAITPEND|SDIO_CMD_CPSMEN);
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/* Set WAITRESP bits */
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#warning VERIFY
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switch ((cmd & MMCSD_RESPONSE_MASK) >> MMCSD_RESPONSE_SHIFT)
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{
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case MMCSD_NO_RESPONSE:
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regval |= SDIO_CMD_NORESPONSE;
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break;
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case MMCSD_R1_RESPONSE:
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case MMCSD_R1B_RESPONSE:
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case MMCSD_R3_RESPONSE:
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case MMCSD_R4_RESPONSE:
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case MMCSD_R5_RESPONSE:
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case MMCSD_R6_RESPONSE:
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case MMCSD_R7_RESPONSE:
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regval |= SDIO_CMD_SHORTRESPONSE;
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break;
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case MMCSD_R2_RESPONSE:
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regval |= SDIO_CMD_LONGRESPONSE;
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break;
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}
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/* Set CPSMEN and the command index */
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cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
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regval |= cmdidx | SDIO_CMD_CPSMEN;
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/* Write the SDIO CMD */
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putreg32(regval, STM32_SDIO_CMD);
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}
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/****************************************************************************
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@ -618,7 +774,17 @@ static int stm32_dmastop(FAR struct sdio_dev_s *dev)
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#ifdef CONFIG_SDIO_DMA
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static int stm32_dmastatus(FAR struct sdio_dev_s *dev, size_t *remaining)
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{
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return -ENOSYS;
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#ifdef CONFIG_DEBUG
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if (remaining)
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{
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*remaining = getreg32(STM32_SDIO_DCOUNT);
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return OK;
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}
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return -EINVAL;
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#else
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*remaining = getreg32(STM32_SDIO_DCOUNT);
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return OK;
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#endif
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}
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#endif
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@ -123,7 +123,7 @@
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#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT)
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#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */
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#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT)
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# define SDIO_CMD_NORESPONSE1 (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */
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# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */
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# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */
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# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */
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#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */
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@ -217,6 +217,7 @@
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#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */
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#define SDIO_ICR_RESET 0x00c007ff
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#define SDIO_ICR_STATICFLAGS 0x000005ff
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#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
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#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */
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