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xtensa/esp32: Add option to enable ETH PHY reset pin

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This commit is contained in:
Dong Heng 2022-12-30 14:57:47 +08:00 committed by Xiang Xiao
parent 96ec6983db
commit 7097cfd000
2 changed files with 13 additions and 1 deletions
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5
arch/xtensa/src/esp32/Kconfig
View File

@ -1860,10 +1860,15 @@ config ESP32_ETH_MDIOPIN
default 18
range 0 39
config ESP32_ETH_ENABLE_PHY_RSTPIN
bool "Enable Reset PHY Pin"
default y
config ESP32_ETH_PHY_RSTPIN
int "Reset PHY Pin"
default 5
range 0 39
depends on ESP32_ETH_ENABLE_PHY_RSTPIN
config ESP32_ETH_PHY_ADDR
int "PHY address"

7
arch/xtensa/src/esp32/esp32_emac.c
View File

@ -146,7 +146,9 @@
/* Reset PHY chip pins */
#ifdef CONFIG_ESP32_ETH_ENABLE_PHY_RSTPIN
# define EMAC_PHYRST_PIN (CONFIG_ESP32_ETH_PHY_RSTPIN)
#endif
/* PHY chip address in SMI bus */
@ -511,7 +513,9 @@ static void emac_init_gpio(void)
esp32_gpio_matrix_out(EMAC_MDIO_PIN, EMAC_MDO_O_IDX, 0, 0);
esp32_gpio_matrix_in(EMAC_MDIO_PIN, EMAC_MDI_I_IDX, 0);
#ifdef CONFIG_ESP32_ETH_ENABLE_PHY_RSTPIN
esp32_configgpio(EMAC_PHYRST_PIN, OUTPUT | PULLUP);
#endif
}
/****************************************************************************
@ -538,11 +542,14 @@ static int emac_config(void)
uint32_t regval;
uint8_t macaddr[6];
#ifdef CONFIG_ESP32_ETH_ENABLE_PHY_RSTPIN
/* Hardware reset PHY chip */
esp32_gpiowrite(EMAC_PHYRST_PIN, false);
nxsig_usleep(50);
esp32_gpiowrite(EMAC_PHYRST_PIN, true);
#endif
/* Open hardware clock */