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Fix problems when DMA2 is enabled

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2277 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2009-11-21 17:43:59 +00:00
parent d3ea3abde6
commit 70e2fd6f6c
5 changed files with 31 additions and 5 deletions
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2
ChangeLog
View File

@ -969,6 +969,8 @@
attempts to mount at the location to fail (reporting that the node
already exists). This is a probably for block drivers for removable
media: The bind method could fail repeatedly until media is asserted.
* arch/arm/src/stm32/chip.h & stm32_dma.c -- Fixed several definitions
that can cause compilation errors when DMA2 is enabled.

4
Documentation/NuttX.html
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@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: November 18, 2009</p>
<p>Last Updated: November 21, 2009</p>
</td>
</tr>
</table>
@ -1617,6 +1617,8 @@ nuttx-0.4.14 2009-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
attempts to mount at the location to fail (reporting that the node
already exists). This is a probably for block drivers for removable
media: The bind method could fail repeatedly until media is asserted.
* arch/arm/src/stm32/chip.h & stm32_dma.c -- Fixed several definitions
that can cause compilation errors when DMA2 is enabled.
pascal-0.1.3 2009-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;

3
arch/arm/src/stm32/chip.h
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@ -57,11 +57,12 @@
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */
# define STM32 NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 1 /* bxCAN1 */
# define STM32_NSDIO 1 /* 1 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NGPIO 112 /* GPIOA-G */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 0 /* No DAC */

12
arch/arm/src/stm32/stm32_dma.c
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@ -145,12 +145,20 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
},
{
.chan = STM32_DMA2_CHAN4,
#ifdef CONFIG_STM32_CONNECTIVITY_LINE
.irq = STM32_IRQ_DMA2CH4,
#else
.irq = STM32_IRQ_DMA2CH45,
#endif
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
},
{
.chan = STM32_DMA2_CHAN5,
#ifdef CONFIG_STM32_CONNECTIVITY_LINE
.irq = STM32_IRQ_DMA2CH5,
#else
.irq = STM32_IRQ_DMA2CH45,
#endif
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4),
},
#endif
@ -241,7 +249,11 @@ static int stm32_dmainterrupt(int irq, void *context)
}
else
#if STM32_NDMA > 1
#ifdef CONFIG_STM32_CONNECTIVITY_LINE
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
#else
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
#endif
{
chan = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
}

15
arch/arm/src/stm32/stm32_sdio.c
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@ -72,6 +72,10 @@
# undef CONFIG_SDIO_DMA
#endif
#ifndef CONFIG_SDIO_DMA
# warning "Large Non-DMA transfer may result in RX overrun failures"
#endif
#ifndef CONFIG_SCHED_WORKQUEUE
# error "Callback support requires CONFIG_SCHED_WORKQUEUE"
#endif
@ -941,13 +945,14 @@ static int stm32_interrupt(int irq, void *context)
stm32_endtransfer(priv, OK);
}
/* Handler data block send/receive CRC failure */
/* Handle data block send/receive CRC failure */
else if ((pending & SDIO_STA_DCRCFAIL) != 0)
{
/* Terminate the transfer with an error */
putreg32(SDIO_ICR_DCRCFAILC, STM32_SDIO_ICR);
flldbg("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, -EIO);
}
@ -958,6 +963,7 @@ static int stm32_interrupt(int irq, void *context)
/* Terminate the transfer with an error */
putreg32(SDIO_ICR_DTIMEOUTC, STM32_SDIO_ICR);
flldbg("ERROR: Data timeout, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, -ETIMEDOUT);
}
@ -968,6 +974,7 @@ static int stm32_interrupt(int irq, void *context)
/* Terminate the transfer with an error */
putreg32(SDIO_ICR_RXOVERRC, STM32_SDIO_ICR);
flldbg("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, -EOVERFLOW);
}
@ -978,6 +985,7 @@ static int stm32_interrupt(int irq, void *context)
/* Terminate the transfer with an error */
putreg32(SDIO_ICR_TXUNDERRC, STM32_SDIO_ICR);
flldbg("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, -EOVERFLOW);
}
@ -988,6 +996,7 @@ static int stm32_interrupt(int irq, void *context)
/* Terminate the transfer with an error */
putreg32(SDIO_ICR_STBITERRC, STM32_SDIO_ICR);
flldbg("ERROR: Start bit, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, -EIO);
}
}
@ -1297,12 +1306,12 @@ static void stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32 cmd, uint32 arg)
cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
regval |= cmdidx | SDIO_CMD_CPSMEN;
fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, getreg32(STM32_SDIO_CMD));
/* Write the SDIO CMD */
putreg32(SDIO_RESPDONE_ICR|SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
putreg32(regval, STM32_SDIO_CMD);
fvdbg("cmd: %08x arg: %08x regval: %08x\n",
cmd, arg, getreg32(STM32_SDIO_CMD));
}
/****************************************************************************