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stm32_f7/h7_eth: Added error handling for abnormal interrupts.

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This commit is contained in:
Fotis Panagiotopoulos 2023-04-25 01:00:19 +03:00 committed by Alin Jerpelea
parent 6d5f8caf53
commit 70e42f5bfe
2 changed files with 34 additions and 10 deletions
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22
arch/arm/src/stm32f7/stm32_ethernet.c
View File

@ -2117,16 +2117,13 @@ static void stm32_interrupt_work(void *arg)
stm32_putreg(ETH_DMAINT_NIS, STM32_ETH_DMASR); stm32_putreg(ETH_DMAINT_NIS, STM32_ETH_DMASR);
} }
/* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */
#ifdef CONFIG_DEBUG_NET
/* Check if there are pending "abnormal" interrupts */ /* Check if there are pending "abnormal" interrupts */
if ((dmasr & ETH_DMAINT_AIS) != 0) if ((dmasr & ETH_DMAINT_AIS) != 0)
{ {
/* Just let the user know what happened */ /* Just let the user know what happened */
nerr("ERROR: Abormal event(s): %08x\n", dmasr); nerr("ERROR: Abnormal event(s): %08" PRIx32 "\n", dmasr);
/* Clear all pending abnormal events */ /* Clear all pending abnormal events */
@ -2135,8 +2132,23 @@ static void stm32_interrupt_work(void *arg)
/* Clear the pending abnormal summary interrupt */ /* Clear the pending abnormal summary interrupt */
stm32_putreg(ETH_DMAINT_AIS, STM32_ETH_DMASR); stm32_putreg(ETH_DMAINT_AIS, STM32_ETH_DMASR);
/* As per the datasheet's recommendation, the MAC
* needs to be reset for all abnormal events. The
* scheduled job will take the interface down and
* up again.
*/
work_queue(ETHWORK, &priv->irqwork, stm32_txtimeout_work, priv, 0);
/* Interrupts need to remain disabled, no other
* processing will take place. After reset
* everything will be restored.
*/
net_unlock();
return;
} }
#endif
net_unlock(); net_unlock();

22
arch/arm/src/stm32h7/stm32_ethernet.c
View File

@ -2230,16 +2230,13 @@ static void stm32_interrupt_work(void *arg)
stm32_putreg(ETH_DMACSR_NIS, STM32_ETH_DMACSR); stm32_putreg(ETH_DMACSR_NIS, STM32_ETH_DMACSR);
} }
/* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */
#ifdef CONFIG_DEBUG_NET
/* Check if there are pending "abnormal" interrupts */ /* Check if there are pending "abnormal" interrupts */
if ((dmasr & ETH_DMACSR_AIS) != 0) if ((dmasr & ETH_DMACSR_AIS) != 0)
{ {
/* Just let the user know what happened */ /* Just let the user know what happened */
nerr("ERROR: Abormal event(s): %08x\n", dmasr); nerr("ERROR: Abnormal event(s): %08" PRIx32 "\n", dmasr);
/* Clear all pending abnormal events */ /* Clear all pending abnormal events */
@ -2248,8 +2245,23 @@ static void stm32_interrupt_work(void *arg)
/* Clear the pending abnormal summary interrupt */ /* Clear the pending abnormal summary interrupt */
stm32_putreg(ETH_DMACSR_AIS, STM32_ETH_DMACSR); stm32_putreg(ETH_DMACSR_AIS, STM32_ETH_DMACSR);
/* As per the datasheet's recommendation, the MAC
* needs to be reset for all abnormal events. The
* scheduled job will take the interface down and
* up again.
*/
work_queue(ETHWORK, &priv->irqwork, stm32_txtimeout_work, priv, 0);
/* Interrupts need to remain disabled, no other
* processing will take place. After reset
* everything will be restored.
*/
net_unlock();
return;
} }
#endif
net_unlock(); net_unlock();