Add suport for the Stellaris LM3S6432S2E and the TI RDK-S2E
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4260 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
686b63f5d0
commit
70f5f130b1
@ -116,6 +116,41 @@
|
||||
# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
|
||||
/* Vectors 60-70: Reserved */
|
||||
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
|
||||
# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
|
||||
# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */
|
||||
# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */
|
||||
# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
|
||||
# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
|
||||
/* Vector 25: Reserved */
|
||||
# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
|
||||
/* Vectors 27-29: Reserved */
|
||||
# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
|
||||
# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
|
||||
# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
|
||||
# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
|
||||
# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
|
||||
# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
|
||||
# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
|
||||
# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
|
||||
# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
|
||||
# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
|
||||
# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
|
||||
# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
|
||||
# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
|
||||
/* Vector 43: Reserved */
|
||||
# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */
|
||||
# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
|
||||
# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
|
||||
# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
|
||||
/* Vectors 48-57: Reserved */
|
||||
# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
|
||||
/* Vectors 59-70: Reserved */
|
||||
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
|
||||
@ -59,6 +59,17 @@
|
||||
# define LM2S_NPWM 0 /* No PWM generator modules */
|
||||
# define LM3S_NQEI 0 /* No quadrature encoders */
|
||||
# define LM3S_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
# define LM3S_NTIMERS 3 /* Three general purpose timers */
|
||||
# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
# undef LM3S_ETHTS /* No timestamp register */
|
||||
# define LM3S_NSSI 1 /* One SSI module */
|
||||
# define LM3S_NUARTS 2 /* Two UART modules */
|
||||
# define LM3S_NI2C 1 /* Two I2C modules */
|
||||
# define LM3S_NADC 1 /* One ADC module */
|
||||
# define LM2S_NPWM 1 /* One PWM generator module */
|
||||
# define LM3S_NQEI 0 /* No quadrature encoders */
|
||||
# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
# define LM3S_NTIMERS 4 /* Four general purpose timers */
|
||||
# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
|
||||
|
||||
@ -367,6 +367,10 @@ static void lm3s_ethreset(struct lm3s_driver_s *priv)
|
||||
putreg32(regval, LM3S_SYSCON_SRCR2);
|
||||
nllvdbg("SRCR2: %08x\n", regval);
|
||||
|
||||
/* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */
|
||||
|
||||
up_mdelay(2);
|
||||
|
||||
/* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */
|
||||
|
||||
#ifdef CONFIG_LM3S_ETHLEDS
|
||||
|
||||
@ -192,6 +192,36 @@
|
||||
# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
|
||||
# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
|
||||
# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
|
||||
# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
|
||||
# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */
|
||||
# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */
|
||||
# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */
|
||||
# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
|
||||
# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
|
||||
# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */
|
||||
# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */
|
||||
# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */
|
||||
# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */
|
||||
# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */
|
||||
# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
|
||||
# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
|
||||
# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */
|
||||
# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */
|
||||
# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */
|
||||
# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
|
||||
# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
|
||||
# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */
|
||||
# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
|
||||
# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */
|
||||
# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
|
||||
# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */
|
||||
# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
|
||||
# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */
|
||||
# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */
|
||||
# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
|
||||
# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
|
||||
# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
|
||||
|
||||
@ -48,7 +48,8 @@
|
||||
|
||||
/* Memory map ***********************************************************************/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \
|
||||
defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
|
||||
# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
|
||||
/* -0x1fffffff: Reserved */
|
||||
# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
|
||||
@ -140,6 +141,46 @@
|
||||
# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
/* FiRM Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
/* -0x1ffff: Reserved */
|
||||
/* Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
/* -0x27fff: Reserved */
|
||||
# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */
|
||||
# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
/* FiRM Peripheral Base Addresses */
|
||||
|
||||
|
||||
@ -183,6 +183,62 @@ lm3s_vectors:
|
||||
.word lm3s_reserved /* Vector 68: Reserved */
|
||||
.word lm3s_reserved /* Vector 69: Reserved */
|
||||
.word lm3s_reserved /* Vector 70: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
.word lm3s_gpioa /* Vector 16: GPIO Port A */
|
||||
.word lm3s_gpiob /* Vector 17: GPIO Port B */
|
||||
.word lm3s_gpioc /* Vector 18: GPIO Port C */
|
||||
.word lm3s_gpiod /* Vector 19: GPIO Port D */
|
||||
.word lm3s_gpioe /* Vector 20: GPIO Port E */
|
||||
.word lm3s_uart0 /* Vector 21: UART 0 */
|
||||
.word lm3s_uart1 /* Vector 22: UART 1 */
|
||||
.word lm3s_ssi0 /* Vector 23: SSI 0 */
|
||||
.word lm3s_i2c0 /* Vector 24: I2C 0 */
|
||||
.word lm3s_reserved /* Vector 25: Reserved */
|
||||
.word lm3s_pwm0 /* Vector 26: PWM Generator 0 */
|
||||
.word lm3s_reserved /* Vector 27: Reserved */
|
||||
.word lm3s_reserved /* Vector 28: Reserved */
|
||||
.word lm3s_reserved /* Vector 29: Reserved */
|
||||
.word lm3s_adc0 /* Vector 30: ADC Sequence 0 */
|
||||
.word lm3s_adc1 /* Vector 31: ADC Sequence 1 */
|
||||
.word lm3s_adc2 /* Vector 32: ADC Sequence 2 */
|
||||
.word lm3s_adc3 /* Vector 33: ADC Sequence 3 */
|
||||
.word lm3s_wdog /* Vector 34: Watchdog Timer */
|
||||
.word lm3s_tmr0a /* Vector 35: Timer 0 A */
|
||||
.word lm3s_tmr0b /* Vector 36: Timer 0 B */
|
||||
.word lm3s_tmr1a /* Vector 37: Timer 1 A */
|
||||
.word lm3s_tmr1b /* Vector 38: Timer 1 B */
|
||||
.word lm3s_tmr2a /* Vector 39: Timer 2 A */
|
||||
.word lm3s_tmr2b /* Vector 40: Timer 3 B */
|
||||
.word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */
|
||||
.word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */
|
||||
.word lm3s_reserved /* Vector 43: Reserved */
|
||||
.word lm3s_syscon /* Vector 44: System Control */
|
||||
.word lm3s_flashcon /* Vector 45: FLASH Control */
|
||||
.word lm3s_gpiof /* Vector 46: GPIO Port F */
|
||||
.word lm3s_gpiog /* Vector 47: GPIO Port G */
|
||||
.word lm3s_reserved /* Vector 48: Reserved */
|
||||
.word lm3s_reserved /* Vector 49: Reserved */
|
||||
.word lm3s_reserved /* Vector 50: Reserved */
|
||||
.word lm3s_reserved /* Vector 51: Reserved */
|
||||
.word lm3s_reserved /* Vector 52: Reserved */
|
||||
.word lm3s_reserved /* Vector 53: Reserved */
|
||||
.word lm3s_reserved /* Vector 54: Reserved */
|
||||
.word lm3s_reserved /* Vector 55: Reserved */
|
||||
.word lm3s_reserved /* Vector 56: Reserved */
|
||||
.word lm3s_reserved /* Vector 57: Reserved */
|
||||
.word lm3s_eth /* Vector 58: Ethernet Controller */
|
||||
.word lm3s_reserved /* Vector 59: Reserved */
|
||||
.word lm3s_reserved /* Vector 60: Reserved */
|
||||
.word lm3s_reserved /* Vector 61: Reserved */
|
||||
.word lm3s_reserved /* Vector 62: Reserved */
|
||||
.word lm3s_reserved /* Vector 63: Reserved */
|
||||
.word lm3s_reserved /* Vector 64: Reserved */
|
||||
.word lm3s_reserved /* Vector 65: Reserved */
|
||||
.word lm3s_reserved /* Vector 66: Reserved */
|
||||
.word lm3s_reserved /* Vector 67: Reserved */
|
||||
.word lm3s_reserved /* Vector 68: Reserved */
|
||||
.word lm3s_reserved /* Vector 69: Reserved */
|
||||
.word lm3s_reserved /* Vector 70: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
.word lm3s_gpioa /* Vector 16: GPIO Port A */
|
||||
.word lm3s_gpiob /* Vector 17: GPIO Port B */
|
||||
@ -410,6 +466,35 @@ handlers:
|
||||
HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user