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arch/arm/src/tiva:  Add CC13xx logic to enable power domains needed by peripherals and to enable clocking to peripherals.

    arch/arm/src/tiva:  Rename some header files so that they are unique in order to avoid including the wrong file.  Fix various compile issues found during some initial trial builds.

    arch/arm/src/tiva:  Add CC13xx clock enable and power enable macros that are backward compatible with lm/tm4c macros.
This commit is contained in:
Gregory Nutt 2018-12-09 07:02:15 -06:00
parent b9a1969122
commit 7113cef6b7
25 changed files with 1874 additions and 934 deletions
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14
arch/arm/include/tiva/cc13x0_irq.h
View File

@ -57,14 +57,14 @@
#define TIVA_IRQ_I2C (17) /* Interrupt event from I2C */
#define TIVA_IRQ_RFC_CPE_1 (18) /* Combined Interrupt for CPE
* Generated events */
#define TIVA_IRQ_AON_RTC_COMB (20) /* Event from AON_RTC */
#define TIVA_IRQ_UART0_COMB (21) /* UART0 combined interrupt */
#define TIVA_IRQ_AON_RTC (20) /* Event from AON_RTC */
#define TIVA_IRQ_UART0 (21) /* UART0 combined interrupt */
#define TIVA_IRQ_AUX_SWEV0 (22) /* AUX software event 0 */
#define TIVA_IRQ_SSI0_COMB (23) /* SSI0 combined interrupt */
#define TIVA_IRQ_SSI1_COMB (24) /* SSI1 combined interrupt */
#define TIVA_IRQ_SSI0 (23) /* SSI0 combined interrupt */
#define TIVA_IRQ_SSI1 (24) /* SSI1 combined interrupt */
#define TIVA_IRQ_RFC_CPE_0 (25) /* Combined Interrupt for CPE
* Generated events */
#define TIVA_IRQ_RFC_HW_COMB (26) /* Combined RFC hardware interrupt */
#define TIVA_IRQ_RFC_HW (26) /* Combined RFC hardware interrupt */
#define TIVA_IRQ_RFC_CMD_ACK (27) /* RFC Doorbell Command
* Acknowledgement Interrupt */
#define TIVA_IRQ_I2S (28) /* Interrupt event from I2S */
@ -80,11 +80,11 @@
#define TIVA_IRQ_GPT3B (38) /* GPT3B interrupt event */
#define TIVA_IRQ_CRYPTO_RESULT_AVAIL (39) /* CRYPTO result available interupt
* event */
#define TIVA_IRQ_DMA_DONE_COMB (40) /* Combined DMA done */
#define TIVA_IRQ_DMA_DONE (40) /* Combined DMA done */
#define TIVA_IRQ_DMA_ERR (41) /* DMA bus error */
#define TIVA_IRQ_FLASH (42) /* FLASH controller error event */
#define TIVA_IRQ_SWEV0 (43) /* Software event 0 */
#define TIVA_IRQ_AUX_COMB (44) /* AUX combined event */
#define TIVA_IRQ_AUX (44) /* AUX combined event */
#define TIVA_IRQ_AON_PROG0 (45) /* AON programmable event 0 */
#define TIVA_IRQ_PROG0 (46) /* Programmable Interrupt 0 */
#define TIVA_IRQ_AUX_COMPA (47) /* AUX Compare A event */

20
arch/arm/include/tiva/cc13x2_cc26x2_irq.h
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@ -58,14 +58,14 @@
#define TIVA_IRQ_RFC_CPE_1 (18) /* Combined Interrupt for CPE
* Generated events */
#define TIVA_IRQ_PKA (19) /* PKA Interrupt event */
#define TIVA_IRQ_AON_RTC_COMB (20) /* Event from AON_RTC */
#define TIVA_IRQ_UART0_COMB (21) /* UART0 combined interrupt */
#define TIVA_IRQ_AON_RTC (20) /* Event from AON_RTC */
#define TIVA_IRQ_UART0 (21) /* UART0 combined interrupt */
#define TIVA_IRQ_AUX_SWEV0 (22) /* AUX software event 0 */
#define TIVA_IRQ_SSI0_COMB (23) /* SSI0 combined interrupt */
#define TIVA_IRQ_SSI1_COMB (24) /* SSI1 combined interrupt */
#define TIVA_IRQ_SSI0 (23) /* SSI0 combined interrupt */
#define TIVA_IRQ_SSI1 (24) /* SSI1 combined interrupt */
#define TIVA_IRQ_RFC_CPE_0 (25) /* Combined Interrupt for CPE
* Generated events */
#define TIVA_IRQ_RFC_HW_COMB (26) /* Combined RFC hardware interrupt */
#define TIVA_IRQ_RFC_HW (26) /* Combined RFC hardware interrupt */
#define TIVA_IRQ_RFC_CMD_ACK (27) /* RFC Doorbell Command
* Acknowledgement Interrupt */
#define TIVA_IRQ_I2S (28) /* Interrupt event from I2S */
@ -81,21 +81,21 @@
#define TIVA_IRQ_GPT3B (38) /* GPT3B interrupt event */
#define TIVA_IRQ_CRYPTO_RESULT_AVAIL (39) /* CRYPTO result available interrupt
* event */
#define TIVA_IRQ_DMA_DONE_COMB (40) /* Combined DMA done */
#define TIVA_IRQ_DMA_DONE (40) /* Combined DMA done */
#define TIVA_IRQ_DMA_ERR (41) /* DMA bus error */
#define TIVA_IRQ_FLASH (42) /* FLASH controller error event */
#define TIVA_IRQ_SWEV0 (43) /* Software event 0 */
#define TIVA_IRQ_AUX_COMB (44) /* AUX combined event */
#define TIVA_IRQ_AUX (44) /* AUX combined event */
#define TIVA_IRQ_AON_PROG0 (45) /* AON programmable event 0 */
#define TIVA_IRQ_PROG0 (46) /* Programmable Interrupt 0 */
#define TIVA_IRQ_AUX_COMPA (47) /* AUX Compare A event */
#define TIVA_IRQ_AUX_ADC (48) /* AUX ADC interrupt event */
#define TIVA_IRQ_TRNG (49) /* TRNG Interrupt event */
#define TIVA_IRQ_OSC_COMB (50) /* Combined event from Oscillator
#define TIVA_IRQ_OSC (50) /* Combined event from Oscillator
* control */
#define TIVA_IRQ_AUX_TIMER2_EV0 (51) /* AUX Timer2 event 0 */
#define TIVA_IRQ_UART1_COMB (52) /* UART1 combined interrupt */
#define TIVA_IRQ_BATMON_COMB (53) /* Combined event from battery
#define TIVA_IRQ_UART1 (52) /* UART1 combined interrupt */
#define TIVA_IRQ_BATMON (53) /* Combined event from battery
* monitor */
#define NR_IRQS (54) /* Number of interrupt vectors */

12
arch/arm/src/tiva/Make.defs
View File

@ -87,15 +87,17 @@ CHIP_CSRCS = tiva_allocateheap.c tiva_irq.c tiva_lowputc.c tiva_serial.c
CHIP_CSRCS += tiva_ssi.c
ifeq ($(CONFIG_ARCH_CHIP_LM3S),y)
CHIP_CSRCS += tiva_start.c lm3s_gpio.c tiva_gpioirq.c
CHIP_CSRCS += lmxx_tm4c_start.c lm3s_gpio.c tiva_gpioirq.c
else ifeq ($(CONFIG_ARCH_CHIP_LM4F),y)
CHIP_CSRCS += tiva_start.c lm4f_gpio.c tiva_gpioirq.c
CHIP_CSRCS += lmxx_tm4c_start.c lm4f_gpio.c tiva_gpioirq.c
else ifeq ($(CONFIG_ARCH_CHIP_TM4C),y)
CHIP_CSRCS += tiva_start.c tm4c_gpio.c tiva_gpioirq.c
CHIP_CSRCS += lmxx_tm4c_start.c tm4c_gpio.c tiva_gpioirq.c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y)
CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
CHIP_CSRCS += cc13xx_enableclks.c cc13xx_enablepwr.c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y)
CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
CHIP_CSRCS += cc13xx_enableclks.c cc13xx_enablepwr.c
endif
ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
@ -166,7 +168,7 @@ VPATH += chip/lm
else ifeq ($(CONFIG_ARCH_CHIP_TM4C),y)
VPATH += chip/tm4c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y)
VPATH += chip/cc13x0
VPATH += chip/cc13xx
else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y)
VPATH += chip/cc13x2
VPATH += chip/cc13xx
endif

120
arch/arm/src/tiva/cc13xx/cc13xx_enableclks.c Normal file
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@ -0,0 +1,120 @@
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13xx_enableclks.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "hardware/tiva_prcm"
#include "tiva_enableclks.h"
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: cc13xx_periph_enableclks
*
* Description:
* Enable clocking in the selected modes for this peripheral.
*
****************************************************************************/
void cc13xx_periph_enableclk(uint32_t peripheral, uint32_t modeset)
{
DEBUGASSERT(modeset != 0);
if ((modeset & CC13XX_RUNMODE_CLOCK) != 0)
{
prcm_periph_runenable(peripheral);
}
if ((modeset & CC13XX_SLEEPMODE_CLOCK) != 0)
{
prcm_periph_sleepenable(peripheral);
}
if ((modeset & CC13XX_DEEPSLEEPMODE_CLOCK) != 0)
{
prcm_periph_deepsleepenable(peripheral);
}
prcm_load_set();
while (!prcm_load_get())
{
}
}
/****************************************************************************
* Name: cc13xx_periph_disableclk
*
* Description:
* Disable clocking in the selected modes for this peripheral.
*
****************************************************************************/
void cc13xx_periph_disableclk(uint32_t peripheral, uint32_t modeset)
{
DEBUGASSERT(modeset != 0);
if ((modeset & CC13XX_RUNMODE_CLOCK) != 0)
{
prcm_periph_rundisable(peripheral);
}
if ((modeset & CC13XX_SLEEPMODE_CLOCK) != 0)
{
prcm_periph_sleepdisable(peripheral);
}
if ((modeset & CC13XX_DEEPSLEEPMODE_CLOCK) != 0)
{
prcm_periph_deepsleepdisable(peripheral);
}
prcm_load_set();
}

260
arch/arm/src/tiva/cc13xx/cc13xx_enableclks.h Normal file
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@ -0,0 +1,260 @@
/****************************************************************************************************
* arch/arm/src/tiva/cc13xx/cc13xx_enableclks.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLECLKS_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLECLKS_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "cc13xx/cc13xx_prcm.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
#define CC13XX_RUNMODE_CLOCK (1 << 0)
#define CC13XX_SLEEPMODE_CLOCK (1 << 1)
#define CC13XX_DEEPSLEEPMODE_CLOCK (1 << 2)
#define CC13XX_ALLMODE_CLOCKS (7)
/* Watchdog Timer Clock Control */
#define tiva_wdt0_enableclk()
#define tiva_wdt0_disableclk()
/* 16/32-Bit Timer Clock Control */
#define tiva_gptm0_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER0, CC13XX_RUNMODE_CLOCK)
#define tiva_gptm0_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER0, CC13XX_RUNMODE_CLOCK)
#define tiva_gptm0_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER0, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gptm0_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER0, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gptm0_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER0, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gptm0_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER0, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gptm0_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER0, CC13XX_ALLMODE_CLOCKS)
#define tiva_gptm0_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER0, CC13XX_ALLMODE_CLOCKS)
#define tiva_gptm1_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER1, CC13XX_RUNMODE_CLOCK)
#define tiva_gptm1_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER1, CC13XX_RUNMODE_CLOCK)
#define tiva_gptm1_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER1, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gptm1_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER1, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gptm1_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER1, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gptm1_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER1, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gptm1_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER1, CC13XX_ALLMODE_CLOCKS)
#define tiva_gptm1_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER1, CC13XX_ALLMODE_CLOCKS)
#define tiva_gptm2_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER2, CC13XX_RUNMODE_CLOCK)
#define tiva_gptm2_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER2, CC13XX_RUNMODE_CLOCK)
#define tiva_gptm2_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER2, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gptm2_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER2, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gptm2_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER2, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gptm2_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER2, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gptm2_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER2, CC13XX_ALLMODE_CLOCKS)
#define tiva_gptm2_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER2, CC13XX_ALLMODE_CLOCKS)
#define tiva_gptm3_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER3, CC13XX_RUNMODE_CLOCK)
#define tiva_gptm3_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER3, CC13XX_RUNMODE_CLOCK)
#define tiva_gptm3_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER3, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gptm3_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER3, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gptm3_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER3, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gptm3_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER3, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gptm3_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_TIMER3, CC13XX_ALLMODE_CLOCKS)
#define tiva_gptm3_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_TIMER3, CC13XX_ALLMODE_CLOCKS)
/* GPIO Clock Control */
#define tiva_gpio_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_GPIO, CC13XX_RUNMODE_CLOCK)
#define tiva_gpio_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_GPIO, CC13XX_RUNMODE_CLOCK)
#define tiva_gpio_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_GPIO, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gpio_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_GPIO, CC13XX_SLEEPMODE_CLOCK)
#define tiva_gpio_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_GPIO, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gpio_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_GPIO, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_gpio_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_GPIO, CC13XX_ALLMODE_CLOCKS)
#define tiva_gpio_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_GPIO, CC13XX_ALLMODE_CLOCKS)
#define tiva_gpioa_runenable() tiva_gpio_runenable()
#define tiva_gpioa_rundisable() tiva_gpio_rundisable()
#define tiva_gpioa_sleepenable() tiva_gpio_sleepenable()
#define tiva_gpioa_sleepdisable() tiva_gpio_sleepdisable()
#define tiva_gpioa_deepsleepenable() tiva_gpio_deepsleepenable()
#define tiva_gpioa_deepsleepdisable() tiva_gpio_deepsleepdisable()
#define tiva_gpioa_enableclk() tiva_gpio_enableclk()
#define tiva_gpioa_disableclk() tiva_gpio_disableclk()
/* μDMA Clock Control */
#define tiva_udma_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_UDMA, CC13XX_RUNMODE_CLOCK)
#define tiva_udma_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_UDMA, CC13XX_RUNMODE_CLOCK)
#define tiva_udma_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_UDMA, CC13XX_SLEEPMODE_CLOCK)
#define tiva_udma_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_UDMA, CC13XX_SLEEPMODE_CLOCK)
#define tiva_udma_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_UDMA, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_udma_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_UDMA, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_udma_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_UDMA, CC13XX_ALLMODE_CLOCKS)
#define tiva_udma_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_UDMA, CC13XX_ALLMODE_CLOCKS)
/* UART Clock Control */
#define tiva_uart0_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_UART0, CC13XX_RUNMODE_CLOCK)
#define tiva_uart0_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_UART0, CC13XX_RUNMODE_CLOCK)
#define tiva_uart0_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_UART0, CC13XX_SLEEPMODE_CLOCK)
#define tiva_uart0_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_UART0, CC13XX_SLEEPMODE_CLOCK)
#define tiva_uart0_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_UART0, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_uart0_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_UART0, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_uart0_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_UART0, CC13XX_ALLMODE_CLOCKS)
#define tiva_uart0_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_UART0, CC13XX_ALLMODE_CLOCKS)
#ifdef CONFIG_ARCH_CHIP_CC13X2
# define tiva_uart1_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_UART1, CC13XX_RUNMODE_CLOCK)
# define tiva_uart1_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_UART1, CC13XX_RUNMODE_CLOCK)
# define tiva_uart1_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_UART1, CC13XX_SLEEPMODE_CLOCK)
# define tiva_uart1_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_UART1, CC13XX_SLEEPMODE_CLOCK)
# define tiva_uart1_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_UART1, CC13XX_DEEPSLEEPMODE_CLOCK)
# define tiva_uart1_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_UART1, CC13XX_DEEPSLEEPMODE_CLOCK)
# define tiva_uart1_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_UART1, CC13XX_ALLMODE_CLOCKS)
# define tiva_uart1_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_UART1, CC13XX_ALLMODE_CLOCKS)
#endif
/* SSI Clock Control */
#define tiva_ssi0_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_SSI0, CC13XX_RUNMODE_CLOCK)
#define tiva_ssi0_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_SSI0, CC13XX_RUNMODE_CLOCK)
#define tiva_ssi0_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_SSI0, CC13XX_SLEEPMODE_CLOCK)
#define tiva_ssi0_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_SSI0, CC13XX_SLEEPMODE_CLOCK)
#define tiva_ssi0_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_SSI0, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_ssi0_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_SSI0, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_ssi0_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_SSI0, CC13XX_ALLMODE_CLOCKS)
#define tiva_ssi0_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_SSI0, CC13XX_ALLMODE_CLOCKS)
#define tiva_ssi1_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_SSI1, CC13XX_RUNMODE_CLOCK)
#define tiva_ssi1_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_SSI1, CC13XX_RUNMODE_CLOCK)
#define tiva_ssi1_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_SSI1, CC13XX_SLEEPMODE_CLOCK)
#define tiva_ssi1_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_SSI1, CC13XX_SLEEPMODE_CLOCK)
#define tiva_ssi1_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_SSI1, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_ssi1_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_SSI1, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_ssi1_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_SSI1, CC13XX_ALLMODE_CLOCKS)
#define tiva_ssi1_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_SSI1, CC13XX_ALLMODE_CLOCKS)
/* I2C Clock Control */
#define tiva_i2c0_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_I2C0, CC13XX_RUNMODE_CLOCK)
#define tiva_i2c0_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_I2C0, CC13XX_RUNMODE_CLOCK)
#define tiva_i2c0_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_I2C0, CC13XX_SLEEPMODE_CLOCK)
#define tiva_i2c0_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_I2C0, CC13XX_SLEEPMODE_CLOCK)
#define tiva_i2c0_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_I2C0, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_i2c0_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_I2C0, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_i2c0_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_I2C0, CC13XX_ALLMODE_CLOCKS)
#define tiva_i2c0_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_I2C0, CC13XX_ALLMODE_CLOCKS)
/* I2S Clock Control */
#define tiva_i2s_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_I2S, CC13XX_RUNMODE_CLOCK)
#define tiva_i2s_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_I2S, CC13XX_RUNMODE_CLOCK)
#define tiva_i2s_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_I2S, CC13XX_SLEEPMODE_CLOCK)
#define tiva_i2s_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_I2S, CC13XX_SLEEPMODE_CLOCK)
#define tiva_i2s_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_I2S, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_i2s_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_I2S, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_i2s_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_I2S, CC13XX_ALLMODE_CLOCKS)
#define tiva_i2s_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_I2S, CC13XX_ALLMODE_CLOCKS)
#define tiva_i2s0_runenable() tiva_i2s_runenable()
#define tiva_i2s0_rundisable() tiva_i2s_rundisable()
#define tiva_i2s0_sleepenable() tiva_i2s_sleepenable()
#define tiva_i2s0_sleepdisable() tiva_i2s_sleepdisable()
#define tiva_i2s0_deepsleepenable() tiva_i2s_deepsleepenable()
#define tiva_i2s0_deepsleepdisable() tiva_i2s_deepsleepdisable()
#define tiva_i2s0_enableclk() tiva_i2s_enableclk()
#define tiva_i2s0_disableclk() tiva_i2s_disableclk()
/* CRC/PKA Clock Control */
#define tiva_crypto_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_CRYPTO, CC13XX_RUNMODE_CLOCK)
#define tiva_crypto_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_CRYPTO, CC13XX_RUNMODE_CLOCK)
#define tiva_crypto_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_CRYPTO, CC13XX_SLEEPMODE_CLOCK)
#define tiva_crypto_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_CRYPTO, CC13XX_SLEEPMODE_CLOCK)
#define tiva_crypto_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_CRYPTO, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_crypto_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_CRYPTO, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_crypto_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_CRYPTO, CC13XX_ALLMODE_CLOCKS)
#define tiva_crypto_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_CRYPTO, CC13XX_ALLMODE_CLOCKS)
#ifdef CONFIG_ARCH_CHIP_CC13X2
# define tiva_pka_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_PKA, CC13XX_RUNMODE_CLOCK)
# define tiva_pka_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_PKA, CC13XX_RUNMODE_CLOCK)
# define tiva_pka_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_PKA, CC13XX_SLEEPMODE_CLOCK)
# define tiva_pka_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_PKA, CC13XX_SLEEPMODE_CLOCK)
# define tiva_pka_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_PKA, CC13XX_DEEPSLEEPMODE_CLOCK)
# define tiva_pka_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_PKA, CC13XX_DEEPSLEEPMODE_CLOCK)
# define tiva_pka_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_PKA, CC13XX_ALLMODE_CLOCKS)
# define tiva_pka_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_PKA, CC13XX_ALLMODE_CLOCKS)
#endif
/* TRNG Clock Control */
#define tiva_trng_runenable() cc13xx_periph_enableclk(PRCM_PERIPH_TRNG, CC13XX_RUNMODE_CLOCK)
#define tiva_trng_rundisable() cc13xx_periph_disableclk(PRCM_PERIPH_TRNG, CC13XX_RUNMODE_CLOCK)
#define tiva_trng_sleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TRNG, CC13XX_SLEEPMODE_CLOCK)
#define tiva_trng_sleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TRNG, CC13XX_SLEEPMODE_CLOCK)
#define tiva_trng_deepsleepenable() cc13xx_periph_enableclk(PRCM_PERIPH_TRNG, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_trng_deepsleepdisable() cc13xx_periph_disableclk(PRCM_PERIPH_TRNG, CC13XX_DEEPSLEEPMODE_CLOCK)
#define tiva_trng_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_TRNG, CC13XX_ALLMODE_CLOCKS)
#define tiva_trng_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_TRNG, CC13XX_ALLMODE_CLOCKS)
/****************************************************************************************************
* Public Function Prototypes
****************************************************************************************************/
/****************************************************************************************************
* Name: cc13xx_periph_enableclks
*
* Description:
* Enable clocking in the selected modes for this peripheral.
*
****************************************************************************************************/
void cc13xx_periph_enableclk(uint32_t peripheral, uint32_t modeset);
/****************************************************************************************************
* Name: cc13xx_periph_disableclk
*
* Description:
* Disable clocking in the selected modes for this peripheral.
*
****************************************************************************************************/
void cc13xx_periph_disableclk(uint32_t peripheral, uint32_t modeset);
#endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLECLKS_H */

129
arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.c Normal file
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@ -0,0 +1,129 @@
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "hardware/tiva_prcm"
#include "tiva_enablepwr.h"
/****************************************************************************
* Private Data
****************************************************************************/
static uint16_t g_domain_usage[2];
/****************************************************************************
* Public Functions
****************************************************************************/
/************************************************************************************
* Name: cc13xx_periph_enablepwr
*
* Description:
* Enable the power domain associated with the peripheral.
*
************************************************************************************/
void cc13xx_periph_enablepwr(uint32_t peripheral)
{
irgstate_t flags;
uint32_t domain;
int dndx;
int pndx;
dndx = PRCM_DOMAIN_INDEX(peripheral);
pndx = PRCM_PERIPH_ID(peripheral);
domain = (pndx == 0 ? PRCM_DOMAIN_SERIAL : PRCM_DOMAIN_PERIPH)
/* Remember that this peripheral needs power in this domain */
flags = spin_lock_irqsave();
g_domain_usage[dndx] |= (1 << pndx);
/* Make sure that power is enabled in that domain */
prcm_powerdomain_on(domain);
spin_unlock_irqrestore(flags);
/* Wait for the power domain to be ready. REVISIT: This really should be in the
* critical section but this could take too long.
*/
while (!prcm_powerdomain_status(domain))
{
}
}
/************************************************************************************
* Name: cc13xx_periph_disablepwr
*
* Description:
* Disable the power domain associated with the peripheral if and only if all
* peripherals using that power domain no longer need power.
*
************************************************************************************/
void cc13xx_periph_disablepwr(uint32_t peripheral)
{
int dndx = PRCM_DOMAIN_INDEX(peripheral);
int pndx = PRCM_PERIPH_ID(peripheral);
irgstate_t flags;
/* This peripheral no longer needs power in this domain */
flags = spin_lock_irqsave();
g_domain_usage[dndx] &= ~(1 << pndx);
/* If there are no peripherals needing power in this domain, then turn off the
* power domain.
*/
if (g_domain_usage[dndx] == 0)
{
prcm_powerdomain_off(pndx == ? PRCM_DOMAIN_SERIAL : PRCM_DOMAIN_PERIPH);
}
spin_unlock_irqrestore(flags);
}

164
arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.h Normal file
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@ -0,0 +1,164 @@
/************************************************************************************
* arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLEPWR_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLEPWR_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "cc13xx/cc13xx_prcm.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* CC13xx Power Domains:
*
* 1) PRCM_DOMAIN_RFCORE : RF Core
* 2) PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
* 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1
* 4) PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
* 5) PRCM_DOMAIN_SYSBUS
* 6) PRCM_DOMAIN_CPU
*/
/* Watchdog Timer Power Control */
#define tiva_wdt0_enablepwr()
#define tiva_wdt0_disablepwr()
/* 16/32-Bit Timer Power Control */
#define tiva_gptm0_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_TIMER0)
#define tiva_gptm0_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_TIMER0)
#define tiva_gptm1_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_TIMER1)
#define tiva_gptm1_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_TIMER1)
#define tiva_gptm2_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_TIMER2)
#define tiva_gptm2_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_TIMER2)
#define tiva_gptm3_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_TIMER3)
#define tiva_gptm3_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_TIMER3)
/* GPIO Power Control */
#define tiva_gpio_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_GPIO)
#define tiva_gpio_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_GPIO)
#define tiva_gpioa_enablepwr() tiva_gpio_enablepwr()
#define tiva_gpioa_disablepwr() tiva_gpio_disablepwr()
/* μDMA Power Control */
#define tiva_udma_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_UDMA)
#define tiva_udma_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_UDMA)
/* UART Power Control */
#define tiva_uart0_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_UART0)
#define tiva_uart0_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_UART0)
#ifdef CONFIG_ARCH_CHIP_CC13X2
# define tiva_uart1_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_UART1)
# define tiva_uart1_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_UART1)
#endif
/* SSI Power Control */
#define tiva_ssi0_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_SSI0)
#define tiva_ssi0_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_SSI0)
#define tiva_ssi1_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_SSI1)
#define tiva_ssi1_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_SSI1)
/* I2C Power Control */
#define tiva_i2c0_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_I2C0)
#define tiva_i2c0_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_I2C0)
/* I2S Power Control */
#define tiva_i2s_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_I2S)
#define tiva_i2s_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_I2S)
#define tiva_i2s0_enablepwr() tiva_i2s_enablepwr()
#define tiva_i2s0_disablepwr() tiva_i2s_disablepwr()
/* CRC/PKA Power Control */
#define tiva_crypto_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_CRYPTO)
#define tiva_crypto_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_CRYPTO)
#ifdef CONFIG_ARCH_CHIP_CC13X2
# define tiva_pka_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_PKA)
# define tiva_pka_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_PKA)
#endif
/* TRNG Power Control */
#define tiva_trng_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_TRNG)
#define tiva_trng_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_TRNG)
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: cc13xx_periph_enablepwr
*
* Description:
* Enable the power domain associated with the peripheral.
*
************************************************************************************/
void cc13xx_periph_enablepwr(uint32_t peripheral);
/************************************************************************************
* Name: cc13xx_periph_disablepwr
*
* Description:
* Disable the power domain associated with the peripheral if and only if all
* peripherals using that power domain no longer need power.
*
************************************************************************************/
void cc13xx_periph_disablepwr(uint32_t peripheral);
#endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLEPWR_H */

16
arch/arm/src/tiva/cc13xx/cc13xx_gpio.h
View File

@ -43,6 +43,8 @@
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_gpio.h"
#include "hardware/tiva_ioc.h"
/****************************************************************************
* Pre-processor Definitions
@ -193,13 +195,13 @@
*/
#define GPIO_IOMODE_SHIFT (8) /* Bits 8-10: I/O Mode */
#define GPIO_IOMODE_MASK (7 << IOC_IOCFG1_IOMODE_SHIFT)
# define GPIO_IOMODE_NORMAL (0 << IOC_IOCFG1_IOMODE_SHIFT) /* Normal I/O */
# define GPIO_IOMODE_INV (1 << IOC_IOCFG1_IOMODE_SHIFT) /* Inverted I/O */
# define GPIO_IOMODE_OPENDR (4 << IOC_IOCFG1_IOMODE_SHIFT) /* Open drain */
# define GPIO_IOMODE_OPENDRINV (5 << IOC_IOCFG1_IOMODE_SHIFT) /* Open drain, inverted I/O */
# define GPIO_IOMODE_OPENSRC (6 << IOC_IOCFG1_IOMODE_SHIFT) /* Open source */
# define GPIO_IOMODE_OPENSRCINV (7 << IOC_IOCFG1_IOMODE_SHIFT) /* Open source, inverted I/O */
#define GPIO_IOMODE_MASK (7 << GPIO_IOMODE_SHIFT)
# define GPIO_IOMODE_NORMAL (0 << GPIO_IOMODE_SHIFT) /* Normal I/O */
# define GPIO_IOMODE_INV (1 << GPIO_IOMODE_SHIFT) /* Inverted I/O */
# define GPIO_IOMODE_OPENDR (4 << GPIO_IOMODE_SHIFT) /* Open drain */
# define GPIO_IOMODE_OPENDRINV (5 << GPIO_IOMODE_SHIFT) /* Open drain, inverted I/O */
# define GPIO_IOMODE_OPENSRC (6 << GPIO_IOMODE_SHIFT) /* Open source */
# define GPIO_IOMODE_OPENSRCINV (7 << GPIO_IOMODE_SHIFT) /* Open source, inverted I/O */
/* Edge detect mode
*

209
arch/arm/src/tiva/cc13xx/cc13xx_prcm.c
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@ -1,4 +1,4 @@
/****************************************************************************
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@ -42,31 +42,20 @@
* Included Files
******************************************************************************/
#include <nuttx/config.y>
#include <stdint.h>
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include "up_arch.h"
#include "hardware/tiva_prcm.h"
#include "cc13xx/cc13xx_prcm.h"
/******************************************************************************
* Pre-processor Definitions
******************************************************************************/
/* This macro extracts the array index out of the peripheral number */
#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf)
/* This macro extracts the peripheral instance number and generates bit mask */
#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f))
/******************************************************************************
* Private Data
******************************************************************************/
/* The size of a register look-up table */
#define TABLE_SIZE 7
/******************************************************************************
* Private Data
******************************************************************************/
/* Arrays that maps the "peripheral set" number (which is stored in
* bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that
* contains the relevant bit for that peripheral.
@ -74,7 +63,7 @@
/* Run mode registers */
static const uintptr_t g_rcgcr_base[TABLE_SIZE] =
static const uintptr_t g_rcgcr_base[PRCM_NPERIPH] =
{
TIVA_PRCM_GPTCLKGR, /* Index 0 */
TIVA_PRCM_SSICLKGR, /* Index 1 */
@ -87,7 +76,7 @@ static const uintptr_t g_rcgcr_base[TABLE_SIZE] =
/* Sleep mode registers */
static const uintptr_t g_scgcr_base[TABLE_SIZE] =
static const uintptr_t g_scgcr_base[PRCM_NPERIPH] =
{
TIVA_PRCM_GPTCLKGS, /* Index 0 */
TIVA_PRCM_SSICLKGS, /* Index 1 */
@ -100,7 +89,7 @@ static const uintptr_t g_scgcr_base[TABLE_SIZE] =
/* Deep sleep mode registers */
static const uintptr_t g_dcgcr_base[TABLE_SIZE] =
static const uintptr_t g_dcgcr_base[PRCM_NPERIPH] =
{
TIVA_PRCM_GPTCLKGDS, /* Index 0 */
TIVA_PRCM_SSICLKGDS, /* Index 1 */
@ -111,13 +100,13 @@ static const uintptr_t g_dcgcr_base[TABLE_SIZE] =
TIVA_PRCM_I2CCLKGDS /* Index 6 */
};
/******************************************************************************
* Public Functions
******************************************************************************/
/******************************************************************************
* Name: prcm_infclock_configure
*
* Public Functions
******************************************************************************/
/******************************************************************************
* Name: prcm_infclock_configure
*
* Description:
* Configure the infrastructure clock.
*
@ -129,12 +118,12 @@ static const uintptr_t g_dcgcr_base[TABLE_SIZE] =
* can be enabled and disabled from the AON Wake Up Controller.
*
* NOTE: If source clock is 48 MHz, minimum clock divider is 2.
*
* Input Parameters
*
* Input Parameters:
* clockdiv - Determines the division ratio for the infrastructure
* clock when the device is in the specified mode. Allowed
* division factors for all three System CPU power modes are:
* {1, 2, 8, or 32}
* {1, 2, 8, or 32}
* powermode - Determines the System CPU operation mode for which to
* modify the clock division factor. The three allowed power
* modes are:{PRCM_RUN_MODE, PRCM_SLEEP_MODE, or
@ -146,10 +135,10 @@ void prcm_infclock_configure(enum prcm_clkdivider_e clkdiv,
enum prcm_powermode_e powermode)
{
uint32_t divisor;
/* Find the correct division factor. */
divisor = 0;
divisor = 0;
if (clkdiv == PRCM_CLOCK_DIV_1)
{
divisor = PRCM_INFRCLKDIVR_RATIO_DIV1;
@ -183,7 +172,7 @@ void prcm_infclock_configure(enum prcm_clkdivider_e clkdiv,
}
else if (powermode == PRCM_DEEP_SLEEP_MODE)
{
putreg32(divisor, TIVA_PRCM_INFRCLKDIVDSS);
putreg32(divisor, TIVA_PRCM_INFRCLKDIVDS);
}
else
{
@ -248,11 +237,12 @@ void prcm_audioclock_manual(uint32_t clkconfig, uint32_t mstdiv,
retval &= ~(PRCM_I2SCLKCTL_WCLKPHASE_MASK | PRCM_I2SCLKCTL_POSEDGE);
putreg32(regval | clkconfig, TIVA_PRCM_I2SCLKCTL);
}
#endif
/******************************************************************************
* Name: prcm_audioclock_configure
*
* Description:
/******************************************************************************
* Name: prcm_audioclock_configure
*
* Description:
* Configure the audio clock generation
*
* Use this function to set the sample rate when using internal audio clock
@ -328,10 +318,10 @@ void prcm_audioclock_configure(uint32_t clkconfig,
}
#endif
/******************************************************************************
* Name: prcm_powerdomain_on
*
* Description:
/******************************************************************************
* Name: prcm_powerdomain_on
*
* Description:
* Turn power on in power domains in the MCU domain
* Use this function to turn on power domains inside the MCU voltage domain.
*
@ -367,7 +357,7 @@ void prcm_audioclock_configure(uint32_t clkconfig,
* Any write operation to a power domain which is still not operational can
* result in unexpected behavior.
*
* Input Parameters
* Input Parameters:
* domains - Determines which power domains to turn on. The domains that
* can be turned on/off are:
* 1) PRCM_DOMAIN_RFCORE : RF Core
@ -428,17 +418,17 @@ void prcm_powerdomain_on(uint32_t domains)
}
}
/******************************************************************************
* Name: prcm_powerdomain_off
*
* Description:
/******************************************************************************
* Name: prcm_powerdomain_off
*
* Description:
* Turn off a specific power domain
* Use this function to power down domains inside the MCU voltage domain.
*
* NOTE: See prcm_powerdomain_on() for specifics regarding on/off
* configuration.
*
* Input Parameters
* Input Parameters:
* domains - Determines which power domains to turn off. The domains that
* can be turned on/off are:
* 1) PRCM_DOMAIN_RFCORE : RF Core
@ -509,10 +499,67 @@ void prcm_powerdomain_off(uint32_t domains)
}
}
/******************************************************************************
* Name: prcm_periph_rundisable
*
* Description:
/******************************************************************************
* Name: prcm_powerdomain_status
*
* Description:
* Use this function to retrieve the current power status of one or more
* power domains.
*
* Input Parameters:
* domains - Determines which domain to get the power status for. The
* parameter must be an OR'ed combination of one or several of:
* 1) PRCM_DOMAIN_RFCORE : RF Core.
* 2) PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
* 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S,
* DMA, UART1
*
* Returned Value
* - True: The specified domains are all powered up.
* - False: One or more of the domains is powered down.
*
******************************************************************************/
bool prcm_powerdomain_status(uint32_t domains)
{
uint32_t pdstat0;
uint32_t pdstat1;
bool status;
DEBUGASSERT((domains & (PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL |
PRCM_DOMAIN_PERIPH)) != 0);
status = true;
pdstat0 = getreg32(TIVA_PRCM_PDSTAT0);
pdstat1 = getreg32(TIVA_PRCM_PDSTAT1);
/* Return the correct power status. */
if (domains & PRCM_DOMAIN_RFCORE)
{
status = status && ((pdstat0 & PRCM_PDSTAT0_RFC_ON) != 0 ||
(pdstat1 & PRCM_PDSTAT1_RFC_ON) != 0);
}
if (domains & PRCM_DOMAIN_SERIAL)
{
status = status && (pdstat0 & PRCM_PDSTAT0_SERIAL_ON) != 0;
}
if (domains & PRCM_DOMAIN_PERIPH)
{
status = status && (pdstat0 & PRCM_DOMAIN_PERIPH) != 0;
}
/* Return the status. */
return status;
}
/******************************************************************************
* Name: prcm_periph_runenable
*
* Description:
* Enables a peripheral in Run mode
*
* Peripherals are enabled with this function. At power-up, some peripherals
@ -545,17 +592,17 @@ void prcm_periph_runenable(uint32_t peripheral)
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
DEBUGASSERT(index < PRCM_NPERIPH);
/* Enable module in Run Mode. */
modifyreg32(g_rcgcr_base[index], PRCM_PERIPH_MASKBIT(peripheral), 0);
}
/******************************************************************************
* Name: prcm_periph_rundisable
*
* Description:
/******************************************************************************
* Name: prcm_periph_rundisable
*
* Description:
* Disables a peripheral in Run mode
*
* Peripherals are disabled with this function. Once disabled, they will not
@ -584,17 +631,17 @@ void prcm_periph_rundisable(uint32_t peripheral)
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
DEBUGASSERT(index < PRCM_NPERIPH);
/* Disable module in Run Mode. */
modifyreg32(g_rcgcr_base[index], 0, PRCM_PERIPH_MASKBIT(peripheral));
}
/******************************************************************************
* Name: prcm_periph_sleepenable
*
* Description:
/******************************************************************************
* Name: prcm_periph_sleepenable
*
* Description:
* Enables a peripheral in sleep mode
*
* This function allows a peripheral to continue operating when the processor
@ -622,17 +669,17 @@ void prcm_periph_sleepenable(uint32_t peripheral)
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
DEBUGASSERT(index < PRCM_NPERIPH);
/* Enable this peripheral in sleep mode. */
modifyreg32(g_scgcr_base[index], PRCM_PERIPH_MASKBIT(peripheral), 0);
}
/******************************************************************************
* Name: prcm_periph_sleepdisable
*
* Description:
/******************************************************************************
* Name: prcm_periph_sleepdisable
*
* Description:
* Disables a peripheral in sleep mode
*
* This function causes a peripheral to stop operating when the processor goes
@ -661,17 +708,17 @@ void prcm_periph_sleepdisable(uint32_t peripheral)
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
DEBUGASSERT(index < PRCM_NPERIPH);
/* Disable this peripheral in sleep mode */
modifyreg32(g_scgcr_base[index], 0, PRCM_PERIPH_MASKBIT(peripheral));
}
/******************************************************************************
* Name: prcm_periph_deepsleepenable
*
* Description:
/******************************************************************************
* Name: prcm_periph_deepsleepenable
*
* Description:
* Enables a peripheral in deep-sleep mode
*
* This function allows a peripheral to continue operating when the processor
@ -699,17 +746,17 @@ void prcm_periph_deepsleepenable(uint32_t peripheral)
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
DEBUGASSERT(index < PRCM_NPERIPH);
/* Enable this peripheral in sleep mode. */
modifyreg32(g_dcgcr_base[index], PRCM_PERIPH_MASKBIT(peripheral), 0);
}
/******************************************************************************
* Name: prcm_periph_deepsleepdisable
*
* Description:
/******************************************************************************
* Name: prcm_periph_deepsleepdisable
*
* Description:
* Disables a peripheral in deep-sleep mode
*
* This function causes a peripheral to stop operating when the processor goes
@ -740,7 +787,7 @@ void prcm_periph_deepsleepdisable(uint32_t peripheral)
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
DEBUGASSERT(index < PRCM_NPERIPH);
/* Enable this peripheral in sleep mode. */

104
arch/arm/src/tiva/cc13xx/cc13xx_prcm.h
View File

@ -48,6 +48,13 @@
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include "up_arch.h"
#include "hardware/tiva_prcm.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -83,29 +90,52 @@
/* Encoded values used for enabling and disabling peripheral modules in the
* MCU domain. Encoding:
*
* Bits 0-4: Defines the bit position within the register.
* Bits 8-11: Defines the index into the register offset constant tables.
* Bits 0-4: Defines the bit position within the register.
* Bits 5-7: Defines the index into the register offset constant tables.
* Bit 8: Power domain. 0=SERIAL 1=PERIPH
* Bits 12-15: Unique peripheral identifier
*/
#define PRCM_PERIPH_TIMER0 ((0 << 8) | PRCM_GPTCLKG_CLKEN_GPT0_SHIFT)
#define PRCM_PERIPH_TIMER1 ((0 << 8) | PRCM_GPTCLKG_CLKEN_GPT1_SHIFT)
#define PRCM_PERIPH_TIMER2 ((0 << 8) | PRCM_GPTCLKG_CLKEN_GPT2_SHIFT)
#define PRCM_PERIPH_TIMER3 ((0 << 8) | PRCM_GPTCLKG_CLKEN_GPT3_SHIFT)
#define PRCM_PERIPH_SSI0 ((1 << 8) | PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
#define PRCM_PERIPH_SSI1 ((1 << 8) | PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
#define PRCM_PERIPH_UART0 ((2 << 8) | PRCM_UARTCLKG_CLKEN_UART0_SHIFT)
#define _PRCM_PERIPH(p,d,i,b) (((p) << 12) | ((d) << 8) | ((i) << 5) | (b))
#define PRCM_PERIPH_TIMER0 _PRCM_PERIPH( 0, 1, 0, PRCM_GPTCLKG_CLKEN_GPT0_SHIFT)
#define PRCM_PERIPH_TIMER1 _PRCM_PERIPH( 1, 1, 0, PRCM_GPTCLKG_CLKEN_GPT1_SHIFT)
#define PRCM_PERIPH_TIMER2 _PRCM_PERIPH( 2, 1, 0, PRCM_GPTCLKG_CLKEN_GPT2_SHIFT)
#define PRCM_PERIPH_TIMER3 _PRCM_PERIPH( 3, 1, 0, PRCM_GPTCLKG_CLKEN_GPT3_SHIFT)
#define PRCM_PERIPH_SSI0 _PRCM_PERIPH( 4, 0, 1, PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
#define PRCM_PERIPH_SSI1 _PRCM_PERIPH( 5, 1, 1, PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
#define PRCM_PERIPH_UART0 _PRCM_PERIPH( 6, 0, 2, PRCM_UARTCLKG_CLKEN_UART0_SHIFT)
#ifdef CONFIG_ARCH_CHIP_CC13X2
# define PRCM_PERIPH_UART1 ((2 << 8) | PRCM_UARTCLKG_CLKEN_UART1_SHIFT)
# define PRCM_PERIPH_UART1 _PRCM_PERIPH( 7, 1, 2, PRCM_UARTCLKG_CLKEN_UART1_SHIFT)
#endif
#define PRCM_PERIPH_I2C0 ((3 << 8) | PRCM_I2CCLKGR_CLKEN_SHIFT)
#define PRCM_PERIPH_CRYPTO ((4 << 8) | PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
#define PRCM_PERIPH_TRNG ((4 << 8) | PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
#define PRCM_PERIPH_I2C0 _PRCM_PERIPH( 8, 0, 3, PRCM_I2CCLKGR_CLKEN_SHIFT)
#define PRCM_PERIPH_CRYPTO _PRCM_PERIPH( 9, 1, 4, PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
#define PRCM_PERIPH_TRNG _PRCM_PERIPH(10, 1, 4, PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
#ifdef CONFIG_ARCH_CHIP_CC13X2
# define PRCM_PERIPH_PKA ((4 << 8) | PRCM_SECDMACLKG_PKA_CLKEN_SHIFT)
# define PRCM_PERIPH_PKA _PRCM_PERIPH(11, 1, 4, PRCM_SECDMACLKG_PKA_CLKEN_SHIFT)
#endif
#define PRCM_PERIPH_UDMA ((4 << 8) | PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
#define PRCM_PERIPH_GPIO ((5 << 8) | PRCM_GPIOCLKG_CLKEN_SHIFT)
#define PRCM_PERIPH_I2S ((6 << 8) | PRCM_I2SCLKG_CLKEN_SHIFT)
#define PRCM_PERIPH_UDMA _PRCM_PERIPH(12, 1, 4, PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
#define PRCM_PERIPH_GPIO _PRCM_PERIPH(13, 1, 5, PRCM_GPIOCLKG_CLKEN_SHIFT)
#define PRCM_PERIPH_I2S _PRCM_PERIPH(14, 1, 6, PRCM_I2SCLKG_CLKEN_SHIFT)
/* This macro extracts the power domain index out of the peripheral number */
#define PRCM_PERIPH_ID(a) (((a) >> 12) & 15)
/* This macro extracts the power domain index out of the peripheral number */
#define PRCM_DOMAIN_INDEX(a) (((a) >> 8) & 1)
/* This macro extracts the array index out of the peripheral number */
#define PRCM_PERIPH_INDEX(a) (((a) >> 5) & 7)
/* This macro extracts the peripheral instance number and generates bit mask */
#define PRCM_PERIPH_MASKBIT(a) (1 << ((a) & 0x1f))
/* The size of a register look-up table */
#define PRCM_NPERIPH 7
/****************************************************************************
* Public Types
@ -199,7 +229,7 @@ static inline void prcm_mcuuldo_configure(uint32_t enable)
{
/* Enable or disable the uLDO request signal. */
putreg32(enabled, TIVA_PRCM_VDCTL);
putreg32(enable, TIVA_PRCM_VDCTL);
}
/******************************************************************************
@ -242,7 +272,7 @@ static inline void prcm_gptclock_set(uint32_t clkdiv)
*
******************************************************************************/
static inline uint32_t PRCMGPTimerClockDivisionGet(void)
static inline uint32_t prcm_gptclock_get(void)
{
return getreg32(TIVA_PRCM_GPTCLKDIV);
}
@ -412,7 +442,7 @@ static inline void prcm_rfpowerdown_whenidle(void)
*
******************************************************************************/
static inline bool (void)
static inline bool prcm_rfready(void)
{
/* Return the ready status of the RF Core. */
@ -469,7 +499,7 @@ static inline void prcm_cacheretention_disable(void)
*
* NOTE: If source clock is 48 MHz, minimum clock divider is 2.
*
* Input Parameters
* Input Parameters:
* clockdiv - Determines the division ratio for the infrastructure
* clock when the device is in the specified mode. Allowed
* division factors for all three System CPU power modes are:
@ -481,7 +511,8 @@ static inline void prcm_cacheretention_disable(void)
*
******************************************************************************/
void prcm_infclock_configure(uint32_t clkdiv, enum prcm_powermode_e powermode);
void prcm_infclock_configure(enum prcm_clkdivider_e clkdiv,
enum prcm_powermode_e powermode);
/******************************************************************************
* Name: prcm_audioclock_manual
@ -584,7 +615,7 @@ void prcm_audioclock_configure(uint32_t clkconfig,
* Any write operation to a power domain which is still not operational can
* result in unexpected behavior.
*
* Input Parameters
* Input Parameters:
* domains - Determines which power domains to turn on. The domains that
* can be turned on/off are:
* 1) PRCM_DOMAIN_RFCORE : RF Core
@ -609,7 +640,7 @@ void prcm_powerdomain_on(uint32_t domains);
* NOTE: See prcm_powerdomain_on() for specifics regarding on/off
* configuration.
*
* Input Parameters
* Input Parameters:
* domains - Determines which power domains to turn off. The domains that
* can be turned on/off are:
* 1) PRCM_DOMAIN_RFCORE : RF Core
@ -625,7 +656,30 @@ void prcm_powerdomain_on(uint32_t domains);
void prcm_powerdomain_off(uint32_t domains);
/******************************************************************************
* Name: prcm_periph_rundisable
* Name: prcm_powerdomain_status
*
* Description:
* Use this function to retrieve the current power status of one or more
* power domains.
*
* Input Parameters:
* domains - Determines which domain to get the power status for. The
* parameter must be an OR'ed combination of one or several of:
* 1) PRCM_DOMAIN_RFCORE : RF Core.
* 2) PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
* 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S,
* DMA, UART1
*
* Returned Value
* - True: The specified domains are all powered up.
* - False: One or more of the domains is powered down.
*
******************************************************************************/
bool prcm_powerdomain_status(uint32_t domains);
/******************************************************************************
* Name: prcm_periph_runenable
*
* Description:
* Enables a peripheral in Run mode

3
arch/arm/src/tiva/cc13xx/cc13xx_start.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
* arch/arm/src/tiva/cc13xx/cc13xx_start.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -44,6 +44,7 @@
#include <debug.h>
#include <nuttx/init.h>
#include <arch/irq.h>
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"

433
arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h Normal file
View File

@ -0,0 +1,433 @@
/************************************************************************************
* arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h
*
* Copyright (C) 2014, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLECLKS_H
#define __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLECLKS_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "chip.h"
#include "hardware/tiva_sysctrl.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Clocks are enabled or disabled by setting or clearing a bit (b) in a system
* control register (a))
*/
#define tiva_enableclk(a,b) modifyreg32((a),0,(b))
#define tiva_disableclk(a,b) modifyreg32((a),(b),0)
/* Watchdog Timer Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCWD
# define tiva_wdt_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCWD,SYSCON_RCGCWD(p))
# define tiva_wdt_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCWD,SYSCON_RCGCWD(p))
# define tiva_wdt0_enableclk() tiva_wdt_enableclk(0)
# define tiva_wdt1_enableclk() tiva_wdt_enableclk(1)
# define tiva_wdt0_disableclk() tiva_wdt_disableclk(0)
# define tiva_wdt1_disableclk() tiva_wdt_disableclk(1)
#else
#endif
/* 16/32-Bit Timer Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCTIMER
# define tiva_gptm_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCTIMER,SYSCON_RCGCTIMER(p))
# define tiva_gptm_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCTIMER,SYSCON_RCGCTIMER(p))
# define tiva_gptm0_enableclk() tiva_gptm_enableclk(0)
# define tiva_gptm1_enableclk() tiva_gptm_enableclk(1)
# define tiva_gptm2_enableclk() tiva_gptm_enableclk(2)
# define tiva_gptm3_enableclk() tiva_gptm_enableclk(3)
# define tiva_gptm4_enableclk() tiva_gptm_enableclk(4)
# define tiva_gptm5_enableclk() tiva_gptm_enableclk(5)
# define tiva_gptm6_enableclk() tiva_gptm_enableclk(6)
# define tiva_gptm7_enableclk() tiva_gptm_enableclk(7)
# define tiva_gptm0_disableclk() tiva_gptm_disableclk(0)
# define tiva_gptm1_disableclk() tiva_gptm_disableclk(1)
# define tiva_gptm2_disableclk() tiva_gptm_disableclk(2)
# define tiva_gptm3_disableclk() tiva_gptm_disableclk(3)
# define tiva_gptm4_disableclk() tiva_gptm_disableclk(4)
# define tiva_gptm5_disableclk() tiva_gptm_disableclk(5)
# define tiva_gptm6_disableclk() tiva_gptm_disableclk(6)
# define tiva_gptm7_disableclk() tiva_gptm_disableclk(7)
#else
#endif
/* GPIO Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCGPIO
# define tiva_gpio_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCGPIO,SYSCON_RCGCGPIO(p))
# define tiva_gpio_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCGPIO,SYSCON_RCGCGPIO(p))
# define tiva_gpioa_enableclk() tiva_gpio_enableclk(0)
# define tiva_gpiob_enableclk() tiva_gpio_enableclk(1)
# define tiva_gpioc_enableclk() tiva_gpio_enableclk(2)
# define tiva_gpiod_enableclk() tiva_gpio_enableclk(3)
# define tiva_gpioe_enableclk() tiva_gpio_enableclk(4)
# define tiva_gpiof_enableclk() tiva_gpio_enableclk(5)
# define tiva_gpiog_enableclk() tiva_gpio_enableclk(6)
# define tiva_gpioh_enableclk() tiva_gpio_enableclk(7)
# define tiva_gpioj_enableclk() tiva_gpio_enableclk(8)
# define tiva_gpiok_enableclk() tiva_gpio_enableclk(9)
# define tiva_gpiol_enableclk() tiva_gpio_enableclk(10)
# define tiva_gpiom_enableclk() tiva_gpio_enableclk(11)
# define tiva_gpion_enableclk() tiva_gpio_enableclk(12)
# define tiva_gpiop_enableclk() tiva_gpio_enableclk(13)
# define tiva_gpioq_enableclk() tiva_gpio_enableclk(14)
# define tiva_gpior_enableclk() tiva_gpio_enableclk(15)
# define tiva_gpios_enableclk() tiva_gpio_enableclk(16)
# define tiva_gpiot_enableclk() tiva_gpio_enableclk(17)
# define tiva_gpioa_disableclk() tiva_gpio_disableclk(0)
# define tiva_gpiob_disableclk() tiva_gpio_disableclk(1)
# define tiva_gpioc_disableclk() tiva_gpio_disableclk(2)
# define tiva_gpiod_disableclk() tiva_gpio_disableclk(3)
# define tiva_gpioe_disableclk() tiva_gpio_disableclk(4)
# define tiva_gpiof_disableclk() tiva_gpio_disableclk(5)
# define tiva_gpiog_disableclk() tiva_gpio_disableclk(6)
# define tiva_gpioh_disableclk() tiva_gpio_disableclk(7)
# define tiva_gpioj_disableclk() tiva_gpio_disableclk(8)
# define tiva_gpiok_disableclk() tiva_gpio_disableclk(9)
# define tiva_gpiol_disableclk() tiva_gpio_disableclk(10)
# define tiva_gpiom_disableclk() tiva_gpio_disableclk(11)
# define tiva_gpion_disableclk() tiva_gpio_disableclk(12)
# define tiva_gpiop_disableclk() tiva_gpio_disableclk(13)
# define tiva_gpioq_disableclk() tiva_gpio_disableclk(14)
# define tiva_gpior_disableclk() tiva_gpio_disableclk(15)
# define tiva_gpios_disableclk() tiva_gpio_disableclk(16)
# define tiva_gpiot_disableclk() tiva_gpio_disableclk(17)
#else
# define tiva_gpio_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGC2,SYSCON_RCGC2_GPIO(p))
# define tiva_gpio_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGC2,SYSCON_RCGC2_GPIO(p))
# define tiva_gpioa_enableclk() tiva_gpio_enableclk(0)
# define tiva_gpiob_enableclk() tiva_gpio_enableclk(1)
# define tiva_gpioc_enableclk() tiva_gpio_enableclk(2)
# define tiva_gpiod_enableclk() tiva_gpio_enableclk(3)
# define tiva_gpioe_enableclk() tiva_gpio_enableclk(4)
# define tiva_gpiof_enableclk() tiva_gpio_enableclk(5)
# define tiva_gpiog_enableclk() tiva_gpio_enableclk(6)
# define tiva_gpioh_enableclk() tiva_gpio_enableclk(7)
# define tiva_gpioj_enableclk() tiva_gpio_enableclk(8)
# define tiva_gpiok_enableclk() tiva_gpio_enableclk(9)
# define tiva_gpiol_enableclk() tiva_gpio_enableclk(10)
# define tiva_gpiom_enableclk() tiva_gpio_enableclk(11)
# define tiva_gpion_enableclk() tiva_gpio_enableclk(12)
# define tiva_gpiop_enableclk() tiva_gpio_enableclk(13)
# define tiva_gpioq_enableclk() tiva_gpio_enableclk(14)
# define tiva_gpioa_disableclk() tiva_gpio_disableclk(0)
# define tiva_gpiob_disableclk() tiva_gpio_disableclk(1)
# define tiva_gpioc_disableclk() tiva_gpio_disableclk(2)
# define tiva_gpiod_disableclk() tiva_gpio_disableclk(3)
# define tiva_gpioe_disableclk() tiva_gpio_disableclk(4)
# define tiva_gpiof_disableclk() tiva_gpio_disableclk(5)
# define tiva_gpiog_disableclk() tiva_gpio_disableclk(6)
# define tiva_gpioh_disableclk() tiva_gpio_disableclk(7)
# define tiva_gpioj_disableclk() tiva_gpio_disableclk(8)
# define tiva_gpiok_disableclk() tiva_gpio_disableclk(9)
# define tiva_gpiol_disableclk() tiva_gpio_disableclk(10)
# define tiva_gpiom_disableclk() tiva_gpio_disableclk(11)
# define tiva_gpion_disableclk() tiva_gpio_disableclk(12)
# define tiva_gpiop_disableclk() tiva_gpio_disableclk(13)
# define tiva_gpioq_disableclk() tiva_gpio_disableclk(14)
#endif
/* μDMA Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCDMA
# define tiva_udma_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCDMA,SYSCON_RCGCDMA_R0)
# define tiva_udma_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCDMA,SYSCON_RCGCDMA_R0)
#else
#endif
/* EPI Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCEPI
# define tiva_epi_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCEPI,SYSCON_RCGCEPI_R0)
# define tiva_epi_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCEPI,SYSCON_RCGCEPI_R0)
#else
#endif
/* Hibernation Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCHIB
# define tiva_hib_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCHIB,SYSCON_RCGCHIB_R0)
# define tiva_hib_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCHIB,SYSCON_RCGCHIB_R0)
#else
#endif
/* UART Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCUART
# define tiva_uart_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCUART,SYSCON_RCGCUART(p))
# define tiva_uart_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCUART,SYSCON_RCGCUART(p))
# define tiva_uart0_enableclk() tiva_uart_enableclk(0)
# define tiva_uart1_enableclk() tiva_uart_enableclk(1)
# define tiva_uart2_enableclk() tiva_uart_enableclk(2)
# define tiva_uart3_enableclk() tiva_uart_enableclk(3)
# define tiva_uart4_enableclk() tiva_uart_enableclk(4)
# define tiva_uart5_enableclk() tiva_uart_enableclk(5)
# define tiva_uart6_enableclk() tiva_uart_enableclk(6)
# define tiva_uart7_enableclk() tiva_uart_enableclk(7)
# define tiva_uart0_disableclk() tiva_uart_disableclk(0)
# define tiva_uart1_disableclk() tiva_uart_disableclk(1)
# define tiva_uart2_disableclk() tiva_uart_disableclk(2)
# define tiva_uart3_disableclk() tiva_uart_disableclk(3)
# define tiva_uart4_disableclk() tiva_uart_disableclk(4)
# define tiva_uart5_disableclk() tiva_uart_disableclk(5)
# define tiva_uart6_disableclk() tiva_uart_disableclk(6)
# define tiva_uart7_disableclk() tiva_uart_disableclk(7)
#else
# define tiva_uart0_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART0)
# define tiva_uart1_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART1)
# define tiva_uart2_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART2)
# define tiva_uart0_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART0)
# define tiva_uart1_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART1)
# define tiva_uart2_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART2)
#endif
/* SSI Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCSSI
# define tiva_ssi_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCSSI,SYSCON_RCGCSSI(p))
# define tiva_ssi_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCSSI,SYSCON_RCGCSSI(p))
# define tiva_ssi0_enableclk() tiva_ssi_enableclk(0)
# define tiva_ssi1_enableclk() tiva_ssi_enableclk(1)
# define tiva_ssi2_enableclk() tiva_ssi_enableclk(2)
# define tiva_ssi3_enableclk() tiva_ssi_enableclk(3)
# define tiva_ssi0_disableclk() tiva_ssi_disableclk(0)
# define tiva_ssi1_disableclk() tiva_ssi_disableclk(1)
# define tiva_ssi2_disableclk() tiva_ssi_disableclk(2)
# define tiva_ssi3_disableclk() tiva_ssi_disableclk(3)
#else
# define tiva_ssi0_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI0)
# define tiva_ssi1_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI1)
# define tiva_ssi0_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI0)
# define tiva_ssi1_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI1)
#endif
/* I2C Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCI2C
# define tiva_i2c_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCI2C,SYSCON_RCGCI2C(p))
# define tiva_i2c_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCI2C,SYSCON_RCGCI2C(p))
# define tiva_i2c0_enableclk() tiva_i2c_enableclk(0)
# define tiva_i2c1_enableclk() tiva_i2c_enableclk(1)
# define tiva_i2c2_enableclk() tiva_i2c_enableclk(2)
# define tiva_i2c3_enableclk() tiva_i2c_enableclk(3)
# define tiva_i2c4_enableclk() tiva_i2c_enableclk(4)
# define tiva_i2c5_enableclk() tiva_i2c_enableclk(5)
# define tiva_i2c6_enableclk() tiva_i2c_enableclk(6)
# define tiva_i2c7_enableclk() tiva_i2c_enableclk(7)
# define tiva_i2c8_enableclk() tiva_i2c_enableclk(8)
# define tiva_i2c9_enableclk() tiva_i2c_enableclk(9)
# define tiva_i2c0_disableclk() tiva_i2c_disableclk(0)
# define tiva_i2c1_disableclk() tiva_i2c_disableclk(1)
# define tiva_i2c2_disableclk() tiva_i2c_disableclk(2)
# define tiva_i2c3_disableclk() tiva_i2c_disableclk(3)
# define tiva_i2c4_disableclk() tiva_i2c_disableclk(4)
# define tiva_i2c5_disableclk() tiva_i2c_disableclk(5)
# define tiva_i2c6_disableclk() tiva_i2c_disableclk(6)
# define tiva_i2c7_disableclk() tiva_i2c_disableclk(7)
# define tiva_i2c8_disableclk() tiva_i2c_disableclk(8)
# define tiva_i2c9_disableclk() tiva_i2c_disableclk(9)
#else
#endif
/* USB Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCUSB
# define tiva_usb_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCUSB,SYSCON_RCGCUSB_R0)
# define tiva_usb_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCUSB,SYSCON_RCGCUSB_R0)
#else
#endif
/* Ethernet PHY Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCEPHY
# define tiva_ephy_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCEPHY,SYSCON_RCGCEPHY_R0)
# define tiva_ephy_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCEPHY,SYSCON_RCGCEPHY_R0)
#else
#endif
/* CAN RunMode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCCAN
# define tiva_can_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCCAN,SYSCON_RCGCCAN(p))
# define tiva_can_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCCAN,SYSCON_RCGCCAN(p))
# define tiva_can0_enableclk() tiva_can_enableclk(0)
# define tiva_can1_enableclk() tiva_can_enableclk(1)
# define tiva_can0_disableclk() tiva_can_disableclk(0)
# define tiva_can1_disableclk() tiva_can_disableclk(1)
#else
#endif
/* ADC Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCADC
# define tiva_adc_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCADC,SYSCON_RCGCADC(p))
# define tiva_adc_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCADC,SYSCON_RCGCADC(p))
# define tiva_adc0_enableclk() tiva_adc_enableclk(0)
# define tiva_adc1_enableclk() tiva_adc_enableclk(1)
# define tiva_adc0_disableclk() tiva_adc_disableclk(0)
# define tiva_adc1_disableclk() tiva_adc_disableclk(1)
#else
#endif
/* ACMP Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCACMP
# define tiva_acmp_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCACMP,SYSCON_RCGCACMP_R0)
# define tiva_acmp_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCACMP,SYSCON_RCGCACMP_R0)
#else
#endif
/* PWM Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCPWM
# define tiva_pwm_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCPWM,SYSCON_RCGCPWM(p))
# define tiva_pwm_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCPWM,SYSCON_RCGCPWM(p))
# define tiva_pwm0_enableclk() tiva_pwm_enableclk(0)
# define tiva_pwm1_enableclk() tiva_pwm_enableclk(1)
# define tiva_pwm0_disableclk() tiva_pwm_disableclk(0)
# define tiva_pwm1_disableclk() tiva_pwm_disableclk(1)
#else
#endif
/* QE Interface Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCQEI
# define tiva_qei_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCQEI,SYSCON_RCGCQEI(p))
# define tiva_qei_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCQEI,SYSCON_RCGCQEI(p))
# define tiva_qei0_enableclk() tiva_qei_enableclk(0)
# define tiva_qei1_enableclk() tiva_qei_enableclk(1)
# define tiva_qei0_disableclk() tiva_qei_disableclk(0)
# define tiva_qei1_disableclk() tiva_qei_disableclk(1)
#else
#endif
/* EEPROM Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCEEPROM
# define tiva_eeprom_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCEEPROM,SYSCON_RCGCEEPROM_R0)
# define tiva_eeprom_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCEEPROM,SYSCON_RCGCEEPROM_R0)
#else
#endif
/* 32/64-Bit Wide Timer Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCWTIMER
# define tiva_wtm_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCWTIMER,SYSCON_RCGCWTIMER(p))
# define tiva_wtm_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCWTIMER,SYSCON_RCGCWTIMER(p))
# define tiva_wtm0_enableclk() tiva_wtm_enableclk(0)
# define tiva_wtm1_enableclk() tiva_wtm_enableclk(1)
# define tiva_wtm2_enableclk() tiva_wtm_enableclk(2)
# define tiva_wtm3_enableclk() tiva_wtm_enableclk(3)
# define tiva_wtm4_enableclk() tiva_wtm_enableclk(4)
# define tiva_wtm5_enableclk() tiva_wtm_enableclk(5)
# define tiva_wtm0_disableclk() tiva_wtm_disableclk(0)
# define tiva_wtm1_disableclk() tiva_wtm_disableclk(1)
# define tiva_wtm2_disableclk() tiva_wtm_disableclk(2)
# define tiva_wtm3_disableclk() tiva_wtm_disableclk(3)
# define tiva_wtm4_disableclk() tiva_wtm_disableclk(4)
# define tiva_wtm5_disableclk() tiva_wtm_disableclk(5)
#else
#endif
/* CRC/Crypto Modules RunMode ClockGating Control */
#ifdef TIVA_SYSCON_RCGCCCM
# define tiva_ccm_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCCCM,SYSCON_RCGCCCM_R0)
# define tiva_ccm_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCCCM,SYSCON_RCGCCCM_R0)
#else
#endif
/* LCD Controller Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCLCD
# define tiva_lcd_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCLCD,SYSCON_RCGCLCD_R0)
# define tiva_lcd_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCLCD,SYSCON_RCGCLCD_R0)
#else
#endif
/* 1-Wire Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCOWIRE
# define tiva_owire_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCOWIRE,SYSCON_RCGCOWIRE_R0)
# define tiva_owire_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCOWIRE,SYSCON_RCGCOWIRE_R0)
#else
#endif
/* Ethernet MAC Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCEMAC
# define tiva_emac_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCEMAC,SYSCON_RCGCEMAC_R0)
# define tiva_emac_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCEMAC,SYSCON_RCGCEMAC_R0)
#else
#endif
#endif /* __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLECLKS_H */

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/************************************************************************************
* arch/arm/src/tiva/common/lmxx_tm4c_enablepwr.h
*
* Copyright (C) 2014, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLEPWR_H
#define __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLEPWR_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "chip.h"
#include "hardware/tiva_sysctrl.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Power control is enabled or disabled by setting or clearing a bit (b) in a system
* control register (a))
*/
#define tiva_enablepwr(a, b) modifyreg32((a), 0, (b))
#define tiva_disablepwr(a, b) modifyreg32((a), (b), 0)
/* Watchdog Timer Power Control */
#ifdef TIVA_SYSCON_PCWD
# define tiva_wdt_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCWD, SYSCON_PCWD(p))
# define tiva_wdt_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCWD, SYSCON_PCWD(p))
#else
# define tiva_wdt_enablepwr(p)
# define tiva_wdt_disablepwr(p)
#endif
#define tiva_wdt0_enablepwr() tiva_wdt_enablepwr(0)
#define tiva_wdt1_enablepwr() tiva_wdt_enablepwr(1)
#define tiva_wdt0_disablepwr() tiva_wdt_disablepwr(0)
#define tiva_wdt1_disablepwr() tiva_wdt_disablepwr(1)
/* 16/32-Bit Timer Power Control */
#ifdef TIVA_SYSCON_PCTIMER
# define tiva_gptm_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCTIMER, SYSCON_PCTIMER(p))
# define tiva_gptm_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCTIMER, SYSCON_PCTIMER(p))
#else
# define tiva_gptm_enablepwr(p)
# define tiva_gptm_disablepwr(p)
#endif
#define tiva_gptm0_enablepwr() tiva_gptm_enablepwr(0)
#define tiva_gptm1_enablepwr() tiva_gptm_enablepwr(1)
#define tiva_gptm2_enablepwr() tiva_gptm_enablepwr(2)
#define tiva_gptm3_enablepwr() tiva_gptm_enablepwr(3)
#define tiva_gptm4_enablepwr() tiva_gptm_enablepwr(4)
#define tiva_gptm5_enablepwr() tiva_gptm_enablepwr(5)
#define tiva_gptm6_enablepwr() tiva_gptm_enablepwr(6)
#define tiva_gptm7_enablepwr() tiva_gptm_enablepwr(7)
#define tiva_gptm0_disablepwr() tiva_gptm_disablepwr(0)
#define tiva_gptm1_disablepwr() tiva_gptm_disablepwr(1)
#define tiva_gptm2_disablepwr() tiva_gptm_disablepwr(2)
#define tiva_gptm3_disablepwr() tiva_gptm_disablepwr(3)
#define tiva_gptm4_disablepwr() tiva_gptm_disablepwr(4)
#define tiva_gptm5_disablepwr() tiva_gptm_disablepwr(5)
#define tiva_gptm6_disablepwr() tiva_gptm_disablepwr(6)
#define tiva_gptm7_disablepwr() tiva_gptm_disablepwr(7)
/* GPIO Power Control */
#ifdef TIVA_SYSCON_PCGPIO
# define tiva_gpio_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCGPIO, SYSCON_PCGPIO(p))
# define tiva_gpio_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCGPIO, SYSCON_PCGPIO(p))
#else
# define tiva_gpio_enablepwr(p)
# define tiva_gpio_disablepwr(p)
#endif
#define tiva_gpioa_enablepwr() tiva_gpio_enablepwr(0)
#define tiva_gpiob_enablepwr() tiva_gpio_enablepwr(1)
#define tiva_gpioc_enablepwr() tiva_gpio_enablepwr(2)
#define tiva_gpiod_enablepwr() tiva_gpio_enablepwr(3)
#define tiva_gpioe_enablepwr() tiva_gpio_enablepwr(4)
#define tiva_gpiof_enablepwr() tiva_gpio_enablepwr(5)
#define tiva_gpiog_enablepwr() tiva_gpio_enablepwr(6)
#define tiva_gpioh_enablepwr() tiva_gpio_enablepwr(7)
#define tiva_gpioj_enablepwr() tiva_gpio_enablepwr(8)
#define tiva_gpiok_enablepwr() tiva_gpio_enablepwr(9)
#define tiva_gpiol_enablepwr() tiva_gpio_enablepwr(10)
#define tiva_gpiom_enablepwr() tiva_gpio_enablepwr(11)
#define tiva_gpion_enablepwr() tiva_gpio_enablepwr(12)
#define tiva_gpiop_enablepwr() tiva_gpio_enablepwr(13)
#define tiva_gpioq_enablepwr() tiva_gpio_enablepwr(14)
#define tiva_gpior_enablepwr() tiva_gpio_enablepwr(15)
#define tiva_gpios_enablepwr() tiva_gpio_enablepwr(16)
#define tiva_gpiot_enablepwr() tiva_gpio_enablepwr(17)
#define tiva_gpioa_disablepwr() tiva_gpio_disablepwr(0)
#define tiva_gpiob_disablepwr() tiva_gpio_disablepwr(1)
#define tiva_gpioc_disablepwr() tiva_gpio_disablepwr(2)
#define tiva_gpiod_disablepwr() tiva_gpio_disablepwr(3)
#define tiva_gpioe_disablepwr() tiva_gpio_disablepwr(4)
#define tiva_gpiof_disablepwr() tiva_gpio_disablepwr(5)
#define tiva_gpiog_disablepwr() tiva_gpio_disablepwr(6)
#define tiva_gpioh_disablepwr() tiva_gpio_disablepwr(7)
#define tiva_gpioj_disablepwr() tiva_gpio_disablepwr(8)
#define tiva_gpiok_disablepwr() tiva_gpio_disablepwr(9)
#define tiva_gpiol_disablepwr() tiva_gpio_disablepwr(10)
#define tiva_gpiom_disablepwr() tiva_gpio_disablepwr(11)
#define tiva_gpion_disablepwr() tiva_gpio_disablepwr(12)
#define tiva_gpiop_disablepwr() tiva_gpio_disablepwr(13)
#define tiva_gpioq_disablepwr() tiva_gpio_disablepwr(14)
#define tiva_gpior_disablepwr() tiva_gpio_disablepwr(15)
#define tiva_gpios_disablepwr() tiva_gpio_disablepwr(16)
#define tiva_gpiot_disablepwr() tiva_gpio_disablepwr(17)
/* μDMA Power Control */
#ifdef TIVA_SYSCON_PCDMA
# define tiva_udma_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCDMA, SYSCON_PCDMA_P0)
# define tiva_udma_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCDMA, SYSCON_PCDMA_P0)
#else
# define tiva_udma_enablepwr()
# define tiva_udma_disablepwr()
#endif
/* EPI Power Control */
#ifdef TIVA_SYSCON_PCEPI
# define tiva_epi_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEPI, SYSCON_PCEPI_P0)
# define tiva_epi_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEPI, SYSCON_PCEPI_P0)
#else
# define tiva_epi_enablepwr()
# define tiva_epi_disablepwr()
#endif
/* Hibernation Power Control */
#ifdef TIVA_SYSCON_PCHIB
# define tiva_hib_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCHIB, SYSCON_PCHIB_P0)
# define tiva_hib_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCHIB, SYSCON_PCHIB_P0)
#else
# define tiva_hib_enablepwr()
# define tiva_hib_disablepwr()
#endif
/* UART Power Control */
#ifdef TIVA_SYSCON_PCUART
# define tiva_uart_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCUART, SYSCON_PCUART(p))
# define tiva_uart_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCUART, SYSCON_PCUART(p))
#else
# define tiva_uart_enablepwr(p)
# define tiva_uart_disablepwr(p)
#endif
#define tiva_uart0_enablepwr() tiva_uart_enablepwr(0)
#define tiva_uart1_enablepwr() tiva_uart_enablepwr(1)
#define tiva_uart2_enablepwr() tiva_uart_enablepwr(2)
#define tiva_uart3_enablepwr() tiva_uart_enablepwr(3)
#define tiva_uart4_enablepwr() tiva_uart_enablepwr(4)
#define tiva_uart5_enablepwr() tiva_uart_enablepwr(5)
#define tiva_uart6_enablepwr() tiva_uart_enablepwr(6)
#define tiva_uart7_enablepwr() tiva_uart_enablepwr(7)
#define tiva_uart0_disablepwr() tiva_uart_disablepwr(0)
#define tiva_uart1_disablepwr() tiva_uart_disablepwr(1)
#define tiva_uart2_disablepwr() tiva_uart_disablepwr(2)
#define tiva_uart3_disablepwr() tiva_uart_disablepwr(3)
#define tiva_uart4_disablepwr() tiva_uart_disablepwr(4)
#define tiva_uart5_disablepwr() tiva_uart_disablepwr(5)
#define tiva_uart6_disablepwr() tiva_uart_disablepwr(6)
#define tiva_uart7_disablepwr() tiva_uart_disablepwr(7)
/* SSI Power Control */
#ifdef TIVA_SYSCON_PCSSI
# define tiva_ssi_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCSSI, SYSCON_PCSSI(p))
# define tiva_ssi_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCSSI, SYSCON_PCSSI(p))
#else
# define tiva_ssi_enablepwr(p)
# define tiva_ssi_disablepwr(p)
#endif
#define tiva_ssi0_enablepwr() tiva_ssi_enablepwr(0)
#define tiva_ssi1_enablepwr() tiva_ssi_enablepwr(1)
#define tiva_ssi2_enablepwr() tiva_ssi_enablepwr(2)
#define tiva_ssi3_enablepwr() tiva_ssi_enablepwr(3)
#define tiva_ssi0_disablepwr() tiva_ssi_disablepwr(0)
#define tiva_ssi1_disablepwr() tiva_ssi_disablepwr(1)
#define tiva_ssi2_disablepwr() tiva_ssi_disablepwr(2)
#define tiva_ssi3_disablepwr() tiva_ssi_disablepwr(3)
/* I2C Power Control */
#ifdef TIVA_SYSCON_PCI2C
# define tiva_i2c_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCI2C, SYSCON_PCI2C(p))
# define tiva_i2c_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCI2C, SYSCON_PCI2C(p))
#else
# define tiva_i2c_enablepwr(p)
# define tiva_i2c_disablepwr(p)
#endif
#define tiva_i2c0_enablepwr() tiva_i2c_enablepwr(0)
#define tiva_i2c1_enablepwr() tiva_i2c_enablepwr(1)
#define tiva_i2c2_enablepwr() tiva_i2c_enablepwr(2)
#define tiva_i2c3_enablepwr() tiva_i2c_enablepwr(3)
#define tiva_i2c4_enablepwr() tiva_i2c_enablepwr(4)
#define tiva_i2c5_enablepwr() tiva_i2c_enablepwr(5)
#define tiva_i2c6_enablepwr() tiva_i2c_enablepwr(6)
#define tiva_i2c7_enablepwr() tiva_i2c_enablepwr(7)
#define tiva_i2c8_enablepwr() tiva_i2c_enablepwr(8)
#define tiva_i2c9_enablepwr() tiva_i2c_enablepwr(9)
#define tiva_i2c0_disablepwr() tiva_i2c_disablepwr(0)
#define tiva_i2c1_disablepwr() tiva_i2c_disablepwr(1)
#define tiva_i2c2_disablepwr() tiva_i2c_disablepwr(2)
#define tiva_i2c3_disablepwr() tiva_i2c_disablepwr(3)
#define tiva_i2c4_disablepwr() tiva_i2c_disablepwr(4)
#define tiva_i2c5_disablepwr() tiva_i2c_disablepwr(5)
#define tiva_i2c6_disablepwr() tiva_i2c_disablepwr(6)
#define tiva_i2c7_disablepwr() tiva_i2c_disablepwr(7)
#define tiva_i2c8_disablepwr() tiva_i2c_disablepwr(8)
#define tiva_i2c9_disablepwr() tiva_i2c_disablepwr(9)
/* USB Power Control */
#ifdef TIVA_SYSCON_PCUSB
# define tiva_usb_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCUSB, SYSCON_PCUSB_P0)
# define tiva_usb_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCUSB, SYSCON_PCUSB_P0)
#else
# define tiva_usb_enablepwr()
# define tiva_usb_disablepwr()
#endif
/* Ethernet PHY Power Control */
#ifdef TIVA_SYSCON_PCEPHY
# define tiva_ephy_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEPHY, SYSCON_PCEPHY_P0)
# define tiva_ephy_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEPHY, SYSCON_PCEPHY_P0)
#else
# define tiva_ephy_enablepwr()
# define tiva_ephy_disablepwr()
#endif
/* CAN RunMode Clock Gating Control */
#ifdef TIVA_SYSCON_PCCAN
# define tiva_can_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCCAN, SYSCON_PCCAN(p))
# define tiva_can_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCCAN, SYSCON_PCCAN(p))
#else
# define tiva_can_enablepwr(p)
# define tiva_can_disablepwr(p)
#endif
#define tiva_can0_enablepwr() tiva_can_enablepwr(0)
#define tiva_can1_enablepwr() tiva_can_enablepwr(1)
#define tiva_can0_disablepwr() tiva_can_disablepwr(0)
#define tiva_can1_disablepwr() tiva_can_disablepwr(1)
/* ADC Power Control */
#ifdef TIVA_SYSCON_PCADC
# define tiva_adc_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCADC, SYSCON_PCADC(p))
# define tiva_adc_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCADC, SYSCON_PCADC(p))
#else
# define tiva_adc_enablepwr(p)
# define tiva_adc_disablepwr(p)
#endif
#define tiva_adc0_enablepwr() tiva_adc_enablepwr(0)
#define tiva_adc1_enablepwr() tiva_adc_enablepwr(1)
#define tiva_adc0_disablepwr() tiva_adc_disablepwr(0)
#define tiva_adc1_disablepwr() tiva_adc_disablepwr(1)
/* ACMP Power Control */
#ifdef TIVA_SYSCON_PCACMP
# define tiva_acmp_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCACMP, SYSCON_PCACMP_P0)
# define tiva_acmp_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCACMP, SYSCON_PCACMP_P0)
#else
# define tiva_acmp_enablepwr()
# define tiva_acmp_disablepwr()
#endif
/* PWM Power Control */
#ifdef TIVA_SYSCON_PCPWM
# define tiva_pwm_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCPWM, SYSCON_PCPWM(p))
# define tiva_pwm_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCPWM, SYSCON_PCPWM(p))
#else
# define tiva_pwm_enablepwr(p)
# define tiva_pwm_disablepwr(p)
#endif
#define tiva_pwm0_enablepwr() tiva_pwm_enablepwr(0)
#define tiva_pwm1_enablepwr() tiva_pwm_enablepwr(1)
#define tiva_pwm0_disablepwr() tiva_pwm_disablepwr(0)
#define tiva_pwm1_disablepwr() tiva_pwm_disablepwr(1)
/* QE Interface Power Control */
#ifdef TIVA_SYSCON_PCQEI
# define tiva_qei_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCQEI, SYSCON_PCQEI(p))
# define tiva_qei_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCQEI, SYSCON_PCQEI(p))
#else
# define tiva_qei_enablepwr(p)
# define tiva_qei_disablepwr(p)
#endif
#define tiva_qei0_enablepwr() tiva_qei_enablepwr(0)
#define tiva_qei1_enablepwr() tiva_qei_enablepwr(1)
#define tiva_qei0_disablepwr() tiva_qei_disablepwr(0)
#define tiva_qei1_disablepwr() tiva_qei_disablepwr(1)
/* EEPROM Power Control */
#ifdef TIVA_SYSCON_PCEEPROM
# define tiva_eeprom_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEEPROM, SYSCON_PCEEPROM_P0)
# define tiva_eeprom_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEEPROM, SYSCON_PCEEPROM_P0)
#else
# define tiva_eeprom_enablepwr()
# define tiva_eeprom_disablepwr()
#endif
/* 32/64-Bit Wide Timer Power Control */
#ifdef TIVA_SYSCON_PCWTIMER
# define tiva_wtm_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCWTIMER, SYSCON_PCWTIMER(p))
# define tiva_wtm_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCWTIMER, SYSCON_PCWTIMER(p))
#else
# define tiva_wtm_enablepwr(p)
# define tiva_wtm_disablepwr(p)
#endif
#define tiva_wtm0_enablepwr() tiva_wtm_enablepwr(0)
#define tiva_wtm1_enablepwr() tiva_wtm_enablepwr(1)
#define tiva_wtm2_enablepwr() tiva_wtm_enablepwr(2)
#define tiva_wtm3_enablepwr() tiva_wtm_enablepwr(3)
#define tiva_wtm4_enablepwr() tiva_wtm_enablepwr(4)
#define tiva_wtm5_enablepwr() tiva_wtm_enablepwr(5)
#define tiva_wtm0_disablepwr() tiva_wtm_disablepwr(0)
#define tiva_wtm1_disablepwr() tiva_wtm_disablepwr(1)
#define tiva_wtm2_disablepwr() tiva_wtm_disablepwr(2)
#define tiva_wtm3_disablepwr() tiva_wtm_disablepwr(3)
#define tiva_wtm4_disablepwr() tiva_wtm_disablepwr(4)
#define tiva_wtm5_disablepwr() tiva_wtm_disablepwr(5)
/* CRC/Crypto Modules RunMode ClockGating Control */
#ifdef TIVA_SYSCON_PCCCM
# define tiva_ccm_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCCCM, SYSCON_PCCCM_P0)
# define tiva_ccm_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCCCM, SYSCON_PCCCM_P0)
#else
# define tiva_ccm_enablepwr()
# define tiva_ccm_disablepwr()
#endif
/* LCD Controller Power Control */
#ifdef TIVA_SYSCON_PCLCD
# define tiva_lcd_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCLCD, SYSCON_PCLCD_P0)
# define tiva_lcd_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCLCD, SYSCON_PCLCD_P0)
#else
# define tiva_lcd_enablepwr()
# define tiva_lcd_disablepwr()
#endif
/* 1-Wire Power Control */
#ifdef TIVA_SYSCON_PCOWIRE
# define tiva_owire_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCOWIRE, SYSCON_PCOWIRE_P0)
# define tiva_owire_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCOWIRE, SYSCON_PCOWIRE_P0)
#else
# define tiva_owire_enablepwr()
# define tiva_owire_disablepwr()
#endif
/* Ethernet MAC Power Control */
#ifdef TIVA_SYSCON_PCEMAC
# define tiva_emac_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEMAC, SYSCON_PCEMAC_P0)
# define tiva_emac_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEMAC, SYSCON_PCEMAC_P0)
#else
# define tiva_emac_enablepwr()
# define tiva_emac_disablepwr()
#endif
#endif /* __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLEPWR_H */

3
arch/arm/src/tiva/common/tiva_start.c → arch/arm/src/tiva/common/lmxx_tm4c_start.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/tiva/common/tiva_start.c
* arch/arm/src/tiva/common/lmxx_tm4c_start.c
*
* Copyright (C) 2009, 2012, 2014, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -44,6 +44,7 @@
#include <debug.h>
#include <nuttx/init.h>
#include <arch/irq.h>
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"

20
arch/arm/src/tiva/common/tiva_lowputc.c
View File

@ -203,26 +203,6 @@
* Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
*/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

1
arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h
View File

@ -336,7 +336,6 @@
#define PRCM_I2SWCLKDIV_WDIV_SHIFT (0) /* Bits 0-9: MCLK divider */
#define PRCM_I2SWCLKDIV_WDIV_MASK (0x3ff << PRCM_I2SWCLKDIV_WDIV_SHIFT)
# define PRCM_I2SWCLKDIV_WDIV(n) ((uint32_t)(n) << PRCM_I2SWCLKDIV_WDIV_SHIFT)
# define PRCM_I2SWCLKDIV_WDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SWCLKDIV_WDIV_SHIFT)
/* SW Initiated Resets */

1
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h
View File

@ -41,6 +41,7 @@
************************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************
* Pre-processor Definitions

2
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h
View File

@ -44,7 +44,7 @@
************************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************
* Pre-processor Definitions

3
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_prcm.h
View File

@ -41,6 +41,7 @@
****************************************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/****************************************************************************************************
* Pre-processor Definitions
@ -429,7 +430,6 @@
#define PRCM_I2SBCLKDIV_BDIV_SHIFT (0) /* Bits 0-9: MCLK divider */
#define PRCM_I2SBCLKDIV_BDIV_MASK (0x3ff << PRCM_I2SBCLKDIV_BDIV_SHIFT)
# define PRCM_I2SBCLKDIV_BDIV(n) ((uint32_t)(n) << PRCM_I2SBCLKDIV_BDIV_SHIFT)
# define PRCM_I2SBCLKDIV_BDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SBCLKDIV_BDIV_SHIFT)
/* WCLK Division Ratio */
@ -437,7 +437,6 @@
#define PRCM_I2SWCLKDIV_WDIV_SHIFT (0) /* Bits 0-9: MCLK divider */
#define PRCM_I2SWCLKDIV_WDIV_MASK (0x3ff << PRCM_I2SWCLKDIV_WDIV_SHIFT)
# define PRCM_I2SWCLKDIV_WDIV(n) ((uint32_t)(n) << PRCM_I2SWCLKDIV_WDIV_SHIFT)
# define PRCM_I2SWCLKDIV_WDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SWCLKDIV_WDIV_SHIFT)
/* RESET For SEC (PKA And TRNG And CRYPTO) And UDMA */

1
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_timer.h
View File

@ -41,6 +41,7 @@
************************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************
* Pre-processor Definitions

2
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h
View File

@ -41,7 +41,7 @@
************************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************
* Pre-processor Definitions

73
arch/arm/src/tiva/hardware/tiva_prcm.h Normal file
View File

@ -0,0 +1,73 @@
/************************************************************************************
* arch/arm/src/tiva/hardware/tiva_prcm.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PRCM_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PRCM_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */
#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
/* These architectures do not support the PRCM block */
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
# include "hardware/cc13x0/cc13x0_prcm.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_prcm.h"
#else
# error "Unsupported Tiva/Stellaris/SimpleLink PRCM"
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PRCM_H */

391
arch/arm/src/tiva/tiva_enableclks.h
View File

@ -42,392 +42,15 @@
#include <nuttx/config.h>
#include "up_arch.h"
#include "chip.h"
#include "hardware/tiva_sysctrl.h"
/* Include chip specific definitions */
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Clocks are enabled or disabled by setting or clearing a bit (b) in a system
* control register (a))
*/
#define tiva_enableclk(a,b) modifyreg32((a),0,(b))
#define tiva_disableclk(a,b) modifyreg32((a),(b),0)
/* Watchdog Timer Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCWD
# define tiva_wdt_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCWD,SYSCON_RCGCWD(p))
# define tiva_wdt_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCWD,SYSCON_RCGCWD(p))
# define tiva_wdt0_enableclk() tiva_wdt_enableclk(0)
# define tiva_wdt1_enableclk() tiva_wdt_enableclk(1)
# define tiva_wdt0_disableclk() tiva_wdt_disableclk(0)
# define tiva_wdt1_disableclk() tiva_wdt_disableclk(1)
#else
#endif
/* 16/32-Bit Timer Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCTIMER
# define tiva_gptm_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCTIMER,SYSCON_RCGCTIMER(p))
# define tiva_gptm_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCTIMER,SYSCON_RCGCTIMER(p))
# define tiva_gptm0_enableclk() tiva_gptm_enableclk(0)
# define tiva_gptm1_enableclk() tiva_gptm_enableclk(1)
# define tiva_gptm2_enableclk() tiva_gptm_enableclk(2)
# define tiva_gptm3_enableclk() tiva_gptm_enableclk(3)
# define tiva_gptm4_enableclk() tiva_gptm_enableclk(4)
# define tiva_gptm5_enableclk() tiva_gptm_enableclk(5)
# define tiva_gptm6_enableclk() tiva_gptm_enableclk(6)
# define tiva_gptm7_enableclk() tiva_gptm_enableclk(7)
# define tiva_gptm0_disableclk() tiva_gptm_disableclk(0)
# define tiva_gptm1_disableclk() tiva_gptm_disableclk(1)
# define tiva_gptm2_disableclk() tiva_gptm_disableclk(2)
# define tiva_gptm3_disableclk() tiva_gptm_disableclk(3)
# define tiva_gptm4_disableclk() tiva_gptm_disableclk(4)
# define tiva_gptm5_disableclk() tiva_gptm_disableclk(5)
# define tiva_gptm6_disableclk() tiva_gptm_disableclk(6)
# define tiva_gptm7_disableclk() tiva_gptm_disableclk(7)
#else
#endif
/* GPIO Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCGPIO
# define tiva_gpio_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCGPIO,SYSCON_RCGCGPIO(p))
# define tiva_gpio_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCGPIO,SYSCON_RCGCGPIO(p))
# define tiva_gpioa_enableclk() tiva_gpio_enableclk(0)
# define tiva_gpiob_enableclk() tiva_gpio_enableclk(1)
# define tiva_gpioc_enableclk() tiva_gpio_enableclk(2)
# define tiva_gpiod_enableclk() tiva_gpio_enableclk(3)
# define tiva_gpioe_enableclk() tiva_gpio_enableclk(4)
# define tiva_gpiof_enableclk() tiva_gpio_enableclk(5)
# define tiva_gpiog_enableclk() tiva_gpio_enableclk(6)
# define tiva_gpioh_enableclk() tiva_gpio_enableclk(7)
# define tiva_gpioj_enableclk() tiva_gpio_enableclk(8)
# define tiva_gpiok_enableclk() tiva_gpio_enableclk(9)
# define tiva_gpiol_enableclk() tiva_gpio_enableclk(10)
# define tiva_gpiom_enableclk() tiva_gpio_enableclk(11)
# define tiva_gpion_enableclk() tiva_gpio_enableclk(12)
# define tiva_gpiop_enableclk() tiva_gpio_enableclk(13)
# define tiva_gpioq_enableclk() tiva_gpio_enableclk(14)
# define tiva_gpior_enableclk() tiva_gpio_enableclk(15)
# define tiva_gpios_enableclk() tiva_gpio_enableclk(16)
# define tiva_gpiot_enableclk() tiva_gpio_enableclk(17)
# define tiva_gpioa_disableclk() tiva_gpio_disableclk(0)
# define tiva_gpiob_disableclk() tiva_gpio_disableclk(1)
# define tiva_gpioc_disableclk() tiva_gpio_disableclk(2)
# define tiva_gpiod_disableclk() tiva_gpio_disableclk(3)
# define tiva_gpioe_disableclk() tiva_gpio_disableclk(4)
# define tiva_gpiof_disableclk() tiva_gpio_disableclk(5)
# define tiva_gpiog_disableclk() tiva_gpio_disableclk(6)
# define tiva_gpioh_disableclk() tiva_gpio_disableclk(7)
# define tiva_gpioj_disableclk() tiva_gpio_disableclk(8)
# define tiva_gpiok_disableclk() tiva_gpio_disableclk(9)
# define tiva_gpiol_disableclk() tiva_gpio_disableclk(10)
# define tiva_gpiom_disableclk() tiva_gpio_disableclk(11)
# define tiva_gpion_disableclk() tiva_gpio_disableclk(12)
# define tiva_gpiop_disableclk() tiva_gpio_disableclk(13)
# define tiva_gpioq_disableclk() tiva_gpio_disableclk(14)
# define tiva_gpior_disableclk() tiva_gpio_disableclk(15)
# define tiva_gpios_disableclk() tiva_gpio_disableclk(16)
# define tiva_gpiot_disableclk() tiva_gpio_disableclk(17)
#else
# define tiva_gpio_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGC2,SYSCON_RCGC2_GPIO(p))
# define tiva_gpio_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGC2,SYSCON_RCGC2_GPIO(p))
# define tiva_gpioa_enableclk() tiva_gpio_enableclk(0)
# define tiva_gpiob_enableclk() tiva_gpio_enableclk(1)
# define tiva_gpioc_enableclk() tiva_gpio_enableclk(2)
# define tiva_gpiod_enableclk() tiva_gpio_enableclk(3)
# define tiva_gpioe_enableclk() tiva_gpio_enableclk(4)
# define tiva_gpiof_enableclk() tiva_gpio_enableclk(5)
# define tiva_gpiog_enableclk() tiva_gpio_enableclk(6)
# define tiva_gpioh_enableclk() tiva_gpio_enableclk(7)
# define tiva_gpioj_enableclk() tiva_gpio_enableclk(8)
# define tiva_gpiok_enableclk() tiva_gpio_enableclk(9)
# define tiva_gpiol_enableclk() tiva_gpio_enableclk(10)
# define tiva_gpiom_enableclk() tiva_gpio_enableclk(11)
# define tiva_gpion_enableclk() tiva_gpio_enableclk(12)
# define tiva_gpiop_enableclk() tiva_gpio_enableclk(13)
# define tiva_gpioq_enableclk() tiva_gpio_enableclk(14)
# define tiva_gpioa_disableclk() tiva_gpio_disableclk(0)
# define tiva_gpiob_disableclk() tiva_gpio_disableclk(1)
# define tiva_gpioc_disableclk() tiva_gpio_disableclk(2)
# define tiva_gpiod_disableclk() tiva_gpio_disableclk(3)
# define tiva_gpioe_disableclk() tiva_gpio_disableclk(4)
# define tiva_gpiof_disableclk() tiva_gpio_disableclk(5)
# define tiva_gpiog_disableclk() tiva_gpio_disableclk(6)
# define tiva_gpioh_disableclk() tiva_gpio_disableclk(7)
# define tiva_gpioj_disableclk() tiva_gpio_disableclk(8)
# define tiva_gpiok_disableclk() tiva_gpio_disableclk(9)
# define tiva_gpiol_disableclk() tiva_gpio_disableclk(10)
# define tiva_gpiom_disableclk() tiva_gpio_disableclk(11)
# define tiva_gpion_disableclk() tiva_gpio_disableclk(12)
# define tiva_gpiop_disableclk() tiva_gpio_disableclk(13)
# define tiva_gpioq_disableclk() tiva_gpio_disableclk(14)
#endif
/* μDMA Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCDMA
# define tiva_udma_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCDMA,SYSCON_RCGCDMA_R0)
# define tiva_udma_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCDMA,SYSCON_RCGCDMA_R0)
#else
#endif
/* EPI Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCEPI
# define tiva_epi_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCEPI,SYSCON_RCGCEPI_R0)
# define tiva_epi_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCEPI,SYSCON_RCGCEPI_R0)
#else
#endif
/* Hibernation Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCHIB
# define tiva_hib_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCHIB,SYSCON_RCGCHIB_R0)
# define tiva_hib_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCHIB,SYSCON_RCGCHIB_R0)
#else
#endif
/* UART Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCUART
# define tiva_uart_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCUART,SYSCON_RCGCUART(p))
# define tiva_uart_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCUART,SYSCON_RCGCUART(p))
# define tiva_uart0_enableclk() tiva_uart_enableclk(0)
# define tiva_uart1_enableclk() tiva_uart_enableclk(1)
# define tiva_uart2_enableclk() tiva_uart_enableclk(2)
# define tiva_uart3_enableclk() tiva_uart_enableclk(3)
# define tiva_uart4_enableclk() tiva_uart_enableclk(4)
# define tiva_uart5_enableclk() tiva_uart_enableclk(5)
# define tiva_uart6_enableclk() tiva_uart_enableclk(6)
# define tiva_uart7_enableclk() tiva_uart_enableclk(7)
# define tiva_uart0_disableclk() tiva_uart_disableclk(0)
# define tiva_uart1_disableclk() tiva_uart_disableclk(1)
# define tiva_uart2_disableclk() tiva_uart_disableclk(2)
# define tiva_uart3_disableclk() tiva_uart_disableclk(3)
# define tiva_uart4_disableclk() tiva_uart_disableclk(4)
# define tiva_uart5_disableclk() tiva_uart_disableclk(5)
# define tiva_uart6_disableclk() tiva_uart_disableclk(6)
# define tiva_uart7_disableclk() tiva_uart_disableclk(7)
#else
# define tiva_uart0_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART0)
# define tiva_uart1_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART1)
# define tiva_uart2_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART2)
# define tiva_uart0_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART0)
# define tiva_uart1_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART1)
# define tiva_uart2_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART2)
#endif
/* SSI Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCSSI
# define tiva_ssi_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCSSI,SYSCON_RCGCSSI(p))
# define tiva_ssi_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCSSI,SYSCON_RCGCSSI(p))
# define tiva_ssi0_enableclk() tiva_ssi_enableclk(0)
# define tiva_ssi1_enableclk() tiva_ssi_enableclk(1)
# define tiva_ssi2_enableclk() tiva_ssi_enableclk(2)
# define tiva_ssi3_enableclk() tiva_ssi_enableclk(3)
# define tiva_ssi0_disableclk() tiva_ssi_disableclk(0)
# define tiva_ssi1_disableclk() tiva_ssi_disableclk(1)
# define tiva_ssi2_disableclk() tiva_ssi_disableclk(2)
# define tiva_ssi3_disableclk() tiva_ssi_disableclk(3)
#else
# define tiva_ssi0_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI0)
# define tiva_ssi1_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI1)
# define tiva_ssi0_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI0)
# define tiva_ssi1_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_SSI1)
#endif
/* I2C Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCI2C
# define tiva_i2c_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCI2C,SYSCON_RCGCI2C(p))
# define tiva_i2c_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCI2C,SYSCON_RCGCI2C(p))
# define tiva_i2c0_enableclk() tiva_i2c_enableclk(0)
# define tiva_i2c1_enableclk() tiva_i2c_enableclk(1)
# define tiva_i2c2_enableclk() tiva_i2c_enableclk(2)
# define tiva_i2c3_enableclk() tiva_i2c_enableclk(3)
# define tiva_i2c4_enableclk() tiva_i2c_enableclk(4)
# define tiva_i2c5_enableclk() tiva_i2c_enableclk(5)
# define tiva_i2c6_enableclk() tiva_i2c_enableclk(6)
# define tiva_i2c7_enableclk() tiva_i2c_enableclk(7)
# define tiva_i2c8_enableclk() tiva_i2c_enableclk(8)
# define tiva_i2c9_enableclk() tiva_i2c_enableclk(9)
# define tiva_i2c0_disableclk() tiva_i2c_disableclk(0)
# define tiva_i2c1_disableclk() tiva_i2c_disableclk(1)
# define tiva_i2c2_disableclk() tiva_i2c_disableclk(2)
# define tiva_i2c3_disableclk() tiva_i2c_disableclk(3)
# define tiva_i2c4_disableclk() tiva_i2c_disableclk(4)
# define tiva_i2c5_disableclk() tiva_i2c_disableclk(5)
# define tiva_i2c6_disableclk() tiva_i2c_disableclk(6)
# define tiva_i2c7_disableclk() tiva_i2c_disableclk(7)
# define tiva_i2c8_disableclk() tiva_i2c_disableclk(8)
# define tiva_i2c9_disableclk() tiva_i2c_disableclk(9)
#else
#endif
/* USB Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCUSB
# define tiva_usb_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCUSB,SYSCON_RCGCUSB_R0)
# define tiva_usb_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCUSB,SYSCON_RCGCUSB_R0)
#else
#endif
/* Ethernet PHY Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCEPHY
# define tiva_ephy_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCEPHY,SYSCON_RCGCEPHY_R0)
# define tiva_ephy_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCEPHY,SYSCON_RCGCEPHY_R0)
#else
#endif
/* CAN RunMode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCCAN
# define tiva_can_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCCAN,SYSCON_RCGCCAN(p))
# define tiva_can_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCCAN,SYSCON_RCGCCAN(p))
# define tiva_can0_enableclk() tiva_can_enableclk(0)
# define tiva_can1_enableclk() tiva_can_enableclk(1)
# define tiva_can0_disableclk() tiva_can_disableclk(0)
# define tiva_can1_disableclk() tiva_can_disableclk(1)
#else
#endif
/* ADC Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCADC
# define tiva_adc_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCADC,SYSCON_RCGCADC(p))
# define tiva_adc_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCADC,SYSCON_RCGCADC(p))
# define tiva_adc0_enableclk() tiva_adc_enableclk(0)
# define tiva_adc1_enableclk() tiva_adc_enableclk(1)
# define tiva_adc0_disableclk() tiva_adc_disableclk(0)
# define tiva_adc1_disableclk() tiva_adc_disableclk(1)
#else
#endif
/* ACMP Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCACMP
# define tiva_acmp_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCACMP,SYSCON_RCGCACMP_R0)
# define tiva_acmp_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCACMP,SYSCON_RCGCACMP_R0)
#else
#endif
/* PWM Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCPWM
# define tiva_pwm_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCPWM,SYSCON_RCGCPWM(p))
# define tiva_pwm_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCPWM,SYSCON_RCGCPWM(p))
# define tiva_pwm0_enableclk() tiva_pwm_enableclk(0)
# define tiva_pwm1_enableclk() tiva_pwm_enableclk(1)
# define tiva_pwm0_disableclk() tiva_pwm_disableclk(0)
# define tiva_pwm1_disableclk() tiva_pwm_disableclk(1)
#else
#endif
/* QE Interface Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCQEI
# define tiva_qei_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCQEI,SYSCON_RCGCQEI(p))
# define tiva_qei_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCQEI,SYSCON_RCGCQEI(p))
# define tiva_qei0_enableclk() tiva_qei_enableclk(0)
# define tiva_qei1_enableclk() tiva_qei_enableclk(1)
# define tiva_qei0_disableclk() tiva_qei_disableclk(0)
# define tiva_qei1_disableclk() tiva_qei_disableclk(1)
#else
#endif
/* EEPROM Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCEEPROM
# define tiva_eeprom_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCEEPROM,SYSCON_RCGCEEPROM_R0)
# define tiva_eeprom_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCEEPROM,SYSCON_RCGCEEPROM_R0)
#else
#endif
/* 32/64-Bit Wide Timer Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCWTIMER
# define tiva_wtm_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGCWTIMER,SYSCON_RCGCWTIMER(p))
# define tiva_wtm_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCWTIMER,SYSCON_RCGCWTIMER(p))
# define tiva_wtm0_enableclk() tiva_wtm_enableclk(0)
# define tiva_wtm1_enableclk() tiva_wtm_enableclk(1)
# define tiva_wtm2_enableclk() tiva_wtm_enableclk(2)
# define tiva_wtm3_enableclk() tiva_wtm_enableclk(3)
# define tiva_wtm4_enableclk() tiva_wtm_enableclk(4)
# define tiva_wtm5_enableclk() tiva_wtm_enableclk(5)
# define tiva_wtm0_disableclk() tiva_wtm_disableclk(0)
# define tiva_wtm1_disableclk() tiva_wtm_disableclk(1)
# define tiva_wtm2_disableclk() tiva_wtm_disableclk(2)
# define tiva_wtm3_disableclk() tiva_wtm_disableclk(3)
# define tiva_wtm4_disableclk() tiva_wtm_disableclk(4)
# define tiva_wtm5_disableclk() tiva_wtm_disableclk(5)
#else
#endif
/* CRC/Crypto Modules RunMode ClockGating Control */
#ifdef TIVA_SYSCON_RCGCCCM
# define tiva_ccm_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCCCM,SYSCON_RCGCCCM_R0)
# define tiva_ccm_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCCCM,SYSCON_RCGCCCM_R0)
#else
#endif
/* LCD Controller Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCLCD
# define tiva_lcd_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCLCD,SYSCON_RCGCLCD_R0)
# define tiva_lcd_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCLCD,SYSCON_RCGCLCD_R0)
#else
#endif
/* 1-Wire Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCOWIRE
# define tiva_owire_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCOWIRE,SYSCON_RCGCOWIRE_R0)
# define tiva_owire_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCOWIRE,SYSCON_RCGCOWIRE_R0)
#else
#endif
/* Ethernet MAC Run Mode Clock Gating Control */
#ifdef TIVA_SYSCON_RCGCEMAC
# define tiva_emac_enableclk() tiva_enableclk(TIVA_SYSCON_RCGCEMAC,SYSCON_RCGCEMAC_R0)
# define tiva_emac_disableclk() tiva_disableclk(TIVA_SYSCON_RCGCEMAC,SYSCON_RCGCEMAC_R0)
#if defined(CONFIG_ARCH_CHIP_LM3S) || defined(CONFIG_ARCH_CHIP_LM4F) || \
defined(CONFIG_ARCH_CHIP_TM4C)
# include "common/lmxx_tm4c_enableclks.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
# include "cc13xx/cc13xx_enableclks.h"
#else
# error "Unsupported Tiva/Stellaris/SimpleLink clock controls"
#endif
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_ENABLECLKS_H */

389
arch/arm/src/tiva/tiva_enablepwr.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/tiva/tiva_enablepwr.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2014, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -42,388 +42,15 @@
#include <nuttx/config.h>
#include "up_arch.h"
#include "chip.h"
#include "hardware/tiva_sysctrl.h"
/* Include chip specific definitions */
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Power control is enabled or disabled by setting or clearing a bit (b) in a system
* control register (a))
*/
#define tiva_enablepwr(a,b) modifyreg32((a),0,(b))
#define tiva_disablepwr(a,b) modifyreg32((a),(b),0)
/* Watchdog Timer Power Control */
#ifdef TIVA_SYSCON_PCWD
# define tiva_wdt_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCWD,SYSCON_PCWD(p))
# define tiva_wdt_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCWD,SYSCON_PCWD(p))
#if defined(CONFIG_ARCH_CHIP_LM3S) || defined(CONFIG_ARCH_CHIP_LM4F) || \
defined(CONFIG_ARCH_CHIP_TM4C)
# include "common/lmxx_tm4c_enablepwr.h"
#elif defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
# include "cc13xx/cc13xx_enablepwr.h"
#else
# define tiva_wdt_enablepwr(p)
# define tiva_wdt_disablepwr(p)
#endif
#define tiva_wdt0_enablepwr() tiva_wdt_enablepwr(0)
#define tiva_wdt1_enablepwr() tiva_wdt_enablepwr(1)
#define tiva_wdt0_disablepwr() tiva_wdt_disablepwr(0)
#define tiva_wdt1_disablepwr() tiva_wdt_disablepwr(1)
/* 16/32-Bit Timer Power Control */
#ifdef TIVA_SYSCON_PCTIMER
# define tiva_gptm_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCTIMER,SYSCON_PCTIMER(p))
# define tiva_gptm_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCTIMER,SYSCON_PCTIMER(p))
#else
# define tiva_gptm_enablepwr(p)
# define tiva_gptm_disablepwr(p)
#endif
#define tiva_gptm0_enablepwr() tiva_gptm_enablepwr(0)
#define tiva_gptm1_enablepwr() tiva_gptm_enablepwr(1)
#define tiva_gptm2_enablepwr() tiva_gptm_enablepwr(2)
#define tiva_gptm3_enablepwr() tiva_gptm_enablepwr(3)
#define tiva_gptm4_enablepwr() tiva_gptm_enablepwr(4)
#define tiva_gptm5_enablepwr() tiva_gptm_enablepwr(5)
#define tiva_gptm6_enablepwr() tiva_gptm_enablepwr(6)
#define tiva_gptm7_enablepwr() tiva_gptm_enablepwr(7)
#define tiva_gptm0_disablepwr() tiva_gptm_disablepwr(0)
#define tiva_gptm1_disablepwr() tiva_gptm_disablepwr(1)
#define tiva_gptm2_disablepwr() tiva_gptm_disablepwr(2)
#define tiva_gptm3_disablepwr() tiva_gptm_disablepwr(3)
#define tiva_gptm4_disablepwr() tiva_gptm_disablepwr(4)
#define tiva_gptm5_disablepwr() tiva_gptm_disablepwr(5)
#define tiva_gptm6_disablepwr() tiva_gptm_disablepwr(6)
#define tiva_gptm7_disablepwr() tiva_gptm_disablepwr(7)
/* GPIO Power Control */
#ifdef TIVA_SYSCON_PCGPIO
# define tiva_gpio_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCGPIO,SYSCON_PCGPIO(p))
# define tiva_gpio_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCGPIO,SYSCON_PCGPIO(p))
#else
# define tiva_gpio_enablepwr(p)
# define tiva_gpio_disablepwr(p)
#endif
#define tiva_gpioa_enablepwr() tiva_gpio_enablepwr(0)
#define tiva_gpiob_enablepwr() tiva_gpio_enablepwr(1)
#define tiva_gpioc_enablepwr() tiva_gpio_enablepwr(2)
#define tiva_gpiod_enablepwr() tiva_gpio_enablepwr(3)
#define tiva_gpioe_enablepwr() tiva_gpio_enablepwr(4)
#define tiva_gpiof_enablepwr() tiva_gpio_enablepwr(5)
#define tiva_gpiog_enablepwr() tiva_gpio_enablepwr(6)
#define tiva_gpioh_enablepwr() tiva_gpio_enablepwr(7)
#define tiva_gpioj_enablepwr() tiva_gpio_enablepwr(8)
#define tiva_gpiok_enablepwr() tiva_gpio_enablepwr(9)
#define tiva_gpiol_enablepwr() tiva_gpio_enablepwr(10)
#define tiva_gpiom_enablepwr() tiva_gpio_enablepwr(11)
#define tiva_gpion_enablepwr() tiva_gpio_enablepwr(12)
#define tiva_gpiop_enablepwr() tiva_gpio_enablepwr(13)
#define tiva_gpioq_enablepwr() tiva_gpio_enablepwr(14)
#define tiva_gpior_enablepwr() tiva_gpio_enablepwr(15)
#define tiva_gpios_enablepwr() tiva_gpio_enablepwr(16)
#define tiva_gpiot_enablepwr() tiva_gpio_enablepwr(17)
#define tiva_gpioa_disablepwr() tiva_gpio_disablepwr(0)
#define tiva_gpiob_disablepwr() tiva_gpio_disablepwr(1)
#define tiva_gpioc_disablepwr() tiva_gpio_disablepwr(2)
#define tiva_gpiod_disablepwr() tiva_gpio_disablepwr(3)
#define tiva_gpioe_disablepwr() tiva_gpio_disablepwr(4)
#define tiva_gpiof_disablepwr() tiva_gpio_disablepwr(5)
#define tiva_gpiog_disablepwr() tiva_gpio_disablepwr(6)
#define tiva_gpioh_disablepwr() tiva_gpio_disablepwr(7)
#define tiva_gpioj_disablepwr() tiva_gpio_disablepwr(8)
#define tiva_gpiok_disablepwr() tiva_gpio_disablepwr(9)
#define tiva_gpiol_disablepwr() tiva_gpio_disablepwr(10)
#define tiva_gpiom_disablepwr() tiva_gpio_disablepwr(11)
#define tiva_gpion_disablepwr() tiva_gpio_disablepwr(12)
#define tiva_gpiop_disablepwr() tiva_gpio_disablepwr(13)
#define tiva_gpioq_disablepwr() tiva_gpio_disablepwr(14)
#define tiva_gpior_disablepwr() tiva_gpio_disablepwr(15)
#define tiva_gpios_disablepwr() tiva_gpio_disablepwr(16)
#define tiva_gpiot_disablepwr() tiva_gpio_disablepwr(17)
/* μDMA Power Control */
#ifdef TIVA_SYSCON_PCDMA
# define tiva_udma_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCDMA,SYSCON_PCDMA_P0)
# define tiva_udma_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCDMA,SYSCON_PCDMA_P0)
#else
# define tiva_udma_enablepwr()
# define tiva_udma_disablepwr()
#endif
/* EPI Power Control */
#ifdef TIVA_SYSCON_PCEPI
# define tiva_epi_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEPI,SYSCON_PCEPI_P0)
# define tiva_epi_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEPI,SYSCON_PCEPI_P0)
#else
# define tiva_epi_enablepwr()
# define tiva_epi_disablepwr()
#endif
/* Hibernation Power Control */
#ifdef TIVA_SYSCON_PCHIB
# define tiva_hib_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCHIB,SYSCON_PCHIB_P0)
# define tiva_hib_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCHIB,SYSCON_PCHIB_P0)
#else
# define tiva_hib_enablepwr()
# define tiva_hib_disablepwr()
#endif
/* UART Power Control */
#ifdef TIVA_SYSCON_PCUART
# define tiva_uart_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCUART,SYSCON_PCUART(p))
# define tiva_uart_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCUART,SYSCON_PCUART(p))
#else
# define tiva_uart_enablepwr(p)
# define tiva_uart_disablepwr(p)
#endif
#define tiva_uart0_enablepwr() tiva_uart_enablepwr(0)
#define tiva_uart1_enablepwr() tiva_uart_enablepwr(1)
#define tiva_uart2_enablepwr() tiva_uart_enablepwr(2)
#define tiva_uart3_enablepwr() tiva_uart_enablepwr(3)
#define tiva_uart4_enablepwr() tiva_uart_enablepwr(4)
#define tiva_uart5_enablepwr() tiva_uart_enablepwr(5)
#define tiva_uart6_enablepwr() tiva_uart_enablepwr(6)
#define tiva_uart7_enablepwr() tiva_uart_enablepwr(7)
#define tiva_uart0_disablepwr() tiva_uart_disablepwr(0)
#define tiva_uart1_disablepwr() tiva_uart_disablepwr(1)
#define tiva_uart2_disablepwr() tiva_uart_disablepwr(2)
#define tiva_uart3_disablepwr() tiva_uart_disablepwr(3)
#define tiva_uart4_disablepwr() tiva_uart_disablepwr(4)
#define tiva_uart5_disablepwr() tiva_uart_disablepwr(5)
#define tiva_uart6_disablepwr() tiva_uart_disablepwr(6)
#define tiva_uart7_disablepwr() tiva_uart_disablepwr(7)
/* SSI Power Control */
#ifdef TIVA_SYSCON_PCSSI
# define tiva_ssi_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCSSI,SYSCON_PCSSI(p))
# define tiva_ssi_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCSSI,SYSCON_PCSSI(p))
#else
# define tiva_ssi_enablepwr(p)
# define tiva_ssi_disablepwr(p)
#endif
#define tiva_ssi0_enablepwr() tiva_ssi_enablepwr(0)
#define tiva_ssi1_enablepwr() tiva_ssi_enablepwr(1)
#define tiva_ssi2_enablepwr() tiva_ssi_enablepwr(2)
#define tiva_ssi3_enablepwr() tiva_ssi_enablepwr(3)
#define tiva_ssi0_disablepwr() tiva_ssi_disablepwr(0)
#define tiva_ssi1_disablepwr() tiva_ssi_disablepwr(1)
#define tiva_ssi2_disablepwr() tiva_ssi_disablepwr(2)
#define tiva_ssi3_disablepwr() tiva_ssi_disablepwr(3)
/* I2C Power Control */
#ifdef TIVA_SYSCON_PCI2C
# define tiva_i2c_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCI2C,SYSCON_PCI2C(p))
# define tiva_i2c_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCI2C,SYSCON_PCI2C(p))
#else
# define tiva_i2c_enablepwr(p)
# define tiva_i2c_disablepwr(p)
#endif
#define tiva_i2c0_enablepwr() tiva_i2c_enablepwr(0)
#define tiva_i2c1_enablepwr() tiva_i2c_enablepwr(1)
#define tiva_i2c2_enablepwr() tiva_i2c_enablepwr(2)
#define tiva_i2c3_enablepwr() tiva_i2c_enablepwr(3)
#define tiva_i2c4_enablepwr() tiva_i2c_enablepwr(4)
#define tiva_i2c5_enablepwr() tiva_i2c_enablepwr(5)
#define tiva_i2c6_enablepwr() tiva_i2c_enablepwr(6)
#define tiva_i2c7_enablepwr() tiva_i2c_enablepwr(7)
#define tiva_i2c8_enablepwr() tiva_i2c_enablepwr(8)
#define tiva_i2c9_enablepwr() tiva_i2c_enablepwr(9)
#define tiva_i2c0_disablepwr() tiva_i2c_disablepwr(0)
#define tiva_i2c1_disablepwr() tiva_i2c_disablepwr(1)
#define tiva_i2c2_disablepwr() tiva_i2c_disablepwr(2)
#define tiva_i2c3_disablepwr() tiva_i2c_disablepwr(3)
#define tiva_i2c4_disablepwr() tiva_i2c_disablepwr(4)
#define tiva_i2c5_disablepwr() tiva_i2c_disablepwr(5)
#define tiva_i2c6_disablepwr() tiva_i2c_disablepwr(6)
#define tiva_i2c7_disablepwr() tiva_i2c_disablepwr(7)
#define tiva_i2c8_disablepwr() tiva_i2c_disablepwr(8)
#define tiva_i2c9_disablepwr() tiva_i2c_disablepwr(9)
/* USB Power Control */
#ifdef TIVA_SYSCON_PCUSB
# define tiva_usb_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCUSB,SYSCON_PCUSB_P0)
# define tiva_usb_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCUSB,SYSCON_PCUSB_P0)
#else
# define tiva_usb_enablepwr()
# define tiva_usb_disablepwr()
#endif
/* Ethernet PHY Power Control */
#ifdef TIVA_SYSCON_PCEPHY
# define tiva_ephy_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEPHY,SYSCON_PCEPHY_P0)
# define tiva_ephy_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEPHY,SYSCON_PCEPHY_P0)
#else
# define tiva_ephy_enablepwr()
# define tiva_ephy_disablepwr()
#endif
/* CAN RunMode Clock Gating Control */
#ifdef TIVA_SYSCON_PCCAN
# define tiva_can_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCCAN,SYSCON_PCCAN(p))
# define tiva_can_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCCAN,SYSCON_PCCAN(p))
#else
# define tiva_can_enablepwr(p)
# define tiva_can_disablepwr(p)
#endif
#define tiva_can0_enablepwr() tiva_can_enablepwr(0)
#define tiva_can1_enablepwr() tiva_can_enablepwr(1)
#define tiva_can0_disablepwr() tiva_can_disablepwr(0)
#define tiva_can1_disablepwr() tiva_can_disablepwr(1)
/* ADC Power Control */
#ifdef TIVA_SYSCON_PCADC
# define tiva_adc_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCADC,SYSCON_PCADC(p))
# define tiva_adc_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCADC,SYSCON_PCADC(p))
#else
# define tiva_adc_enablepwr(p)
# define tiva_adc_disablepwr(p)
#endif
#define tiva_adc0_enablepwr() tiva_adc_enablepwr(0)
#define tiva_adc1_enablepwr() tiva_adc_enablepwr(1)
#define tiva_adc0_disablepwr() tiva_adc_disablepwr(0)
#define tiva_adc1_disablepwr() tiva_adc_disablepwr(1)
/* ACMP Power Control */
#ifdef TIVA_SYSCON_PCACMP
# define tiva_acmp_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCACMP,SYSCON_PCACMP_P0)
# define tiva_acmp_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCACMP,SYSCON_PCACMP_P0)
#else
# define tiva_acmp_enablepwr()
# define tiva_acmp_disablepwr()
#endif
/* PWM Power Control */
#ifdef TIVA_SYSCON_PCPWM
# define tiva_pwm_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCPWM,SYSCON_PCPWM(p))
# define tiva_pwm_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCPWM,SYSCON_PCPWM(p))
#else
# define tiva_pwm_enablepwr(p)
# define tiva_pwm_disablepwr(p)
#endif
#define tiva_pwm0_enablepwr() tiva_pwm_enablepwr(0)
#define tiva_pwm1_enablepwr() tiva_pwm_enablepwr(1)
#define tiva_pwm0_disablepwr() tiva_pwm_disablepwr(0)
#define tiva_pwm1_disablepwr() tiva_pwm_disablepwr(1)
/* QE Interface Power Control */
#ifdef TIVA_SYSCON_PCQEI
# define tiva_qei_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCQEI,SYSCON_PCQEI(p))
# define tiva_qei_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCQEI,SYSCON_PCQEI(p))
#else
# define tiva_qei_enablepwr(p)
# define tiva_qei_disablepwr(p)
#endif
#define tiva_qei0_enablepwr() tiva_qei_enablepwr(0)
#define tiva_qei1_enablepwr() tiva_qei_enablepwr(1)
#define tiva_qei0_disablepwr() tiva_qei_disablepwr(0)
#define tiva_qei1_disablepwr() tiva_qei_disablepwr(1)
/* EEPROM Power Control */
#ifdef TIVA_SYSCON_PCEEPROM
# define tiva_eeprom_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEEPROM,SYSCON_PCEEPROM_P0)
# define tiva_eeprom_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEEPROM,SYSCON_PCEEPROM_P0)
#else
# define tiva_eeprom_enablepwr()
# define tiva_eeprom_disablepwr()
#endif
/* 32/64-Bit Wide Timer Power Control */
#ifdef TIVA_SYSCON_PCWTIMER
# define tiva_wtm_enablepwr(p) tiva_enablepwr(TIVA_SYSCON_PCWTIMER,SYSCON_PCWTIMER(p))
# define tiva_wtm_disablepwr(p) tiva_disablepwr(TIVA_SYSCON_PCWTIMER,SYSCON_PCWTIMER(p))
#else
# define tiva_wtm_enablepwr(p)
# define tiva_wtm_disablepwr(p)
#endif
#define tiva_wtm0_enablepwr() tiva_wtm_enablepwr(0)
#define tiva_wtm1_enablepwr() tiva_wtm_enablepwr(1)
#define tiva_wtm2_enablepwr() tiva_wtm_enablepwr(2)
#define tiva_wtm3_enablepwr() tiva_wtm_enablepwr(3)
#define tiva_wtm4_enablepwr() tiva_wtm_enablepwr(4)
#define tiva_wtm5_enablepwr() tiva_wtm_enablepwr(5)
#define tiva_wtm0_disablepwr() tiva_wtm_disablepwr(0)
#define tiva_wtm1_disablepwr() tiva_wtm_disablepwr(1)
#define tiva_wtm2_disablepwr() tiva_wtm_disablepwr(2)
#define tiva_wtm3_disablepwr() tiva_wtm_disablepwr(3)
#define tiva_wtm4_disablepwr() tiva_wtm_disablepwr(4)
#define tiva_wtm5_disablepwr() tiva_wtm_disablepwr(5)
/* CRC/Crypto Modules RunMode ClockGating Control */
#ifdef TIVA_SYSCON_PCCCM
# define tiva_ccm_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCCCM,SYSCON_PCCCM_P0)
# define tiva_ccm_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCCCM,SYSCON_PCCCM_P0)
#else
# define tiva_ccm_enablepwr()
# define tiva_ccm_disablepwr()
#endif
/* LCD Controller Power Control */
#ifdef TIVA_SYSCON_PCLCD
# define tiva_lcd_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCLCD,SYSCON_PCLCD_P0)
# define tiva_lcd_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCLCD,SYSCON_PCLCD_P0)
#else
# define tiva_lcd_enablepwr()
# define tiva_lcd_disablepwr()
#endif
/* 1-Wire Power Control */
#ifdef TIVA_SYSCON_PCOWIRE
# define tiva_owire_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCOWIRE,SYSCON_PCOWIRE_P0)
# define tiva_owire_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCOWIRE,SYSCON_PCOWIRE_P0)
#else
# define tiva_owire_enablepwr()
# define tiva_owire_disablepwr()
#endif
/* Ethernet MAC Power Control */
#ifdef TIVA_SYSCON_PCEMAC
# define tiva_emac_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEMAC,SYSCON_PCEMAC_P0)
# define tiva_emac_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEMAC,SYSCON_PCEMAC_P0)
#else
# define tiva_emac_enablepwr()
# define tiva_emac_disablepwr()
# error "Unsupported Tiva/Stellaris/SimpleLink power controls"
#endif
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_ENABLEPWR_H */

8
arch/arm/src/tiva/tiva_gpio.h
View File

@ -47,12 +47,6 @@
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "up_internal.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
@ -69,7 +63,7 @@
#elif defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
# include "cc13xx/cc13xx_gpio.h"
#else
# error "Unsupported Tiva/Stellaris system GPIO"
# error "Unsupported Tiva/Stellaris/SimpleLink GPIO"
#endif
/****************************************************************************