SAMV71: Add PMC register definition header files
This commit is contained in:
Gregory Nutt
parent
6e6b9483ea
commit
7113de4d18
@ -66,6 +66,7 @@
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#define SAM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define SAM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define SAM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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/* Vectors 7-10: Reserved */
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#define SAM_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define SAM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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@ -65,7 +65,7 @@
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#define SAM_PID_PIOC (12) /* Parallel I/O Controller C */
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#define SAM_PID_USART0 (13) /* USART 0 */
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#define SAM_PID_USART1 (14) /* USART 1 */
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#define SAM_PID_USART1 (15) /* USART 2 */
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#define SAM_PID_USART2 (15) /* USART 2 */
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#define SAM_PID_PIOD (16) /* Parallel I/O Controller D */
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#define SAM_PID_PIOE (17) /* Parallel I/O Controller E */
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#define SAM_PID_HSMCI (18) /* High Speed Multimedia Card Interface */
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@ -284,8 +284,8 @@
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# define PMC_CKGR_MOR_MOSCRCF_4MHz (0 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 4MHz (default) */
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# define PMC_CKGR_MOR_MOSCRCF_8MHz (1 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 8MHz */
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# define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */
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#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */
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#define PMC_CKGR_MOR_MOSCXTST_MASK (0x1ff << PMC_CKGR_MOR_MOSCXTST_SHIFT)
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#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-15: Main Crystal Oscillator Start-up Time */
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#define PMC_CKGR_MOR_MOSCXTST_MASK (0xff << PMC_CKGR_MOR_MOSCXTST_SHIFT)
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# define PMC_CKGR_MOR_MOSCXTST(n) ((uint32_t)(n) << PMC_CKGR_MOR_MOSCXTST_SHIFT)
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#define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */
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#define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT)
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@ -500,8 +500,8 @@
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define PMC_FSMR_FLPM_SHIFT (21) /* Bit 21-22: Low Power Mode (MR only) */
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# define PMC_FSMR_FLPM_MASK (3 << PMC_FSMR_FLPM_SHIFT)
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# define PMC_FSMR_FLPM_PWRDOWN (0 << PMC_FSMR_FLPM_SHIFT) /* Flash Standby Mode */
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# define PMC_FSMR_FLPM_STANDBY (1 << PMC_FSMR_FLPM_SHIFT) /* Flash deep power down mode */
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# define PMC_FSMR_FLPM_STANDBY (0 << PMC_FSMR_FLPM_SHIFT) /* Flash Standby Mode */
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# define PMC_FSMR_FLPM_PWRDOWN (1 << PMC_FSMR_FLPM_SHIFT) /* Flash deep power down mode */
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# define PMC_FSMR_FLPM_IDLE (2 << PMC_FSMR_FLPM_SHIFT) /* Idle mode */
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#endif
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@ -53,7 +53,7 @@
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#include "chip.h"
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/****************************************************************************
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* Definitions
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* Pre-processor Definitions
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****************************************************************************/
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/* Select MCU-specific settings
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*
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462
arch/arm/src/samv7/chip/sam_pmc.h
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462
arch/arm/src/samv7/chip/sam_pmc.h
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@ -0,0 +1,462 @@
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/********************************************************************************************
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* arch/arm/src/samv7/chip/sam_pmc.h
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* Power Management Controller (PMC) for the SAMV71
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_PMC_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_PMC_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* PMC register offsets *********************************************************************/
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#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */
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#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */
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#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */
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/* 0x000c: Reserved */
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#define SAM_PMC_PCER0_OFFSET 0x0010 /* Peripheral Clock Enable Register 0 */
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#define SAM_PMC_PCDR0_OFFSET 0x0014 /* Peripheral Clock Disable Register 0 */
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#define SAM_PMC_PCSR0_OFFSET 0x0018 /* Peripheral Clock Status Register 0 */
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#define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */
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#define SAM_PMC_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */
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#define SAM_PMC_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */
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#define SAM_PMC_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */
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/* 0x002c: Reserved */
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#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */
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/* 0x0034 Reserved */
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#define SAM_PMC_USB_OFFSET 0x0038 /* USB Clock Register PMC_USB */
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/* 0x0034-0x003c Reserved (SAM3U) */
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#define SAM_PMC_PCK_OFFSET(n) (0x0040 + ((n) << 2))
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# define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */
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# define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */
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# define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */
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# define SAM_PMC_PCK3_OFFSET 0x004c /* Programmable Clock 4 Register */
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# define SAM_PMC_PCK4_OFFSET 0x0050 /* Programmable Clock 5 Register */
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# define SAM_PMC_PCK5_OFFSET 0x0054 /* Programmable Clock 6 Register */
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# define SAM_PMC_PCK6_OFFSET 0x0058 /* Programmable Clock 7 Register */
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/* 0x005c: Reserved */
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#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */
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#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */
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#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */
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#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */
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#define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */
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#define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */
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#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */
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/* 0x007c-0x00e0: Reserved */
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#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
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#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
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/* 0x00ec-0x00fc: Reserved */
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#define SAM_PMC_PCER1_OFFSET 0x0100 /* Peripheral Clock Enable Register 1 */
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#define SAM_PMC_PCDR1_OFFSET 0x0104 /* Peripheral Clock Disable Register 1 */
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#define SAM_PMC_PCSR1_OFFSET 0x0108 /* Peripheral Clock Status Register 1 */
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#define SAM_PMC_PCR_OFFSET 0x010c /* Peripheral Control Register */
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#define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */
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#define SAM_PMC_SLPWK_ER0_OFFSET 0x0114 /* SleepWalking Enable Register 0 */
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#define SAM_PMC_SLPWK_DR0_OFFSET 0x0118 /* SleepWalking Disable Register 0 */
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#define SAM_PMC_SLPWK_SR0_OFFSET 0x011c /* SleepWalking Status Register 0 */
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#define SAM_PMC_SLPWK_ASR0_OFFSET 0x0120 /* SleepWalking Activity Status Register 0 */
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#define SAM_PMC_SLPWK_ER1_OFFSET 0x0134 /* SleepWalking Enable Register 1 */
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#define SAM_PMC_SLPWK_DR1_OFFSET 0x0138 /* SleepWalking Disable Register 1 */
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#define SAM_PMC_SLPWK_SR1_OFFSET 0x013c /* SleepWalking Status Register 1 */
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#define SAM_PMC_SLPWK_ASR1_OFFSET 0x0140 /* SleepWalking Activity Status Register 1 */
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#define SAM_PMC_SLPWK_AIPR_OFFSET 0x0144 /* SleepWalking Activity In Progress Register */
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/* PMC register addresses *******************************************************************/
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#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET)
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#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET)
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#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET)
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#define SAM_PMC_PCER0 (SAM_PMC_BASE+SAM_PMC_PCER0_OFFSET)
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#define SAM_PMC_PCDR0 (SAM_PMC_BASE+SAM_PMC_PCDR0_OFFSET)
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#define SAM_PMC_PCSR0 (SAM_PMC_BASE+SAM_PMC_PCSR0_OFFSET)
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#define SAM_PMC_CKGR_UCKR (SAM_PMC_BASE+SAM_PMC_CKGR_UCKR_OFFSET)
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#define SAM_PMC_CKGR_MOR (SAM_PMC_BASE+SAM_PMC_CKGR_MOR_OFFSET)
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#define SAM_PMC_CKGR_MCFR (SAM_PMC_BASE+SAM_PMC_CKGR_MCFR_OFFSET)
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#define SAM_PMC_CKGR_PLLAR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLAR_OFFSET)
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#define SAM_PMC_MCKR (SAM_PMC_BASE+SAM_PMC_MCKR_OFFSET)
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#define SAM_PMC_USB (SAM_PMC_BASE+SAM_PMC_USB_OFFSET)
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#define SAM_PMC_PCK(n) (SAM_PMC_BASE+SAM_PMC_PCK_OFFSET(n))
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# define SAM_PMC_PCK0 (SAM_PMC_BASE+SAM_PMC_PCK0_OFFSET)
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# define SAM_PMC_PCK1 (SAM_PMC_BASE+SAM_PMC_PCK1_OFFSET)
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# define SAM_PMC_PCK2 (SAM_PMC_BASE+SAM_PMC_PCK2_OFFSET)
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# define SAM_PMC_PCK3 (SAM_PMC_BASE+SAM_PMC_PCK3_OFFSET)
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# define SAM_PMC_PCK4 (SAM_PMC_BASE+SAM_PMC_PCK4_OFFSET)
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# define SAM_PMC_PCK5 (SAM_PMC_BASE+SAM_PMC_PCK5_OFFSET)
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# define SAM_PMC_PCK6 (SAM_PMC_BASE+SAM_PMC_PCK6_OFFSET)
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#define SAM_PMC_IER (SAM_PMC_BASE+SAM_PMC_IER_OFFSET)
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#define SAM_PMC_IDR (SAM_PMC_BASE+SAM_PMC_IDR_OFFSET)
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#define SAM_PMC_SR (SAM_PMC_BASE+SAM_PMC_SR_OFFSET)
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#define SAM_PMC_IMR (SAM_PMC_BASE+SAM_PMC_IMR_OFFSET)
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#define SAM_PMC_FSMR (SAM_PMC_BASE+SAM_PMC_FSMR_OFFSET)
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#define SAM_PMC_FSPR (SAM_PMC_BASE+SAM_PMC_FSPR_OFFSET)
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#define SAM_PMC_FOCR (SAM_PMC_BASE+SAM_PMC_FOCR_OFFSET)
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#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET)
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#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET)
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#define SAM_PMC_PCER1 (SAM_PMC_BASE+SAM_PMC_PCER1_OFFSET)
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#define SAM_PMC_PCDR1 (SAM_PMC_BASE+SAM_PMC_PCDR1_OFFSET)
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#define SAM_PMC_PCSR1 (SAM_PMC_BASE+SAM_PMC_PCSR1_OFFSET)
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#define SAM_PMC_PCR (SAM_PMC_BASE+SAM_PMC_PCR_OFFSET)
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#define SAM_PMC_OCR (SAM_PMC_BASE+SAM_PMC_OCR_OFFSET)
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#define SAM_PMC_SLPWK_ER0 (SAM_PMC_BASE+SAM_PMC_SLPWK_ER0_OFFSET)
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#define SAM_PMC_SLPWK_DR0 (SAM_PMC_BASE+SAM_PMC_SLPWK_DR0_OFFSET)
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#define SAM_PMC_SLPWK_SR0 (SAM_PMC_BASE+SAM_PMC_SLPWK_SR0_OFFSET)
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#define SAM_PMC_SLPWK_ASR0 (SAM_PMC_BASE+SAM_PMC_SLPWK_ASR0_OFFSET)
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#define SAM_PMC_SLPWK_ER1 (SAM_PMC_BASE+SAM_PMC_SLPWK_ER1_OFFSET)
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#define SAM_PMC_SLPWK_DR1 (SAM_PMC_BASE+SAM_PMC_SLPWK_DR1_OFFSET)
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#define SAM_PMC_SLPWK_SR1 (SAM_PMC_BASE+SAM_PMC_SLPWK_SR1_OFFSET)
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#define SAM_PMC_SLPWK_ASR1 (SAM_PMC_BASE+SAM_PMC_SLPWK_ASR1_OFFSET)
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#define SAM_PMC_SLPWK_AIPR (SAM_PMC_BASE+SAM_PMC_SLPWK_AIPR_OFFSET)
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/* PMC register bit definitions *************************************************************/
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/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System
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* Clock Status Register common bit-field definitions
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*/
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#define PMC_USBCLK (1 << 5) /* Bit 5: Enable USB FS Clock */
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#define PMC_PCK(n) (1 << ((n) + 8)
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# define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */
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# define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */
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# define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */
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# define PMC_PCK3 (1 << 11) /* Bit 11: Programmable Clock 3 Output Enable */
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# define PMC_PCK4 (1 << 12) /* Bit 12: Programmable Clock 4 Output Enable */
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# define PMC_PCK5 (1 << 13) /* Bit 13: Programmable Clock 5 Output Enable */
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# define PMC_PCK6 (1 << 14) /* Bit 14: Programmable Clock 6 Output Enable */
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/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC
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* Peripheral Clock Status Register common bit-field definitions.
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*/
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#define PMC_PIDL(n) (1 << (n))
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# define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */
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# define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */
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# define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */
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# define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */
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# define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */
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# define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */
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# define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */
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# define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */
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# define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */
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# define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */
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# define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */
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# define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */
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# define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */
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# define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */
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# define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */
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# define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */
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# define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */
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# define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */
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# define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */
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# define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */
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# define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */
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# define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */
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# define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */
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# define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */
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# define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */
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/* PMC UTMI Clock Configuration Register */
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#define PMC_CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */
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#define PMC_CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */
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#define PMC_CKGR_UCKR_UPLLCOUNT_MASK (15 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
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/* PMC Clock Generator Main Oscillator Register */
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#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */
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#define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */
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#define PMC_CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */
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#define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */
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#define PMC_CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */
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#define PMC_CKGR_MOR_MOSCRCF_MASK (7 << PMC_CKGR_MOR_MOSCRCF_SHIFT)
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# define PMC_CKGR_MOR_MOSCRCF_4MHz (0 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 4MHz (default) */
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# define PMC_CKGR_MOR_MOSCRCF_8MHz (1 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 8MHz */
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# define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */
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#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-15: Main Crystal Oscillator Start-up Time */
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#define PMC_CKGR_MOR_MOSCXTST_MASK (0xff << PMC_CKGR_MOR_MOSCXTST_SHIFT)
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# define PMC_CKGR_MOR_MOSCXTST(n) ((uint32_t)(n) << PMC_CKGR_MOR_MOSCXTST_SHIFT)
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#define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */
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#define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT)
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# define PMC_CKGR_MOR_KEY (0x37 << PMC_CKGR_MOR_KEY_SHIFT)
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#define PMC_CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */
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#define PMC_CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */
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#define PMC_CKGR_MOR_XT32KFME (1 << 26) /* Bit 26: Main Crystal Oscillator Enable */
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/* PMC Clock Generator Main Clock Frequency Register */
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#define PMC_CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */
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#define PMC_CKGR_MCFR_MAINF_MASK (0xffff << PMC_CKGR_MCFR_MAINF_SHIFT)
|
||||
# define PMC_CKGR_MCFR_MAINF(n) ((uint32_t)(n) << PMC_CKGR_MCFR_MAINF_SHIFT)
|
||||
#define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */
|
||||
#define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */
|
||||
#define PMC_CKGR_MCFR_CCSS (1 << 24) /* Bit 21: Counter Clock Source Selection */
|
||||
# define PMC_CKGR_MCFR_CCSS_RCOSC (0 << 24) /* 0=Clock of the MAINF counter is RC oscillator */
|
||||
# define PMC_CKGR_MCFR_CCSS_XTAL (1 << 24) /* 1=Clock of the MAINF counter is crystal oscillator */
|
||||
|
||||
/* PMC Clock Generator PLLA Register */
|
||||
|
||||
#define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */
|
||||
#define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT)
|
||||
# define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */
|
||||
# define PMC_CKGR_PLLAR_DIV_BYPASS (1 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */
|
||||
# define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */
|
||||
#define PMC_CKGR_PLLAR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */
|
||||
#define PMC_CKGR_PLLAR_COUNT_MASK (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
|
||||
#define PMC_CKGR_PLLAR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */
|
||||
#define PMC_CKGR_PLLAR_MUL_MASK (0x7ff << PMC_CKGR_PLLAR_MUL_SHIFT)
|
||||
#define PMC_CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */
|
||||
|
||||
/* PMC Master Clock Register */
|
||||
|
||||
#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */
|
||||
#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT)
|
||||
# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */
|
||||
# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */
|
||||
# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */
|
||||
# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* Divided UPLL Clock */
|
||||
#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */
|
||||
#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT)
|
||||
# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */
|
||||
# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */
|
||||
# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */
|
||||
# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */
|
||||
# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */
|
||||
# define PMC_MCKR_PRES_DIV32 (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */
|
||||
# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */
|
||||
# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */
|
||||
#define PMC_MCKR_MDIV_SHIFT (8) /* Bits 8-9: Master Clock Division */
|
||||
#define PMC_MCKR_MDIV_MASK (3 << PMC_MCKR_MDIV_SHIFT)
|
||||
# define PMC_MCKR_MDIV_DIV1 (0 << PMC_MCKR_MDIV_SHIFT) /* Master Clock is Prescaler Output Clock / 1 */
|
||||
# define PMC_MCKR_MDIV_DIV2 (1 << PMC_MCKR_MDIV_SHIFT) /* Master Clock = Prescaler Output Clock / 2 */
|
||||
# define PMC_MCKR_MDIV_DIV4 (2 << PMC_MCKR_MDIV_SHIFT) /* Master Clock = Prescaler Output Clock / 4 */
|
||||
# define PMC_MCKR_MDIV_DIV3 (3 << PMC_MCKR_MDIV_SHIFT) /* Master Clock = Prescaler Output Clock / 3 */
|
||||
#define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */
|
||||
|
||||
/* USB Clock Register PMC_USB */
|
||||
|
||||
#define PMC_USB_USBS (1 << 0) /* Bit 0: USB Input Clock Selection */
|
||||
# define PMC_USB_USBS_PLLA (0 << 0) /* 0=USB clock input is PLLA */
|
||||
# define PMC_USB_USBS_UPLL (1 << 0) /* 1=USB clock input is UPLL */
|
||||
#define PMC_USB_USBDIV_SHIFT (8) /* Bits 8-11: Divider for USB Clock */
|
||||
#define PMC_USB_USBDIV_MASK (15 << PMC_USB_USBDIV_SHIFT)
|
||||
# define PMC_USB_USBDIV(n) ((uint32_t)(n) << PMC_USB_USBDIV_SHIFT)
|
||||
|
||||
/* PMC Programmable Clock Register (0,..,6) */
|
||||
|
||||
#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */
|
||||
#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_SHIFT)
|
||||
# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_SHIFT) /* Slow Clock */
|
||||
# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_SHIFT) /* Main Clock */
|
||||
# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_SHIFT) /* PLLA Clock */
|
||||
# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_SHIFT) /* Divided UPLL Clock */
|
||||
# define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_SHIFT) /* Master Clock */
|
||||
#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-11: Programmable Clock Prescaler */
|
||||
#define PMC_PCK_PRES_MASK (0xff << PMC_PCK_PRES_SHIFT)
|
||||
# define PMC_PCK_PRES(n) ((uint32_t)((n)-1) << PMC_PCK_PRES_SHIFT) /* n=1..256 */
|
||||
|
||||
/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register,
|
||||
* and PMC Interrupt Mask Register common bit-field definitions
|
||||
*/
|
||||
|
||||
#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */
|
||||
#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */
|
||||
#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */
|
||||
#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */
|
||||
#define PMC_INT_PCKRDY(n) (1 << ((n)+8)
|
||||
# define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */
|
||||
# define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */
|
||||
# define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */
|
||||
# define PMC_INT_PCKRDY3 (1 << 11) /* Bit 11: Programmable Clock Ready 3 Interrupt */
|
||||
# define PMC_INT_PCKRDY4 (1 << 12) /* Bit 12: Programmable Clock Ready 4 Interrupt */
|
||||
# define PMC_INT_PCKRDY5 (1 << 13) /* Bit 13: Programmable Clock Ready 5 Interrupt */
|
||||
# define PMC_INT_PCKRDY6 (1 << 14) /* Bit 14: Programmable Clock Ready 6 Interrupt */
|
||||
#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */
|
||||
#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */
|
||||
#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */
|
||||
#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */
|
||||
#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */
|
||||
#define PMC_INT_XT32KERR (1 << 21) /* Bit 21: Slow Crystal Oscillator Error Interrupt */
|
||||
|
||||
/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field
|
||||
* definitions
|
||||
*/
|
||||
|
||||
#define PMC_FSTI(n) (1 << (n))
|
||||
# define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */
|
||||
# define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */
|
||||
# define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */
|
||||
# define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */
|
||||
# define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */
|
||||
# define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */
|
||||
# define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */
|
||||
# define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */
|
||||
# define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */
|
||||
# define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */
|
||||
# define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */
|
||||
# define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */
|
||||
# define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */
|
||||
# define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */
|
||||
# define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */
|
||||
# define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */
|
||||
#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */
|
||||
#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */
|
||||
#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */
|
||||
#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */
|
||||
#define PMC_FSMR_FLPM_SHIFT (21) /* Bit 21-22: Low Power Mode (MR only) */
|
||||
#define PMC_FSMR_FLPM_MASK (3 << PMC_FSMR_FLPM_SHIFT)
|
||||
# define PMC_FSMR_FLPM_STANDBY (0 << PMC_FSMR_FLPM_SHIFT) /* Flash Standby Mode */
|
||||
# define PMC_FSMR_FLPM_PWRDOWN (1 << PMC_FSMR_FLPM_SHIFT) /* Flash deep power down mode */
|
||||
# define PMC_FSMR_FLPM_IDLE (2 << PMC_FSMR_FLPM_SHIFT) /* Idle mode */
|
||||
#define PMC_FSMR_FFLPM (1 << 23) /* Bit 20: Force Flash Low-power Mode (MR only) */
|
||||
|
||||
/* PMC Fault Output Clear Register */
|
||||
|
||||
#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */
|
||||
|
||||
/* PMC Write Protect Mode Register */
|
||||
|
||||
#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
|
||||
#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
|
||||
#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT)
|
||||
# define PMC_WPMR_WPKEY (0x00504d43 << PMC_WPMR_WPKEY_SHIFT)
|
||||
|
||||
/* PMC Write Protect Status Register */
|
||||
|
||||
#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
|
||||
#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
|
||||
#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT)
|
||||
|
||||
/* Peripheral Clock Enable Register 1, Peripheral Clock Disable Register 1, and Peripheral
|
||||
* Clock Status Register 1
|
||||
*/
|
||||
|
||||
#define PMC_PIDH(n) (1 << ((n) - 32))
|
||||
# define PMC_PID32 (1 << 0) /* Bit 0: PID32 */
|
||||
# define PMC_PID33 (1 << 1) /* Bit 1: PID33 */
|
||||
# define PMC_PID34 (1 << 2) /* Bit 2: PID34 */
|
||||
# define PMC_PID35 (1 << 3) /* Bit 3: PID35 */
|
||||
# define PMC_PID37 (1 << 5) /* Bit 5: PID37 */
|
||||
# define PMC_PID39 (1 << 7) /* Bit 7: PID39 */
|
||||
# define PMC_PID40 (1 << 8) /* Bit 8: PID40 */
|
||||
# define PMC_PID41 (1 << 9) /* Bit 9: PID41 */
|
||||
# define PMC_PID42 (1 << 10) /* Bit 10: PID42 */
|
||||
# define PMC_PID43 (1 << 11) /* Bit 11: PID43 */
|
||||
# define PMC_PID44 (1 << 12) /* Bit 12: PID44 */
|
||||
# define PMC_PID45 (1 << 13) /* Bit 13: PID45 */
|
||||
# define PMC_PID46 (1 << 14) /* Bit 14: PID46 */
|
||||
# define PMC_PID47 (1 << 15) /* Bit 15: PID47 */
|
||||
# define PMC_PID48 (1 << 16) /* Bit 16: PID48 */
|
||||
# define PMC_PID49 (1 << 17) /* Bit 17: PID49 */
|
||||
# define PMC_PID50 (1 << 18) /* Bit 18: PID50 */
|
||||
# define PMC_PID51 (1 << 19) /* Bit 19: PID51 */
|
||||
# define PMC_PID52 (1 << 20) /* Bit 20: PID52 */
|
||||
# define PMC_PID53 (1 << 21) /* Bit 21: PID53 */
|
||||
# define PMC_PID56 (1 << 24) /* Bit 24: PID56 */
|
||||
# define PMC_PID57 (1 << 25) /* Bit 25: PID57 */
|
||||
# define PMC_PID58 (1 << 26) /* Bit 26: PID58 */
|
||||
# define PMC_PID59 (1 << 27) /* Bit 27: PID59 */
|
||||
# define PMC_PID60 (1 << 28) /* Bit 28: PID60 */
|
||||
|
||||
/* Peripheral Control Register */
|
||||
|
||||
#define PMC_PCR_PID_SHIFT (0) /* Bits 0-5: Peripheral ID */
|
||||
#define PMC_PCR_PID_MASK (63 < PMC_PCR_PID_SHIFT)
|
||||
#define PMC_PCR_CMD (1 << 12) /* Bit 12: Command */
|
||||
#define PMC_PCR_DIV_SHIFT (16) /* Bits 16-17: Divisor Value */
|
||||
#define PMC_PCR_DIV_MASK (3 < PMC_PCR_DIV_SHIFT)
|
||||
# define PMC_PCR_DIV1 (0 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */
|
||||
# define PMC_PCR_DIV2 (1 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */
|
||||
# define PMC_PCR_DIV4 (2 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */
|
||||
# define PMC_PCR_DIV8 (3 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/8 */
|
||||
#define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */
|
||||
|
||||
/* Oscillator Calibration Register */
|
||||
|
||||
#define PMC_OCR_CAL4_SHIFT (0) /* Bits 0-6: 4MHzRC Oscillator Calibration */
|
||||
#define PMC_OCR_CAL4_MASK (0x7f << PMC_OCR_CAL4_SHIFT)
|
||||
# define PMC_OCR_CAL4(n) ((uint32_t)(n) << PMC_OCR_CAL4_SHIFT)
|
||||
#define PMC_OCR_SEL4 (1 << 7) /* Bit 7: Select 4MHz RC Oscillator Calibration */
|
||||
#define PMC_OCR_CAL8_SHIFT (8) /* Bits 8-14: 8MHzRC Oscillator Calibration */
|
||||
#define PMC_OCR_CAL8_MASK (0x7f << PMC_OCR_CAL8_SHIFT)
|
||||
# define PMC_OCR_CAL8(n) ((uint32_t)(n) << PMC_OCR_CAL8_SHIFT)
|
||||
#define PMC_OCR_SEL8 (1 << 15) /* Bit 15: Select 8MHz RC Oscillator Calibration */
|
||||
#define PMC_OCR_CAL12_SHIFT (16) /* Bits 16-22: 12MHzRC Oscillator Calibration */
|
||||
#define PMC_OCR_CAL12_MASK (0x7f << PMC_OCR_CAL12_SHIFT)
|
||||
# define PMC_OCR_CAL12(n) ((uint32_t)(n) << PMC_OCR_CAL12_SHIFT)
|
||||
#define PMC_OCR_SEL12 (1 << 23) /* Bit 23: Select 12MHz RC Oscillator Calibration */
|
||||
|
||||
/* SleepWalking Enable Register 0: Use PMC_PIDL definitions */
|
||||
/* SleepWalking Disable Register 0: Use PMC_PIDL definitions */
|
||||
/* SleepWalking Status Register 0: Use PMC_PIDL definitions */
|
||||
/* SleepWalking Activity Status Register 0: Use PMC_PIDL definitions */
|
||||
|
||||
/* SleepWalking Enable Register 1: Use PMC_PIDH definitions */
|
||||
/* SleepWalking Disable Register 1: Use PMC_PIDH definitions */
|
||||
/* SleepWalking Status Register 1: Use PMC_PIDH definitions */
|
||||
/* SleepWalking Activity Status Register 1: Use PMC_PIDH definitions */
|
||||
|
||||
/* SleepWalking Activity In Progress Register */
|
||||
|
||||
#define PMC_SLPWK_AIPR_AIP (0) /* Bit 0: Activity in progress */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_PMC_H */
|
||||
88
arch/arm/src/samv7/sam_periphclks.h
Normal file
88
arch/arm/src/samv7/sam_periphclks.h
Normal file
@ -0,0 +1,88 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/samv7/sam_periphclks.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_PERIPHCLKS_H
|
||||
#define __ARCH_ARM_SRC_SAMV7_SAM_PERIPHCLKS_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAMV71)
|
||||
# include "samv71_periphclks.h"
|
||||
#else
|
||||
# error Unrecognized SAMV7 architecture
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_PERIPHCLKS_H */
|
||||
227
arch/arm/src/samv7/samv71_periphclks.h
Normal file
227
arch/arm/src/samv7/samv71_periphclks.h
Normal file
@ -0,0 +1,227 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/samv7/sam4e_periphclks.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMV7_SAMV71_PERIPHCLKS_H
|
||||
#define __ARCH_ARM_SRC_SAMV7_SAMV71_PERIPHCLKS_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/irq.h>
|
||||
#include "chip/sam_pmc.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Helper macros */
|
||||
|
||||
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
|
||||
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
|
||||
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
|
||||
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
|
||||
|
||||
#define sam_supc_enableclk()
|
||||
#define sam_rstc_enableclk()
|
||||
#define sam_rtc_enableclk()
|
||||
#define sam_rtt_enableclk()
|
||||
#define sam_wdt0_enableclk()
|
||||
#define sam_pmc_enableclk()
|
||||
#define sam_efc_enableclk()
|
||||
|
||||
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
|
||||
#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC)
|
||||
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
|
||||
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
|
||||
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
|
||||
#define sam_hsmci_enableclk() sam_enableperiph0(SAM_PID_HSMCI)
|
||||
#define sam_twihs0_enableclk() sam_enableperiph0(SAM_PID_TWIHS0)
|
||||
#define sam_twihs1_enableclk() sam_enableperiph0(SAM_PID_TWIHS1)
|
||||
#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
|
||||
#define sam_ssc_enableclk() sam_enableperiph0(SAM_PID_SSC)
|
||||
#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
|
||||
#define sam_tc2_enableclk() sam_enableperiph0(SAM_PID_TC2)
|
||||
#define sam_tc3_enableclk() sam_enableperiph0(SAM_PID_TC3)
|
||||
#define sam_tc4_enableclk() sam_enableperiph0(SAM_PID_TC4)
|
||||
#define sam_tc5_enableclk() sam_enableperiph0(SAM_PID_TC5)
|
||||
#define sam_afec0_enableclk() sam_enableperiph0(SAM_PID_AFEC0)
|
||||
#define sam_dacc_enableclk() sam_enableperiph0(SAM_PID_DACC)
|
||||
#define sam_pwm0_enableclk() sam_enableperiph0(SAM_PID_PWM0)
|
||||
|
||||
#define sam_icm_enableclk() sam_enableperiph1(SAM_PID_ICM)
|
||||
#define sam_acc_enableclk() sam_enableperiph1(SAM_PID_ACC)
|
||||
#define sam_usbhs_enableclk() sam_enableperiph1(SAM_PID_USBHS)
|
||||
#define sam_mcan00_enableclk() sam_enableperiph1(SAM_PID_MCAN00)
|
||||
#define sam_mcan01_enableclk()
|
||||
#define sam_mcan10_enableclk() sam_enableperiph1(SAM_PID_MCAN10)
|
||||
#define sam_mcan11_enableclk()
|
||||
#define sam_emac_enableclk() sam_enableperiph1(SAM_PID_EMAC)
|
||||
#define sam_afec1_enableclk() sam_enableperiph1(SAM_PID_AFEC1)
|
||||
#define sam_twihs2_enableclk() sam_enableperiph1(SAM_PID_TWIHS2)
|
||||
#define sam_spi1_enableclk() sam_enableperiph1(SAM_PID_SPI1)
|
||||
#define sam_spi1_enableclk() sam_enableperiph1(SAM_PID_QSPI)
|
||||
#define sam_uart2_enableclk() sam_enableperiph1(SAM_PID_UART2)
|
||||
#define sam_uart3_enableclk() sam_enableperiph1(SAM_PID_UART3)
|
||||
#define sam_uart4_enableclk() sam_enableperiph1(SAM_PID_UART4)
|
||||
#define sam_tc6_enableclk() sam_enableperiph1(SAM_PID_TC6)
|
||||
#define sam_tc7_enableclk() sam_enableperiph1(SAM_PID_TC7)
|
||||
#define sam_tc8_enableclk() sam_enableperiph1(SAM_PID_TC8)
|
||||
#define sam_tc9_enableclk() sam_enableperiph1(SAM_PID_TC9)
|
||||
#define sam_tc10_enableclk() sam_enableperiph1(SAM_PID_TC10)
|
||||
#define sam_tc11_enableclk() sam_enableperiph1(SAM_PID_TC11)
|
||||
#define sam_mlb0_enableclk() sam_enableperiph1(SAM_PID_MLB0)
|
||||
#define sam_mlb1_enableclk()
|
||||
#define sam_aes_enableclk() sam_enableperiph1(SAM_PID_AES)
|
||||
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
|
||||
#define sam_xdmac_enableclk() sam_enableperiph1(SAM_PID_XDMAC)
|
||||
#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
|
||||
#define sam_pwm1_enableclk() sam_enableperiph1(SAM_PID_PWM1)
|
||||
#define sam_fpu_enableclk()
|
||||
#define sam_sdramc_enableclk()
|
||||
#define sam_wdt1_enableclk()
|
||||
|
||||
#define sam_ccw_enableclk()
|
||||
|
||||
#define sam_supc_disableclk()
|
||||
#define sam_rstc_disableclk()
|
||||
#define sam_rtc_disableclk()
|
||||
#define sam_rtt_disableclk()
|
||||
#define sam_wdt0_disableclk()
|
||||
#define sam_pmc_disableclk()
|
||||
#define sam_efc_disableclk()
|
||||
|
||||
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
|
||||
#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC)
|
||||
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
|
||||
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
|
||||
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
|
||||
#define sam_hsmci_disableclk() sam_disableperiph0(SAM_PID_HSMCI)
|
||||
#define sam_twihs0_disableclk() sam_disableperiph0(SAM_PID_TWIHS0)
|
||||
#define sam_twihs1_disableclk() sam_disableperiph0(SAM_PID_TWIHS1)
|
||||
#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
|
||||
#define sam_ssc_disableclk() sam_disableperiph0(SAM_PID_SSC)
|
||||
#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
|
||||
#define sam_tc2_disableclk() sam_disableperiph0(SAM_PID_TC2)
|
||||
#define sam_tc3_disableclk() sam_disableperiph0(SAM_PID_TC3)
|
||||
#define sam_tc4_disableclk() sam_disableperiph0(SAM_PID_TC4)
|
||||
#define sam_tc5_disableclk() sam_disableperiph0(SAM_PID_TC5)
|
||||
#define sam_afec0_disableclk() sam_disableperiph0(SAM_PID_AFEC0)
|
||||
#define sam_dacc_disableclk() sam_disableperiph0(SAM_PID_DACC)
|
||||
#define sam_pwm0_disableclk() sam_disableperiph0(SAM_PID_PWM0)
|
||||
|
||||
#define sam_icm_disableclk() sam_disableperiph1(SAM_PID_ICM)
|
||||
#define sam_acc_disableclk() sam_disableperiph1(SAM_PID_ACC)
|
||||
#define sam_usbhs_disableclk() sam_disableperiph1(SAM_PID_USBHS)
|
||||
#define sam_mcan00_disableclk() sam_disableperiph1(SAM_PID_MCAN00)
|
||||
#define sam_mcan01_disableclk()
|
||||
#define sam_mcan10_disableclk() sam_disableperiph1(SAM_PID_MCAN10)
|
||||
#define sam_mcan11_disableclk()
|
||||
#define sam_emac_disableclk() sam_disableperiph1(SAM_PID_EMAC)
|
||||
#define sam_afec1_disableclk() sam_disableperiph1(SAM_PID_AFEC1)
|
||||
#define sam_twihs2_disableclk() sam_disableperiph1(SAM_PID_TWIHS2)
|
||||
#define sam_spi1_disableclk() sam_disableperiph1(SAM_PID_SPI1)
|
||||
#define sam_spi1_disableclk() sam_disableperiph1(SAM_PID_QSPI)
|
||||
#define sam_uart2_disableclk() sam_disableperiph1(SAM_PID_UART2)
|
||||
#define sam_uart3_disableclk() sam_disableperiph1(SAM_PID_UART3)
|
||||
#define sam_uart4_disableclk() sam_disableperiph1(SAM_PID_UART4)
|
||||
#define sam_tc6_disableclk() sam_disableperiph1(SAM_PID_TC6)
|
||||
#define sam_tc7_disableclk() sam_disableperiph1(SAM_PID_TC7)
|
||||
#define sam_tc8_disableclk() sam_disableperiph1(SAM_PID_TC8)
|
||||
#define sam_tc9_disableclk() sam_disableperiph1(SAM_PID_TC9)
|
||||
#define sam_tc10_disableclk() sam_disableperiph1(SAM_PID_TC10)
|
||||
#define sam_tc11_disableclk() sam_disableperiph1(SAM_PID_TC11)
|
||||
#define sam_mlb0_disableclk() sam_disableperiph1(SAM_PID_MLB0)
|
||||
#define sam_mlb1_disableclk()
|
||||
#define sam_aes_disableclk() sam_disableperiph1(SAM_PID_AES)
|
||||
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
|
||||
#define sam_xdmac_disableclk() sam_disableperiph1(SAM_PID_XDMAC)
|
||||
#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
|
||||
#define sam_pwm1_disableclk() sam_disableperiph1(SAM_PID_PWM1)
|
||||
#define sam_fpu_disableclk()
|
||||
#define sam_sdramc_disableclk()
|
||||
#define sam_wdt1_disableclk()
|
||||
|
||||
#define sam_ccw_disableclk()
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_SAMV71_PERIPHCLKS_H */
|
||||
Loading…
Reference in New Issue
Block a user