More PIC32 header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3611 42af7a65-404d-4744-a932-0658087f49c3
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/****************************************************************************
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* arch/avr/include/arch.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/arch.h
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*/
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#ifndef __ARCH_AVR_INCLUDE_ARCH_H
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#define __ARCH_AVR_INCLUDE_ARCH_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ARCH_AVR_INCLUDE_ARCH_H */
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216
arch/mips/src/pic32mx/pic32mx-i2c.h
Executable file
216
arch/mips/src/pic32mx/pic32mx-i2c.h
Executable file
@ -0,0 +1,216 @@
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/************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-i2c.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx-memorymap.h"
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/************************************************************************************
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* Pre-Processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define PIC32MX_I2C_CON_OFFSET 0x0000 /* I2C control register */
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#define PIC32MX_I2C_CONCLR_OFFSET 0x0004 /* I2C control clear register */
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#define PIC32MX_I2C_CONSET_OFFSET 0x0008 /* I2C control set register */
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#define PIC32MX_I2C_CONINV_OFFSET 0x000c /* I2C control invert register */
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#define PIC32MX_I2C_STAT_OFFSET 0x0010 /* I2C status register */
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#define PIC32MX_I2C_STATCLR_OFFSET 0x0014 /* I2C status clear register */
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#define PIC32MX_I2C_STATSET_OFFSET 0x0018 /* I2C status set register */
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#define PIC32MX_I2C_STATINV_OFFSET 0x001c /* I2C status invert register */
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#define PIC32MX_I2C_ADD_OFFSET 0x0020 /* I2C address register */
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#define PIC32MX_I2C_ADDCLR_OFFSET 0x0024 /* I2C address clear register */
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#define PIC32MX_I2C_ADDSET_OFFSET 0x0028 /* I2C address set register */
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#define PIC32MX_I2C_ADDINV_OFFSET 0x002c /* I2C address invert register */
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#define PIC32MX_I2C_MSK_OFFSET 0x0030 /* I2C address mask register */
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#define PIC32MX_I2C_MSKCLR_OFFSET 0x0034 /* I2C address mask clear register */
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#define PIC32MX_I2C_MSKSET_OFFSET 0x0038 /* I2C address mask set register */
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#define PIC32MX_I2C_MSKINV_OFFSET 0x003c /* I2C address mask invert register */
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#define PIC32MX_I2C_BRG_OFFSET 0x0040 /* Baud rate generator reload register */
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#define PIC32MX_I2C_BRGSET_OFFSET 0x0044 /* Baud rate generator reload clear register */
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#define PIC32MX_I2C_BRGCLR_OFFSET 0x0048 /* Baud rate generator reload set register */
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#define PIC32MX_I2C_BRGINV_OFFSET 0x004c /* Baud rate generator reload invert register */
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#define PIC32MX_I2C_TRN_OFFSET 0x0050 /* I2C transmit register */
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#define PIC32MX_I2C_TRNCLR_OFFSET 0x0054 /* I2C transmit clear register */
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#define PIC32MX_I2C_TRNSET_OFFSET 0x0058 /* I2C transmit set register */
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#define PIC32MX_I2C_TRNINV_OFFSET 0x005c /* I2C transmit invert register */
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#define PIC32MX_I2C_RCV_OFFSET 0x0060 /* I2C receive buffer register */
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/* Register Addresses ***************************************************************/
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#define PIC32MX_I2C1_CON (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CON_OFFSET)
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#define PIC32MX_I2C1_CONCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
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#define PIC32MX_I2C1_CONSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
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#define PIC32MX_I2C1_CONINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
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#define PIC32MX_I2C1_STAT (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STAT_OFFSET)
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#define PIC32MX_I2C1_STATCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
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#define PIC32MX_I2C1_STATSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
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#define PIC32MX_I2C1_STATINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
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#define PIC32MX_I2C1_ADD (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADD_OFFSET)
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#define PIC32MX_I2C1_ADDCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
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#define PIC32MX_I2C1_ADDSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
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#define PIC32MX_I2C1_ADDINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
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#define PIC32MX_I2C1_MSK (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSK_OFFSET)
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#define PIC32MX_I2C1_MSKCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
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#define PIC32MX_I2C1_MSKSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
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#define PIC32MX_I2C1_MSKINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
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#define PIC32MX_I2C1_BRG (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRG_OFFSET)
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#define PIC32MX_I2C1_BRGSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
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#define PIC32MX_I2C1_BRGCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
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#define PIC32MX_I2C1_BRGINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
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#define PIC32MX_I2C1_TRN (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRN_OFFSET)
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#define PIC32MX_I2C1_TRNCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
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#define PIC32MX_I2C1_TRNSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
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#define PIC32MX_I2C1_TRNINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
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#define PIC32MX_I2C1_RCV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_RCV_OFFSET)
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#define PIC32MX_I2C2_CON (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CON_OFFSET)
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#define PIC32MX_I2C2_CONCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
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#define PIC32MX_I2C2_CONSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
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#define PIC32MX_I2C2_CONINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
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#define PIC32MX_I2C2_STAT (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STAT_OFFSET)
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#define PIC32MX_I2C2_STATCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
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#define PIC32MX_I2C2_STATSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
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#define PIC32MX_I2C2_STATINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
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#define PIC32MX_I2C2_ADD (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADD_OFFSET)
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#define PIC32MX_I2C2_ADDCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
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#define PIC32MX_I2C2_ADDSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
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#define PIC32MX_I2C2_ADDINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
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#define PIC32MX_I2C2_MSK (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSK_OFFSET)
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#define PIC32MX_I2C2_MSKCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
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#define PIC32MX_I2C2_MSKSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
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#define PIC32MX_I2C2_MSKINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
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#define PIC32MX_I2C2_BRG (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRG_OFFSET)
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#define PIC32MX_I2C2_BRGSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
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#define PIC32MX_I2C2_BRGCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
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#define PIC32MX_I2C2_BRGINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
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#define PIC32MX_I2C2_TRN (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRN_OFFSET)
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#define PIC32MX_I2C2_TRNCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
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#define PIC32MX_I2C2_TRNSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
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#define PIC32MX_I2C2_TRNINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
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#define PIC32MX_I2C2_RCV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_RCV_OFFSET)
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/* Register Bit-Field Definitions ***************************************************/
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/* I2C control register */
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#define I2C_CON_SEN (1 << 0) /* Bit 0: Start condition enable */
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#define I2C_CON_RSEN (1 << 1) /* Bit 1: Restart condition enable */
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#define I2C_CON_PEN (1 << 2) /* Bit 2: Stop condition enable */
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#define I2C_CON_RCEN (1 << 3) /* Bit 3: Receive enable */
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#define I2C_CON_ACKEN (1 << 4) /* Bit 4: Acknowledge sequence enable */
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#define I2C_CON_ACKDT (1 << 5) /* Bit 5: Acknowledge data */
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#define I2C_CON_STREN (1 << 6) /* Bit 6: SCL clock stretch enable */
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#define I2C_CON_GCEN (1 << 7) /* Bit 7: General call enable */
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#define I2C_CON_SMEN (1 << 8) /* Bit 8: SMBus input levels disable */
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#define I2C_CON_DISSLW (1 << 9) /* Bit 9: Slew rate control disable */
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#define I2C_CON_A10M (1 << 10) /* Bit 10: 10-bit slave addrewss flag */
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#define I2C_CON_STRICT (1 << 11) /* Bit 11: Strict I2C reserved address rules enable */
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#define I2C_CON_SCLREL (1 << 12) /* Bit 12: SCL release control */
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#define I2C_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
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#define I2C_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug mode control */
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#define I2C_CON_ON (1 << 15) /* Bit 15: I2C enable */
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/* I2C status register */
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#define I2C_STAT_TBF (1 << 0) /* Bit 0: Transmit buffer full */
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#define I2C_STAT_RBF (1 << 1) /* Bit 1: Receive buffer full */
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#define I2C_STAT_RW (1 << 2) /* Bit 2: Read/write information */
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#define I2C_STAT_S (1 << 3) /* Bit 3: Start */
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#define I2C_STAT_P (1 << 4) /* Bit 4: Stop */
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#define I2C_STAT_DA (1 << 5) /* Bit 5: Data/address */
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#define I2C_STAT_I2COV (1 << 6) /* Bit 6: I2C overflow status */
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#define I2C_STAT_IWCOL (1 << 7) /* Bit 7: Write collision detect */
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#define I2C_STAT_ADD10 (1 << 8) /* Bit 8: 10-bit address status */
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#define I2C_STAT_GCSTAT (1 << 9) /* Bit 9: General call status */
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#define I2C_STAT_BCL (1 << 10) /* Bit 10: Master bus collision detect */
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#define I2C_STAT_TRSTAT (1 << 14) /* Bit 14: Transmit status */
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#define I2C_STAT_ACKSTAT (1 << 15) /* Bit 15: Acknowledge status */
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/* I2C address register */
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#define I2C_ADD_MASK 0x3ff /* 10-bit I2C address */
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/* I2C address mask register */
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#define I2C_MSK_MASK 0x3ff /* 10-bit I2C address mask */
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/* Baud rate generator reload register */
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#define I2C_BRG_MASK 0xfff /* 12-bit I2C BRG value */
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/* I2C transmit register */
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#define I2C_TRN_MASK 0xff /* 8-bit transmit data */
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/* I2C receive buffer register */
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#define I2C_RCV_MASK 0xff /* 8-bit receive data */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H */
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@ -123,7 +123,7 @@
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/* Parallel Master Register Base Address */
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# define PCI32MX_PMSTR_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000)
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# define PCI32MX_PMP_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000)
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/* ADC Register Base Addresses */
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241
arch/mips/src/pic32mx/pic32mx-pmp.h
Executable file
241
arch/mips/src/pic32mx/pic32mx-pmp.h
Executable file
@ -0,0 +1,241 @@
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/************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-pmp.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "pic32mx-memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
************************************************************************************/
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define PIC32MX_PMP_CON_OFFSET 0x0000 /* Parallel Port Control Register */
|
||||
#define PIC32MX_PMP_CONCLR_OFFSET 0x0000 /* Parallel Port Control Clear Register */
|
||||
#define PIC32MX_PMP_CONSET_OFFSET 0x0000 /* Parallel Port Control Set Register */
|
||||
#define PIC32MX_PMP_CONINV_OFFSET 0x0000 /* Parallel Port Control Invert Register */
|
||||
#define PIC32MX_PMP_MODE_OFFSET 0x0000 /* Parallel Port Mode Register */
|
||||
#define PIC32MX_PMP_MODECLR_OFFSET 0x0000 /* Parallel Port Mode Clear Register */
|
||||
#define PIC32MX_PMP_MODESET_OFFSET 0x0000 /* Parallel Port Mode Set Register */
|
||||
#define PIC32MX_PMP_MODEINV_OFFSET 0x0000 /* Parallel Port Mode Invert Register */
|
||||
#define PIC32MX_PMP_ADDR_OFFSET 0x0000 /* Parallel Port Address Register */
|
||||
#define PIC32MX_PMP_ADDRCLR_OFFSET 0x0000 /* Parallel Port Address Clear Register */
|
||||
#define PIC32MX_PMP_ADDRSET_OFFSET 0x0000 /* Parallel Port Address Set Register */
|
||||
#define PIC32MX_PMP_ADDRINV_OFFSET 0x0000 /* Parallel Port Address Invert Register */
|
||||
#define PIC32MX_PMP_DOUT_OFFSET 0x0000 /* Parallel Port Data Output Register */
|
||||
#define PIC32MX_PMP_DOUTCLR_OFFSET 0x0000 /* Parallel Port Data Output Clear Register */
|
||||
#define PIC32MX_PMP_DOUTSET_OFFSET 0x0000 /* Parallel Port Data Output Set Register */
|
||||
#define PIC32MX_PMP_DOUTINV_OFFSET 0x0000 /* Parallel Port Data Output Invert Register */
|
||||
#define PIC32MX_PMP_DIN_OFFSET 0x0000 /* Parallel Port Data Input Register */
|
||||
#define PIC32MX_PMP_DINCLR_OFFSET 0x0000 /* Parallel Port Data Input Clear Register */
|
||||
#define PIC32MX_PMP_DINSET_OFFSET 0x0000 /* Parallel Port Data Input Set Register */
|
||||
#define PIC32MX_PMP_DININV_OFFSET 0x0000 /* Parallel Port Data Input Invert Register */
|
||||
#define PIC32MX_PMP_AEN_OFFSET 0x0000 /* Parallel Port Pin Enable Register */
|
||||
#define PIC32MX_PMP_AENCLR_OFFSET 0x0000 /* Parallel Port Pin Enable Clear Register */
|
||||
#define PIC32MX_PMP_AENSET_OFFSET 0x0000 /* Parallel Port Pin Enable Set Register */
|
||||
#define PIC32MX_PMP_AENINV_OFFSET 0x0000 /* Parallel Port Pin Enable Invert Register */
|
||||
#define PIC32MX_PMP_STAT_OFFSET 0x0000 /* Parallel Port Status Register */
|
||||
#define PIC32MX_PMP_STATCLR_OFFSET 0x0000 /* Parallel Port Status Clear Register */
|
||||
#define PIC32MX_PMP_STATSET_OFFSET 0x0000 /* Parallel Port Status Set Register */
|
||||
#define PIC32MX_PMP_STATINV_OFFSET 0x0000 /* Parallel Port Status Invert Register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define PIC32MX_PMP_CON (PCI32MX_PMP_K1BASE+PIC32MX_PMP_CON_OFFSET)
|
||||
#define PIC32MX_PMP_CONCLR (PCI32MX_PMP_K1BASE+PIC32MX_PMP_CONCLR_OFFSET)
|
||||
#define PIC32MX_PMP_CONSET (PCI32MX_PMP_K1BASE+PIC32MX_PMP_CONSET_OFFSET)
|
||||
#define PIC32MX_PMP_CONINV (PCI32MX_PMP_K1BASE+PIC32MX_PMP_CONINV_OFFSET)
|
||||
#define PIC32MX_PMP_MODE (PCI32MX_PMP_K1BASE+PIC32MX_PMP_MODE_OFFSET)
|
||||
#define PIC32MX_PMP_MODECLR (PCI32MX_PMP_K1BASE+PIC32MX_PMP_MODECLR_OFFSET)
|
||||
#define PIC32MX_PMP_MODESET (PCI32MX_PMP_K1BASE+PIC32MX_PMP_MODESET_OFFSET)
|
||||
#define PIC32MX_PMP_MODEINV (PCI32MX_PMP_K1BASE+PIC32MX_PMP_MODEINV_OFFSET)
|
||||
#define PIC32MX_PMP_ADDR (PCI32MX_PMP_K1BASE+PIC32MX_PMP_ADDR_OFFSET)
|
||||
#define PIC32MX_PMP_ADDRCLR (PCI32MX_PMP_K1BASE+PIC32MX_PMP_ADDRCLR_OFFSET)
|
||||
#define PIC32MX_PMP_ADDRSET (PCI32MX_PMP_K1BASE+PIC32MX_PMP_ADDRSET_OFFSET)
|
||||
#define PIC32MX_PMP_ADDRINV (PCI32MX_PMP_K1BASE+PIC32MX_PMP_ADDRINV_OFFSET)
|
||||
#define PIC32MX_PMP_DOUT (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DOUT_OFFSET)
|
||||
#define PIC32MX_PMP_DOUTCLR (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DOUTCLR_OFFSET)
|
||||
#define PIC32MX_PMP_DOUTSET (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DOUTSET_OFFSET)
|
||||
#define PIC32MX_PMP_DOUTINV (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DOUTINV_OFFSET)
|
||||
#define PIC32MX_PMP_DIN (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DIN_OFFSET)
|
||||
#define PIC32MX_PMP_DINCLR (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DINCLR_OFFSET)
|
||||
#define PIC32MX_PMP_DINSET (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DINSET_OFFSET)
|
||||
#define PIC32MX_PMP_DININV (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DININV_OFFSET)
|
||||
#define PIC32MX_PMP_AEN (PCI32MX_PMP_K1BASE+PIC32MX_PMP_AEN_OFFSET)
|
||||
#define PIC32MX_PMP_AENCLR (PCI32MX_PMP_K1BASE+PIC32MX_PMP_AENCLR_OFFSET)
|
||||
#define PIC32MX_PMP_AENSET (PCI32MX_PMP_K1BASE+PIC32MX_PMP_AENSET_OFFSET)
|
||||
#define PIC32MX_PMP_AENINV (PCI32MX_PMP_K1BASE+PIC32MX_PMP_AENINV_OFFSET)
|
||||
#define PIC32MX_PMP_STAT (PCI32MX_PMP_K1BASE+PIC32MX_PMP_STAT_OFFSET)
|
||||
#define PIC32MX_PMP_STATCLR (PCI32MX_PMP_K1BASE+PIC32MX_PMP_STATCLR_OFFSET)
|
||||
#define PIC32MX_PMP_STATSET (PCI32MX_PMP_K1BASE+PIC32MX_PMP_STATSET_OFFSET)
|
||||
#define PIC32MX_PMP_STATINV (PCI32MX_PMP_K1BASE+PIC32MX_PMP_STATINV_OFFSET)
|
||||
|
||||
/* Register Bit-Field Definitions ***************************************************/
|
||||
|
||||
/* Parallel Port Control Register */
|
||||
|
||||
#define PMP_CON_RDSP (1 << 0) /* Bit 0: Read strobe polarity */
|
||||
#define PMP_CON_WRSP (1 << 1) /* Bit 1: Write strobe polarity */
|
||||
#define PMP_CON_CS1P (1 << 3) /* Bit 3: Chip select 0 polarity */
|
||||
#define PMP_CON_CS2P (1 << 4) /* Bit 4: Chip select 1 polarity */
|
||||
#define PMP_CON_ALP (1 << 5) /* Bit 5: Address latch polarity */
|
||||
#define PMP_CON_CSF_SHIFT (6) /* Bits 6-7: Chip select function */
|
||||
#define PMP_CON_CSF_MASK (3 << PMP_CON_CSF_SHIFT)
|
||||
#define PMP_CON_CSF_ADDR1415 (0 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = address bits 15 and 14 */
|
||||
#define PMP_CON_CSF_CS2ADDR14 (1 << PMP_CON_CSF_SHIFT) /* PMCS2 = Chip Select, PMCS1 = address bit 14 */
|
||||
#define PMP_CON_CSF_CS12 (2 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = Chip Select */
|
||||
#define PMP_CON_PTRDEN (1 << 8) /* Bit 8: Read/write strobe port enable */
|
||||
#define PMP_CON_PTWREN (1 << 9) /* Bit 9: Write enable strobe port enable */
|
||||
#define PMP_CON_PMPTTL (1 << 10) /* Bit 10: PMP module TTL input buffer select */
|
||||
#define PMP_CON_ADRMUX_SHIFT (11) /* Bits 11-12: Address/data multiplexing selection */
|
||||
#define PMP_CON_ADRMUX_MASK (3 << PMP_CON_ADRMUX_SHIFT)
|
||||
# define PMP_CON_ADRMUX_NONE (0 << PMP_CON_ADRMUX_SHIFT) /* Address and data appear separate */
|
||||
# define PMP_CON_ADRMUX_BYTE (1 << PMP_CON_ADRMUX_SHIFT) /* LS address are mux'ed on PMD 7:0 MS on PMA 15:8 */
|
||||
# define PMP_CON_ADRMUX_MUX8 (2 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 7:0 */
|
||||
# define PMP_CON_ADRMUX_MUX16 (3 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 15:0 */
|
||||
#define PMP_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
|
||||
#define PMP_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
|
||||
#define PMP_CON_ON (1 << 15) /* Bit 15: Parallel master port enable */
|
||||
|
||||
/* Parallel Port Mode Register */
|
||||
|
||||
#define PMP_MODE_WAITE_SHIFT (0) /* Bits 0-1: Data hold after R/W strobe wait states */
|
||||
#define PMP_MODE_WAITE_MASK (3 << PMP_MODE_WAITE_SHIFT)
|
||||
# define PMP_MODE_WAITE_WR(n) ((n-1) << PMP_MODE_WAITE_SHIFT) /* Wait of n TPB n=1..4 */
|
||||
# define PMP_MODE_WAITE_RD(n) ((n) << PMP_MODE_WAITE_SHIFT) /* Wait of n TPB n=0..3 */
|
||||
#define PMP_MODE_WAITM_SHIFT (2) /* Bits 2-5: Data R/W strobe wait states */
|
||||
#define PMP_MODE_WAITM_MASK (15 << PMP_MODE_WAITM_SHIFT)
|
||||
# define PMP_MODE_WAITM(n) ((n-1) << PMP_MODE_WAITM_SHIFT) /* Wait of n TPB n=1..16 */
|
||||
#define PMP_MODE_WAITB_SHIFT (6) /* Bits 6-7: Data setup to R/W strobe wait states */
|
||||
#define PMP_MODE_WAITB_MASK (3 << PMP_MODE_WAITB_SHIFT)
|
||||
# define PMP_MODE_WAITB_1TPB (0 << PMP_MODE_WAITB_SHIFT) /* Data wait of 1 TPB */
|
||||
# define PMP_MODE_WAITB_2TPB (1 << PMP_MODE_WAITB_SHIFT) /* Data wait of 2 TPB */
|
||||
# define PMP_MODE_WAITB_3TPB (2 << PMP_MODE_WAITB_SHIFT) /* Data wait of 3 TPB */
|
||||
# define PMP_MODE_WAITB_4TPB (3 << PMP_MODE_WAITB_SHIFT) /* Data wait of 4 TPB */
|
||||
#define PMP_MODE_MODE_SHIFT (8) /* Bits 8-9: Parallel port mode select */
|
||||
#define PMP_MODE_MODE_MASK (3 << PMP_MODE_MODE_SHIFT)
|
||||
# define PMP_MODE_MODE_LEGACY (0 << PMP_MODE_MODE_SHIFT) /* Legacy parallel slave port */
|
||||
# define PMP_MODE_MODE_SLAVE (1 << PMP_MODE_MODE_SHIFT) /* Enhanced slave mode */
|
||||
# define PMP_MODE_MODE_MODE2 (2 << PMP_MODE_MODE_SHIFT) /* Master mode 2 */
|
||||
# define PMP_MODE_MODE_MODE1 (3 << PMP_MODE_MODE_SHIFT) /* Master mode 1 */
|
||||
#define PMP_MODE_MODE16 (1 << 10) /* Bit 10: 8/16-bit mode */
|
||||
#define PMP_MODE_INCM_SHIFT (11) /* Bits 11-12: Increment Mode */
|
||||
#define PMP_MODE_INCM_MASK (3 << PMP_MODE_INCM_MASK)
|
||||
# define PMP_MODE_INCM_NONE (0 << PMP_MODE_INCM_MASK) /* No incr or decr of addr */
|
||||
# define PMP_MODE_INCM_INCR (1 << PMP_MODE_INCM_MASK) /* Incr addr on R/W cycle */
|
||||
# define PMP_MODE_INCM_DECR (2 << PMP_MODE_INCM_MASK) /* Decr addr on R/Wcycle */
|
||||
# define PMP_MODE_INCM_SLAVE (3 << PMP_MODE_INCM_MASK) /* Slave mode auto-increment */
|
||||
#define PMP_MODE_IRQM_SHIFT (13) /* Bits 13-14: Interrupt request mode */
|
||||
#define PMP_MODE_IRQM_MASK (3 << PMP_MODE_IRQM_SHIFT)
|
||||
# define PMP_MODE_IRQM_NONE (0 << PMP_MODE_IRQM_SHIFT) /* No Interrupt generated */
|
||||
# define PMP_MODE_IRQM_RW (1 << PMP_MODE_IRQM_SHIFT) /* Interrupt at end of R/W cycle */
|
||||
# define PMP_MODE_IRQM_BUFFER (2 << PMP_MODE_IRQM_SHIFT) /* R/W buffer 3 or write PMA=11 */
|
||||
#define PMP_MODE_BUSY (1 << 15) /* Bit 15: Busy (master mode only) */
|
||||
|
||||
/* Parallel Port Address Register */
|
||||
|
||||
#define PMP_ADDR_ADDR_SHIFT (0) /* Bits 0-13: Destination address */
|
||||
#define PMP_ADDR_ADDR_MASK (0x3fff << PMP_ADDR_ADDR_SHIFT)
|
||||
#define PMP_ADDR_CS1EN (1 << 14) /* Bit 14: Chip select 1 */
|
||||
#define PMP_ADDR_CS2EN (1 << 15) /* Bit 15: Chip select 2 */
|
||||
|
||||
/* Parallel Port Data Output Register -- 32-bit data register */
|
||||
|
||||
/* Parallel Port Data Input Register -- 32-bit data register */
|
||||
|
||||
/* Parallel Port Pin Enable Register */
|
||||
|
||||
#define PMP_AEN_PTEN_SHIFT (0) /* Bits 0-15: xx */
|
||||
#define PMP_AEN_PTEN_MASK (0xffff << PMP_AEN_PTEN_SHIFT)
|
||||
|
||||
#define PMP_AEN_PMCSEN_SHIFT (14) /* PTEN 14-15: PMCSx Strobe enable */
|
||||
#define PMP_AEN_PMCSEN_MASK (3 << PMP_AEN_STROBEN_SHIFT)
|
||||
#define PMP_AEN_ADDR_SHIFT (2) /* PTEN 2-13: PMP address port enable */
|
||||
#define PMP_AEN_ADDR_MASK (0xfff << PMP_AEN_STROBEN_SHIFT)
|
||||
#define PMP_AEN_PMALEN_SHIFT (0) /* PTEN 0-1: PMALH/PMALL strobe enable */
|
||||
#define PMP_AEN_PMALEN_MASK (3 << PMP_AEN_STROBEN_SHIFT)
|
||||
|
||||
/* Parallel Port Status Register */
|
||||
|
||||
#define PMP_STAT_OBE(n) (1 << (n))
|
||||
#define PMP_STAT_OB0E (1 << 0) /* Bit 0: Output buffer 0 status empty bits */
|
||||
#define PMP_STAT_OB1E (1 << 1) /* Bit 1: Output buffer 1 status empty bits */
|
||||
#define PMP_STAT_OB2E (1 << 2) /* Bit 2: Output buffer 2 status empty bits */
|
||||
#define PMP_STAT_OB3E (1 << 3) /* Bit 3: Output buffer 3 status empty bits */
|
||||
#define PMP_STAT_OBUF (1 << 6) /* Bit 6: Output buffer underflow status */
|
||||
#define PMP_STAT_OBE (1 << 7) /* Bit 7: Output buffer empty status */
|
||||
#define PMP_STAT_IBF(n) (1 << (n+8))
|
||||
#define PMP_STAT_IB0F (1 << 8) /* Bit 8: Input buffer 0 status full */
|
||||
#define PMP_STAT_IB1F (1 << 9) /* Bit 9: Input buffer 1 status full */
|
||||
#define PMP_STAT_IB2F (1 << 10) /* Bit 10: Input buffer 2 status full */
|
||||
#define PMP_STAT_IB3F (1 << 11) /* Bit 11: Input buffer 3 status full */
|
||||
#define PMP_STAT_IBOV (1 << 14) /* Bit 14: Input buffer overflow status */
|
||||
#define PMP_STAT_IBF (1 << 15) /* Bit 15: Input buffer full status */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H */
|
||||
@ -56,7 +56,7 @@
|
||||
#define PIC32MX_RESET_RSWRST_OFFSET 0x0010 /* Software reset register */
|
||||
#define PIC32MX_RESET_RSWRSTCLR_OFFSET 0x0014 /* RSWRST clear register */
|
||||
#define PIC32MX_RESET_RSWRSTSET_OFFSET 0x0018 /* RSWRST set register */
|
||||
#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST nvert register */
|
||||
#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST invert register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
|
||||
@ -84,12 +84,56 @@
|
||||
|
||||
/****************************************************************************
|
||||
* Name: fputs
|
||||
*
|
||||
* Description:
|
||||
* fputs() writes the string s to stream, without its trailing '\0'.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* fputs() writes the string s to stream, without its
|
||||
* trailing '\0'.
|
||||
*/
|
||||
#ifdef CONFIG_STDIO_LINEBUFFER
|
||||
int fputs(FAR const char *s, FAR FILE *stream)
|
||||
{
|
||||
int nput;
|
||||
int ret;
|
||||
|
||||
/* Make sure that a string was provided. */
|
||||
|
||||
#ifdef CONFIG_DEBUG /* Most parameter checking is disabled if DEBUG is off */
|
||||
if (!s)
|
||||
{
|
||||
set_errno(EINVAL);
|
||||
return EOF;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Write the string. Loop until the null terminator is encountered */
|
||||
|
||||
for (nput = 0; *s; nput++, s++)
|
||||
{
|
||||
/* Write the next character to the stream buffer */
|
||||
|
||||
ret = lib_fwrite(s, 1, stream);
|
||||
if (ret <= 0)
|
||||
{
|
||||
return EOF;
|
||||
}
|
||||
|
||||
/* Flush the buffer if a newline was writen to the buffer */
|
||||
|
||||
if (*s == '\n')
|
||||
{
|
||||
ret = lib_fflush(stream, true);
|
||||
if (ret < 0)
|
||||
{
|
||||
return EOF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return nput;
|
||||
}
|
||||
|
||||
#else
|
||||
int fputs(FAR const char *s, FAR FILE *stream)
|
||||
{
|
||||
int ntowrite;
|
||||
@ -116,39 +160,11 @@ int fputs(FAR const char *s, FAR FILE *stream)
|
||||
|
||||
/* Write the string */
|
||||
|
||||
#ifdef CONFIG_STDIO_LINEBUFFER
|
||||
nput = ntowrite;
|
||||
while (ntowrite-- > 0)
|
||||
{
|
||||
ret = lib_fwrite(s, 1, stream);
|
||||
if (ret <= 0)
|
||||
{
|
||||
return EOF;
|
||||
}
|
||||
|
||||
/* Flush the buffer if a newline was put to the buffer */
|
||||
|
||||
if (*s == '\n')
|
||||
{
|
||||
ret = lib_fflush(stream, true);
|
||||
if (ret < 0)
|
||||
{
|
||||
return EOF;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set up for the next lib_fwrite() */
|
||||
|
||||
s++;
|
||||
}
|
||||
|
||||
return nput;
|
||||
#else
|
||||
nput = lib_fwrite(s, ntowrite, stream);
|
||||
if (nput < 0)
|
||||
{
|
||||
return EOF
|
||||
}
|
||||
return nput;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
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