SAM4L: Add DFLL0 support, add logic to set the power scaling mode, add support for RAM functions
This commit is contained in:
Gregory Nutt
parent
5052df2e69
commit
7207be4f84
@ -115,6 +115,7 @@ config ARCH_CHIP_NUC1XX
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config ARCH_CHIP_SAM34
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bool "Atmel AT91SAM3/SAM4"
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RAMFUNCS
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---help---
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Atmel AT91SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures
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@ -134,6 +134,7 @@ config ARCH_CHIP_SAM3U
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config ARCH_CHIP_SAM4L
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bool
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default n
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select ARCH_RAMFUNCS
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config ARCH_CHIP_SAM4S
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bool
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@ -110,6 +110,7 @@
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# define BPM_PMCON_PS1 (1 << BPM_PMCON_PS_SHIFT)
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# define BPM_PMCON_PS2 (2 << BPM_PMCON_PS_SHIFT)
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#define BPM_PMCON_PSCREQ (1 << 2) /* Bit 2: Power Scaling Change Request */
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#define BPM_PMCON_PSCM (1 << 3) /* Bit 3: Power Scaling Change Mode */
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#define BPM_PMCON_BKUP (1 << 8) /* Bit 8: BACKUP Mode */
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#define BPM_PMCON_RET (1 << 9) /* Bit 9: RETENTION Mode */
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#define BPM_PMCON_SLEEP_SHIFT (12) /* Bits 12-13: SLEEP mode Configuration */
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@ -250,10 +250,26 @@
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#define SCIF_DFLL0CONF_QLDIS (1 << 6) /* Bit 6: Quick Lock Disable */
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#define SCIF_DFLL0CONF_RANGE_SHIFT (16) /* Bits 16-17: Range Value */
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#define SCIF_DFLL0CONF_RANGE_MASK (3 << SCIF_DFLL0CONF_RANGE_SHIFT)
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# define SCIF_DFLL0CONF_RANGE(n) ((n) << SCIF_DFLL0CONF_RANGE_SHIFT)
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# define SCIF_DFLL0CONF_RANGE0 (0 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 96-150MHz */
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# define SCIF_DFLL0CONF_RANGE1 (1 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 50-110MHz */
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# define SCIF_DFLL0CONF_RANGE2 (2 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 25-55MHz */
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# define SCIF_DFLL0CONF_RANGE3 (3 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 20-30MHz */
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#define SCIF_DFLL0CONF_FCD (1 << 23) /* Bit 23: Fuse Calibration Done */
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#define SCIF_DFLL0CONF_CALIB_SHIFT (24) /* Bits 24-27: Calibration Value */
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#define SCIF_DFLL0CONF_CALIB_MASK (15 << SCIF_DFLL0CONF_CALIB_SHIFT)
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/* Min/max frequencies for each DFLL0 range */
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#define SCIF_DFLL0CONF_MAX_RANGE0 (150000000)
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#define SCIF_DFLL0CONF_MIN_RANGE0 (96000000)
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#define SCIF_DFLL0CONF_MAX_RANGE1 (110000000)
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#define SCIF_DFLL0CONF_MIN_RANGE1 (50000000)
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#define SCIF_DFLL0CONF_MAX_RANGE2 (55000000)
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#define SCIF_DFLL0CONF_MIN_RANGE2 (25000000)
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#define SCIF_DFLL0CONF_MAX_RANGE3 (30000000)
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#define SCIF_DFLL0CONF_MIN_RANGE3 (20000000)
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/* DFLL Value Register */
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#define SCIF_DFLL0VAL_FINE_SHIFT (0) /* Bits 0-7: Fine Value */
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@ -269,8 +285,10 @@
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#define SCIF_DFLL0STEP_FSTEP_SHIFT (0) /* Bits 0-7: Fine Maximum Step */
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#define SCIF_DFLL0STEP_FSTEP_MASK (0xff << SCIF_DFLL0STEP_FSTEP_SHIFT)
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# define SCIF_DFLL0STEP_FSTEP(n) ((n) << SCIF_DFLL0STEP_FSTEP_SHIFT)
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#define SCIF_DFLL0STEP_CSTEP_SHIFT (16) /* Bits 16-20: Coarse Maximum Step */
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#define SCIF_DFLL0STEP_CSTEP_MASK (31 << SCIF_DFLL0STEP_CSTEP_SHIFT)
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# define SCIF_DFLL0STEP_CSTEP(4) ((v) << SCIF_DFLL0STEP_CSTEP_SHIFT)
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/* DFLL0 Spread Spectrum Generator Control Register */
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@ -375,6 +393,7 @@
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# define SCIF_GCCTRL_OSCSEL_RC32K (13 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 32kHz RCOSC */
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#define SCIF_GCCTRL_DIV_SHIFT (16) /* Bits 16-31: Division Factor */
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#define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT)
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# define SCIF_GCCTRL_DIV(n) ((n) << SCIF_GCCTRL_DIV_SHIFT)
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/* 4/8/12MHz RC Oscillator Version Register */
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/* Generic Clock Prescaler Version Register */
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@ -56,8 +56,14 @@
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#include "sam_clockconfig.h"
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/****************************************************************************
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* Private Definitions
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#ifndef CONFIG_ARCH_RAMFUNCS
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# error "CONFIG_ARCH_RAMFUNCS must be defined"
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#endif
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/* Nominal frequencies in on-chip RC oscillators. These may frequencies
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* may vary with temperature changes.
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*/
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@ -395,6 +401,23 @@
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# define SAM_PLL0_OPTIONS 0
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# endif
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# endif
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/* DPLL0 reference clock */
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# if defined(BOARD_DFLL0_SOURCE_RCSYS)
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# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RCSYS
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# elif defined(BOARD_DFLL0_SOURCE_OSC32K)
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# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_OSC32K
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# elif define(BOARD_DFLL0_SOURCE_OSC0)
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# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_OSC0
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# elif define(BOARD_DFLL0_SOURCE_RC80M)
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# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RC80M
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# elif define(BOARD_DFLL0_SOURCE_RC32K)
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# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RC32K
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# else
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# error No DFLL0 source for reference clock defined
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# endif
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#endif
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/****************************************************************************
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@ -636,14 +659,14 @@ static inline void sam_enableglck9(void)
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#endif
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/****************************************************************************
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* Name: sam_enablepll0
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* Name: sam_enablepll0 (and its helper sam_pll0putreg())
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*
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* Description:
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* Initialiaze PLL0 settings per the definitions in the board.h file.
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*
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****************************************************************************/
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#ifdef SAM_CLOCK_PLL0
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#ifdef BOARD_SYSCLK_SOURCE_PLL0
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static inline void sam_pll0putreg(uint32_t regval, uint32_t regaddr,
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uint32_t regoffset)
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{
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@ -672,7 +695,7 @@ static inline void sam_enablepll0(void)
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regval = getreg32(SAM_SCIF_PLL0);
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regval &= ~(SCIF_PLL0_PLLOSC_MASK | SCIF_PLL0_PLLDIV_MASK | SCIF_PLL0_PLLMUL_MASK);
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regval |= ((SAM_PLL0_MUL - 1) << SCIF_PLL0_PLLMUL_SHIFT) |
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(BOARD_FDLL0_DIV << SCIF_PLL0_PLLDIV_SHIFT) |
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(BOARD_DFLL0_DIV << SCIF_PLL0_PLLDIV_SHIFT) |
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SCIF_PLL0_PLLCOUNT_MAX | SAM_PLL0_SOURCE;
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sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET);
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@ -688,6 +711,127 @@ static inline void sam_enablepll0(void)
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}
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#endif
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/****************************************************************************
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* Name: sam_enabledfll0 (and its helper sam_dfll0_putreg32())
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*
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* Description:
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* Initialiaze DFLL0 settings per the definitions in the board.h file.
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*
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****************************************************************************/
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#ifdef BOARD_SYSCLK_SOURCE_DFLL0
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static inline void sam_dfll0_putreg32(uint32_t regval, uint32_t regaddr,
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uint32_t regoffset)
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{
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/* Wait until DFLL0 is completes the last setting */
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while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0);
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/* Then unlock the register and write the next value */
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putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(regoffset),
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SAM_SCIF_UNLOCK);
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putreg32(regval, regaddr);
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}
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static inline void sam_enabledfll0(void)
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{
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uint32_t regval;
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uint32_t conf;
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/* Set up generic clock source with specified reference clock
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* and divider.
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*/
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putreg(0, SAM_SCIF_GCCTRL0);
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/* Set the generic clock 0 source */
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regval = getreg32(SAM_SCIF_GCCTRL0);
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regval &= ~SCIF_GCCTRL_OSCSEL_MASK;
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regval |= SAM_DFLLO_REFCLK;
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putreg32(regval, SAM_SCIF_GCCTRL0);
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/* Get the generic clock 0 divider */
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regval = getreg32(SAM_SCIF_GCCTRL0);
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regval &= ~(SCIF_GCCTRL_DIVEN | SCIF_GCCTRL_DIV_MASK);
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#if BOARD_DFLL0_DIV > 1
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regval |= SCIF_GCCTRL_DIVEN;
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regval |= SCIF_GCCTRL_DIV(((BOARD_DFLL0_DIV + 1) / 2) - 1);
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#endif
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putreg32(regval, SAM_SCIF_GCCTRL0);
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/* Sync before reading a dfll conf register */
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putreg32(SCIF_DFLL0SYNC_SYNC, SAM_SCIF_DFLL0SYNC);
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while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0);
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/* Select Closed Loop Mode */
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conf = getreg(SAM_SCIF_DFLL0CONF);
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conf &= ~SCIF_DFLL0CONF_RANGE_MASK;
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conf |= SCIF_DFLL0CONF_MODE;
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/* Select the DFLL0 Frequency Range */
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#if BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE3
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conf |= SCIF_DFLL0CONF_RANGE3;
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#elif BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE2
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conf |= SCIF_DFLL0CONF_RANGE2;
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#elif BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE1
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conf |= SCIF_DFLL0CONF_RANGE1;
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#else
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conf |= SCIF_DFLL0CONF_RANGE0;
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#ednif
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/* Enable the reference generic clock 0 */
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regval = getreg32(SAM_SCIF_GCCTRL0);
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regval |= SCIF_GCCTRL_CEN;
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putreg32(regval, SAM_SCIF_GCCTRL0);
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/* Enable DFLL0. Here we assume DFLL0RDY because the DFLL was disabled
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* before this function was called.
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*/
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putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_DFLL0CONF_OFFSET),
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SAM_SCIF_UNLOCK);
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putreg32(SCIF_DFLL0CONF_EN, SAM_SCIF_DFLL0CONF);
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/* Configure DFLL0. Note that now we do have to wait for DFLL0RDY before
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* every write.
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*
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* Set the initial coarse and fine step lengths to 4. If this is set
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* too high, DFLL0 may fail to lock.
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*/
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sam_dfll0_putreg32((SCIF_DFLL0STEP_CSTEP(4) | SCIF_DFLL0STEP_FSTEP(4),
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SAM_SCIF_DFLL0STEP,
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SAM_SCIF_DFLL0STEP_OFFSET);
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/* Set the DFLL0 multipler register */
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sam_dfll0_putreg32(BOARD_DFLL0_MUL, SAM_SCIF_DFLL0MUL,
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SAM_SCIF_DFLL0MUL_OFFSET);
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/* Set the multipler and spread spectrum generator control registers */
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sam_dfll0_putreg32(0, SAM_SCIF_DFLL0SSG, SAM_SCIF_DFLL0SSG_OFFSET);
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/* Finally, set the DFLL0 configuration */
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sam_dfll0_putreg32(conf | SCIF_DFLL0CONF_EN,
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SAM_SCIF_DFLL0CONF, SAM_SCIF_DFLL0CONF_OFFSET);
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/* Wait until we are locked on the fine value */
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while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0LOCKF) == 0);
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}
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#endif
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/****************************************************************************
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* Name: sam_setdividers
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*
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@ -762,7 +906,7 @@ static inline void sam_setdividers(void)
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*
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****************************************************************************/
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static void sam_fws(uint32_t cpuclock)
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static inline void sam_fws(uint32_t cpuclock, uint32_t psm, bool fastwkup)
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{
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uint32_t regval;
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@ -794,9 +938,50 @@ static inline void sam_mainclk(uint32_t mcsel)
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regval = getreg32(SAM_PM_MCCTRL);
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regval &= ~PM_MCCTRL_MCSEL_MASK;
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regval |= mcsel;
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_MCCTRL_OFFSET),
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SAM_PM_UNLOCK);
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putreg32(regval, SAM_PM_MCCTRL);
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}
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/****************************************************************************
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* Name: sam_setpsm (and its helper, sam_instantiatepsm())
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*
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* Description:
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* Switch to the selected power scaling mode.
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*
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****************************************************************************/
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static __ramfunc__ void sam_instantiatepsm(Bpm *bpm, uint32_t regval)
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{
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/* Set the BMP PCOM register (containing the new power scaling mode) */
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putreg32(BPM_UNLOCK_KEY(0xaa) | BPM_UNLOCK_ADDR(SAM_BPM_PMCON_OFFSET),
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SAM_BPM_UNLOCK);
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putreg32(regval, SAM_BPM_PMCON);
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/* Wait for new power scaling mode to become active. There should be
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* timeout on this wait.
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*/
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while ((getreg32(SAM_BPM_SR) & BPM_INT_PSOK) == 0);
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}
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static inline void sam_setpsm(uint32_t psm)
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{
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uint32_t regval;
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/* Setup the PMCON register content fo the new power scaling mode */
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regval = getreg32(SAM_BPM_PMCON);
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regval &= ~BPM_PMCON_PS_MASK;
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regval |= (psm | BPM_PMCON_PSCM | BPM_PMCON_PSCREQ);
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/* Then call the RAMFUNC sam_setpsm() to set the new power scaling mode */
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sam_instantiatepsm(bpm, regval);
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}
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/****************************************************************************
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* Name: sam_usbclock
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*
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@ -849,7 +1034,7 @@ static inline void sam_usbclock(void)
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void sam_clockconfig(void)
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{
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uint32_t regval;
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uint32_t bpmps;
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uint32_t psm;
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bool fastwkup;
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/* Enable clocking to the PICOCACHE */
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@ -884,9 +1069,11 @@ void sam_clockconfig(void)
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*/
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#ifdef CONFIG_SAM_FLASH_HSEN
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/* The high speed FLASH mode has been enabled. Select power scaling mode 2 */
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/* The high speed FLASH mode has been enabled. Select power scaling
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* mode 2, no fast wakeup.
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*/
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bpmps = BPM_PMCON_PS2;
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psm = BPM_PMCON_PS2;
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fastwkup = false;
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#else
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/* Not high speed mode. Check if we can go to power scaling mode 1. */
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@ -895,7 +1082,7 @@ void sam_clockconfig(void)
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{
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/* Yes.. Do we also need to enable fast wakeup? */
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bpmps = BPM_PMCON_PS1;
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psm = BPM_PMCON_PS1;
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if (BOARD_CPU_FREQUENCY > FLASH_MAXFREQ_PS1_HSDIS_FWS0)
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{
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/* Yes.. enable fast wakeup */
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@ -912,7 +1099,7 @@ void sam_clockconfig(void)
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}
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else
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{
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bpmps = BPM_PMCON_PS0;
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psm = BPM_PMCON_PS0;
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}
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#endif
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@ -972,11 +1159,13 @@ void sam_clockconfig(void)
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/* Since this function only executes at power up, we know that we are
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* already running from RCSYS.
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*/
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// sam_mainclk(PM_MCCTRL_MCSEL_RCSYS);
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#elif defined(BOARD_SYSCLK_SOURCE_OSC0)
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/* Set up FLASH wait states */
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sam_fws(SAM_FOSC0);
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sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
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/* Then switch the main clock to OSC0 */
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@ -990,25 +1179,65 @@ void sam_clockconfig(void)
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/* Set up FLASH wait states */
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sam_fws(SAM_CPU_CLOCK);
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sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
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/* Then switch the main clock to PLL0 */
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sam_mainclk(PM_MCCTRL_MCSEL_PLL0);
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sam_mainclk(PM_MCCTRL_MCSEL_PLL);
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#elif defined(BOARD_SYSCLK_SOURCE_DFLL0)
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# error Missing logic
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/* Enable PLL0 using the settings in board.h */
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sam_enabledfll0();
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/* Set up FLASH wait states */
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sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
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/* Then switch the main clock to DFLL0 */
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sam_mainclk(PM_MCCTRL_MCSEL_DFLL);
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#elif defined(BOARD_SYSCLK_SOURCE_RC80M)
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# error Missing logic
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/* Set up FLASH wait states */
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sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
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/* Then switch the main clock to RCM80 */
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sam_mainclk(PM_MCCTRL_MCSEL_RC80M);
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#elif defined(BOARD_SYSCLK_SOURCE_FCFAST12M) || defined(BOARD_SYSCLK_SOURCE_FCFAST8M) || \
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defined(BOARD_SYSCLK_SOURCE_FCFAST4M)
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# error Missing logic
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/* Set up FLASH wait states */
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sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
|
||||
|
||||
/* Then switch the main clock to RCFAST */
|
||||
|
||||
sam_mainclk(PM_MCCTRL_MCSEL_RCFAST);
|
||||
|
||||
#elif defined(BOARD_SYSCLK_SOURCE_RC1M)
|
||||
# error Missing logic
|
||||
|
||||
/* Set up FLASH wait states */
|
||||
|
||||
sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
|
||||
|
||||
/* Then switch the main clock to RC1M */
|
||||
|
||||
sam_mainclk(PM_MCCTRL_MCSEL_RC1M);
|
||||
|
||||
#else
|
||||
# error "No SYSCLK source frequency"
|
||||
# error "No SYSCLK source provided"
|
||||
#endif
|
||||
|
||||
/* Switch to the selected power scaling mode */
|
||||
|
||||
sam_setpsm(psm);
|
||||
|
||||
#ifdef CONFIG_USBDEV
|
||||
void sam_usbclock();
|
||||
#endif
|
||||
|
||||
@ -100,12 +100,6 @@ void __start(void)
|
||||
const uint32_t *src;
|
||||
uint32_t *dest;
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon as possible */
|
||||
|
||||
sam_clockconfig();
|
||||
sam_lowsetup();
|
||||
showprogress('A');
|
||||
|
||||
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
|
||||
* certain that there are no issues with the state of global variables.
|
||||
*/
|
||||
@ -114,7 +108,6 @@ void __start(void)
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
showprogress('B');
|
||||
|
||||
/* Move the intialized data section from his temporary holding spot in
|
||||
* FLASH into the correct place in SRAM. The correct place in SRAM is
|
||||
@ -126,14 +119,33 @@ void __start(void)
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
showprogress('C');
|
||||
|
||||
/* Copy any necessary code sections from FLASH to RAM. The correct
|
||||
* destination in SRAM is geive by _sramfuncs and _eramfuncs. The
|
||||
* temporary location is in flash after the data initalization code
|
||||
* at _framfuncs. This must be done before sam_clockconfig() can be
|
||||
* called (at least for the SAM4L family).
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_RAMFUNCS
|
||||
for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; )
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon as possible */
|
||||
|
||||
sam_clockconfig();
|
||||
sam_lowsetup();
|
||||
showprogress('A');
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
up_earlyserialinit();
|
||||
#endif
|
||||
showprogress('D');
|
||||
showprogress('B');
|
||||
|
||||
/* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
@ -143,13 +155,13 @@ void __start(void)
|
||||
|
||||
#ifdef CONFIG_NUTTX_KERNEL
|
||||
sam_userspace();
|
||||
showprogress('E');
|
||||
showprogress('C');
|
||||
#endif
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
sam_boardinitialize();
|
||||
showprogress('F');
|
||||
showprogress('D');
|
||||
|
||||
/* Then start NuttX */
|
||||
|
||||
|
||||
@ -103,9 +103,9 @@
|
||||
*/
|
||||
|
||||
#define BOARD_DFLL0_SOURCE_OSC32K 1
|
||||
#define BOARD_FDLL0_FREQUENCY 48000000
|
||||
#define BOARD_FDLL0_MUL (BOARD_FDLL0_FREQUENCY / BOARD_OSC32_FREQUENCY)
|
||||
#define BOARD_FDLL0_DIV 1
|
||||
#define BOARD_DFLL0_FREQUENCY 48000000
|
||||
#define BOARD_DFLL0_MUL (BOARD_DFLL0_FREQUENCY / BOARD_OSC32_FREQUENCY)
|
||||
#define BOARD_DFLL0_DIV 1
|
||||
|
||||
/* Phase Locked Loop configuration
|
||||
* Fdfll = (Fclk * PLLmul) / PLLdiv
|
||||
|
||||
@ -126,6 +126,7 @@ CONFIG_ARCH_CHIP_SAM4L=y
|
||||
#
|
||||
# AT91SAM3 Peripheral Support
|
||||
#
|
||||
CONFIG_SAM_PICOCACHE=y
|
||||
# CONFIG_SAM34_DMA is not set
|
||||
# CONFIG_SAM34_NAND is not set
|
||||
# CONFIG_SAM34_HSMCI is not set
|
||||
@ -164,7 +165,8 @@ CONFIG_ARCH_IRQPRIO=y
|
||||
CONFIG_ARCH_HAVE_VFORK=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
# CONFIG_ENDIAN_BIG is not set
|
||||
# CONFIG_ARCH_HAVE_RAMFUNCS is not set
|
||||
CONFIG_ARCH_HAVE_RAMFUNCS=y
|
||||
CONFIG_ARCH_RAMFUNCS=y
|
||||
CONFIG_ARCH_HAVE_RAMVECTORS=y
|
||||
# CONFIG_ARCH_RAMVECTORS is not set
|
||||
|
||||
@ -313,6 +315,10 @@ CONFIG_USART1_BAUD=115200
|
||||
CONFIG_USART1_BITS=8
|
||||
CONFIG_USART1_PARITY=0
|
||||
CONFIG_USART1_2STOP=0
|
||||
# CONFIG_USART1_IFLOWCONTROL is not set
|
||||
# CONFIG_USART1_OFLOWCONTROL is not set
|
||||
# CONFIG_SERIAL_IFLOWCONTROL is not set
|
||||
# CONFIG_SERIAL_OFLOWCONTROL is not set
|
||||
# CONFIG_USBDEV is not set
|
||||
# CONFIG_USBHOST is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
|
||||
@ -63,8 +63,6 @@ SECTIONS
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
.data : {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
@ -73,6 +71,16 @@ SECTIONS
|
||||
_edata = ABSOLUTE(.);
|
||||
} > sram AT > flash
|
||||
|
||||
_eronly = LOADADDR(.data);
|
||||
|
||||
.ramfunc ALIGN(4): {
|
||||
_sramfuncs = ABSOLUTE(.);
|
||||
*(.ramfunc .ramfunc.*)
|
||||
_eramfuncs = ABSOLUTE(.);
|
||||
} > sram AT > flash
|
||||
|
||||
_framfuncs = LOADADDR(.ramfunc);
|
||||
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} >sram
|
||||
|
||||
Loading…
Reference in New Issue
Block a user