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Add SMC configuration

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2618 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-04-19 03:13:51 +00:00
parent 933cec7399
commit 734fcb88a5
2 changed files with 59 additions and 15 deletions
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45
arch/arm/src/sam3u/sam3u_smc.h
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@ -125,11 +125,15 @@
#define SAM3U_SMC_ECCPR15 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR15_OFFSET)
#define SAM3U_SMCCS_BASE(n) (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(n))
#define SAM3U_SMCCS_SETUP (SAM3U_SMC_BASE+SAM3U_SMCCS_SETUP_OFFSET)
#define SAM3U_SMCCS_PULSE (SAM3U_SMC_BASE+SAM3U_SMCCS_PULSE_OFFSET)
#define SAM3U_SMCCS_CYCLE (SAM3U_SMC_BASE+SAM3U_SMCCS_CYCLE_OFFSET)
#define SAM3U_SMCCS_TIMINGS (SAM3U_SMC_BASE+SAM3U_SMCCS_TIMINGS_OFFSET)
#define SAM3U_SMCCS_MODE (SAM3U_SMC_BASE+SAM3U_SMCCS_MODE_OFFSET)
# define SAM3U_SMC_CS0_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(0))
# define SAM3U_SMC_CS1_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(1))
# define SAM3U_SMC_CS2_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(2))
# define SAM3U_SMC_CS3_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(3))
#define SAM3U_SMCCS_SETUP(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_SETUP_OFFSET)
#define SAM3U_SMCCS_PULSE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_PULSE_OFFSET)
#define SAM3U_SMCCS_CYCLE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_CYCLE_OFFSET)
#define SAM3U_SMCCS_TIMINGS(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_TIMINGS_OFFSET)
#define SAM3U_SMCCS_MODE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_MODE_OFFSET)
#define SAM3U_SMC_OCMS (SAM3U_SMC_BASE+SAM3U_SMC_OCMS_OFFSET)
#define SAM3U_SMC_KEY1 (SAM3U_SMC_BASE+SAM3U_SMC_KEY1_OFFSET)
@ -226,9 +230,9 @@
/* SMC ECC Status Register 1 */
_RECERR (0) /* Recoverable Error */
_ECCERR (1) /* ECC Error */
_MULERR (2) /* Multiple Error */
#define _RECERR (0) /* Recoverable Error */
#define _ECCERR (1) /* ECC Error */
#define _MULERR (2) /* Multiple Error */
#define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR))
#define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR))
@ -367,18 +371,29 @@ _MULERR (2) /* Multiple Error */
/* SMC Mode Register */
#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0 */
#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1 */
#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */
#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */
#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */
#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT)
0 0 Disabled
1 0 Frozen Mode
1 1 Ready Mode
# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT)
#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */
#define SMCCS_MODE_DBW (1 << 12) /* Bit 12: Data Bus Width */
#define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */
#define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT)
# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */
# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */
# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */
#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */
#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT)
#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization
#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */
#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */
# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */
# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */
# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */
/* SMC OCMS Register */

29
configs/sam3u-ek/src/up_lcd.c
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@ -120,7 +120,11 @@
#include <nuttx/arch.h>
#include <nuttx/lcd.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "sam3u_pmc.h"
#include "sam3u_smc.h"
#include "sam3u_internal.h"
#include "sam3uek_internal.h"
@ -409,6 +413,8 @@ static int sam3u_setcontrast(struct lcd_dev_s *dev, unsigned int contrast)
int up_lcdinitialize(void)
{
uint32_t regval;
/* Enable LCD EXTCS2 pins */
sam3u_configgpio(GPIO_LCD_NCS2);
@ -436,6 +442,29 @@ int up_lcdinitialize(void)
/* Configure LCD Backlight Pin */
sam3u_configgpio(GPIO_LCD_D15);
/* Enable SMC peripheral clock */
putreg32((1 << SAM3U_PID_SMC), SAM3U_PMC_PCER);
/* Configure SMC CS2 */
regval = (4 << SMCCS_SETUP_NWESETUP_SHIFT) | (2 << SMCCS_SETUP_NCSWRSETUP_SHIFT) |
(4 << SMCCS_SETUP_NRDSETUP_SHIFT) | (2 << SMCCS_SETUP_NCSRDSETUP_SHIFT);
putreg32(regval, SAM3U_SMCCS_SETUP(2));
regval = (5 << SMCCS_PULSE_NWEPULSE_SHIFT) | (18 << SMCCS_PULSE_NCSWRPULSE_SHIFT) |
(5 << SMCCS_PULSE_RDPULSE_SHIFT) | (18 << SMCCS_PULSE_NCSRDPULSE_SHIFT);
putreg32(regval, SAM3U_SMCCS_PULSE(2));
regval = (22 << SMCCS_CYCLE_NWECYCLE_SHIFT) | (22 << SMCCS_CYCLE_NRDCYCLE_SHIFT);
putreg32(regval, SAM3U_SMCCS_CYCLE(2));
regval = getreg32(SAM3U_SMCCS_MODE(2));
regval &= ~(SMCCS_MODE_DBW_MASK | SMCCS_MODE_PMEN);
regval |= (SMCCS_MODE_READMODE) | (SMCCS_MODE_WRITEMODE) | (SMCCS_MODE_DBW_16BITS);
putreg32(regval, SAM3U_SMCCS_MODE(2));
return -ENOSYS;
}