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Tiva: Updated files to allow for ADC triggering by the timer. I’ve cleaned up some parts of the ADC code, too, and fleshed out the PWM triggering ioctl. From Calvin Maguranis

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This commit is contained in:
Gregory Nutt 2015-02-17 13:50:30 -06:00
parent d578829ddd
commit 7354e41aa6
5 changed files with 840 additions and 960 deletions
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26
arch/arm/src/tiva/Kconfig
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@ -802,6 +802,14 @@ config TIVA_TIMER32_PERIODIC
bool "32-bit one-shot/periodic timer support"
default n
config TIVA_TIMER32_ADCEVENT
bool "32-bit one-shot/periodic timer ADC event support"
default n
depends on TIVA_TIMER32_PERIODIC
depends on TIVA_TIMER_32BIT
---help---
Enable timer support for triggering an ADC sample on timeout.
config TIVA_TIMER32_RTC
bool "32-bit RTC (needs 32.768-KHz input)"
default n
@ -818,17 +826,25 @@ config TIVA_TIMER16_PERIODIC
bool "16-bit one-shot/periodic timer support"
default n
config TIVA_TIMER32_EDGECOUNT
config TIVA_TIMER16_ADCEVENT
bool "16-bit one-shot/periodic timer ADC event support"
default n
depends on TIVA_TIMER16_PERIODIC
depends on TIVA_TIMER_16BIT
---help---
Enable timer support for triggering an ADC sample on timeout.
config TIVA_TIMER16_EDGECOUNT
bool "16-bit input edge-count capture support"
default n
depends on EXPERIMENTAL
config TIVA_TIMER32_TIMECAP
config TIVA_TIMER16_TIMECAP
bool "16-bit input time capture support"
default n
depends on EXPERIMENTAL
config TIVA_TIMER32_PWM
config TIVA_TIMER16_PWM
bool "16-bit PWM output support"
default n
depends on EXPERIMENTAL
@ -858,7 +874,6 @@ config TIVA_ADC_CLOCK
16 MHz to 32 MHz. The TM4C123 clock is limited to 16 MHz.
if TIVA_ADC0
menu "Tiva ADC0 configuration"
menuconfig TIVA_ADC0_SSE0
bool "Enable and configure ADC0 SSE0"
@ -1290,11 +1305,9 @@ config TIVA_ADC0_SSE3_STEP0_AIN
default 0
depends on TIVA_ADC0_SSE3_STEP0
endmenu # Tiva ADC0 configuration
endif # TIVA_ADC0
if TIVA_ADC1
menu "Tiva ADC1 configuration"
menuconfig TIVA_ADC1_SSE0
bool "Enable and configure ADC1 SSE0"
@ -1725,7 +1738,6 @@ config TIVA_ADC1_SSE3_TRIGGER
default 0
depends on TIVA_ADC1_SSE3_STEP0
endmenu # Tiva ADC1 configuration
endif # TIVA_ADC1
config TIVA_ADC_REGDEBUG

1009
arch/arm/src/tiva/tiva_adc.c
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File diff suppressed because it is too large Load Diff

36
arch/arm/src/tiva/tiva_adc.h
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@ -49,43 +49,19 @@
#ifdef CONFIG_TIVA_ADC
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#define TIVA_ADC_PWM_TRIG_IOCTL _ANIOC(0x00F0)
/* PWM trigger support definitions *************************************************/
/* PWM trigger ioctl support ***********************************************/
#define ADC_TRIG_PWM_MASK \
(0xE0000000 & ADC_EMUX_PWM0 & ADC_EMUX_PWM1 & ADC_EMUX_PWM2 & ADC_EMUX_PWM3)
#define TIVA_ADC_PWM_TRIG(sse, pwm, mod) ((((mod) << 4) << ((pwm) * 8)) + (sse))
/* Encodes the PWM generator (0 to 3) value to the 2 MSB's of 32-bits;
* PWM module (0 or 1) value in the 3rd MSB:
* 0bGGM0.0000.0000.0000,0000.0000.0000.0000
* To be OR'd with a trigger register value.
*/
#define PWM_GEN_SHIFT (31)
#define PWM_MOD_SHIFT (30)
# define ADC_TRIG_PWM_IOCTL(gen,mod) \
(((gen) << PWM_GEN_SHIFT) | ((mod) << PWM_MOD_SHIFT))
/* Decodes PWM generator number from trigger */
#define PWM_GEN_MASK (0xC0000000)
# define ADC_TRIG_PWM_GEN(trig) \
(((trig)&PWM_GEN_MASK)>>(PWM_GEN_SHIFT-1))
/* Decodes PWM module number from trigger */
#define PWM_MOD_MASK (0x20000000)
# define ADC_TRIG_PWM_MOD(trig) \
(((trig)&PWM_MOD_MASK)>>(PWM_MOD_SHIFT-1))
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
# ifdef __cplusplus

18
arch/arm/src/tiva/tiva_timerlib.c
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@ -901,14 +901,6 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
/* Enable and configure ADC trigger outputs */
if (TIMER_ISADCTIMEOUT(timer) || TIMER_ISADCMATCH(timer))
{
/* Enable ADC trigger outputs by setting the TAOTE bit in the
* control register.
*/
regval = tiva_getreg(priv, TIVA_TIMER_CTL_OFFSET);
regval |= TIMER_CTL_TAOTE;
tiva_putreg(priv, TIVA_TIMER_CTL_OFFSET, regval);
#ifdef CONFIG_ARCH_CHIP_TM4C129
/* Enable timeout triggers now (match triggers will be
* enabled when the first match value is set).
@ -918,7 +910,15 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
{
tiva_putreg(priv, TIVA_TIMER_ADCEV_OFFSET, TIMER_ADCEV_TATOADCEN);
}
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
#endif
/* Enable ADC trigger outputs by setting the TAOTE bit in the
* control register.
*/
regval = tiva_getreg(priv, TIVA_TIMER_CTL_OFFSET);
regval |= TIMER_CTL_TAOTE;
tiva_putreg(priv, TIVA_TIMER_CTL_OFFSET, regval);
}
/* In addition, if using CCP pins, the TCACT field can be programmed to

3
arch/arm/src/tiva/tiva_timerlow32.c
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@ -591,6 +591,9 @@ int tiva_timer_register(FAR const char *devpath, int gptm, bool altclk)
config->cmn.mode = TIMER32_MODE_PERIODIC;
config->cmn.alternate = altclk;
config->config.flags = TIMER_FLAG_COUNTUP;
#ifdef CONFIG_TIVA_TIMER32_ADCEVENT
config->config.flags |= TIMER_FLAG_ADCTIMEOUT;
#endif
config->config.handler = tiva_handler;
config->config.arg = priv;