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Fix PU/PD config; improve MODE/CNF setting

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2106 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2009-09-29 18:56:20 +00:00
parent 80688bbff1
commit 73727ef887
2 changed files with 28 additions and 14 deletions
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33
arch/arm/src/stm32/stm32_gpio.c
View File

@ -107,8 +107,7 @@ int stm32_configgpio(uint32 cfgset)
unsigned int gpio; unsigned int gpio;
unsigned int pin; unsigned int pin;
unsigned int pos; unsigned int pos;
unsigned int mode; unsigned int modecnf;
unsigned int cnf;
boolean output; boolean output;
/* Verify that this hardware supports the select GPIO port */ /* Verify that this hardware supports the select GPIO port */
@ -142,28 +141,29 @@ int stm32_configgpio(uint32 cfgset)
if (output) if (output)
{ {
mode = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT; modecnf = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT;
} }
else else
{ {
mode = 0; modecnf = 0;
} }
cnf = (cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT; modecnf |= ((cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT) << 2;
/* Set the port configuration register */ /* Set the port configuration register */
regval = getreg32(cr); regval = getreg32(cr);
regval &= ~(GPIO_CR_MODE_MASK(pos)|GPIO_CRL_CNF_MASK(pos)); regval &= ~(GPIO_CR_MODECNF_MASK(pos));
regval |= (mode << GPIO_CR_MODE_SHIFT(pos)) | (cnf << GPIO_CRL_CNF_SHIFT(pos)); regval |= (modecnf << GPIO_CR_MODECNF_SHIFT(pos));
putreg32(regval, cr); putreg32(regval, cr);
/* Set or reset the corresponding BRR/BSRR bit */ /* Set or reset the corresponding BRR/BSRR bit */
if (output) if (output)
{ {
/* It is an output pin, we need to set/clear the output value */ /* It is an output pin, we need to instantiate the initial
* pin output value
*/
if ((cfgset & GPIO_OUTPUT_VALUE) != 0) if ((cfgset & GPIO_OUTPUT_VALUE) != 0)
{ {
@ -180,16 +180,27 @@ int stm32_configgpio(uint32 cfgset)
} }
else else
{ {
if ((cfgset & GPIO_MODE_MASK) == GPIO_CNF_INPULLDWN) /* It is an input pin... If it is pull-down or pull up,
* then we need to set the ODR appropriately for that
* function.
*/
if ((cfgset & GPIO_MODE_MASK) == GPIO_CNF_INPULLUP)
{ {
/* Set the ODR bit (using BSRR) to one for the PULL-UP functionality */
regaddr = gpiobase + STM32_GPIO_BSRR_OFFSET; regaddr = gpiobase + STM32_GPIO_BSRR_OFFSET;
} }
else if ((cfgset & GPIO_MODE_MASK) == GPIO_CNF_INPULLUP) else if ((cfgset & GPIO_MODE_MASK) == GPIO_CNF_INPULLDWN)
{ {
/* Clear the ODR bit (using BRR) to zero for the PULL-DOWN functionality */
regaddr = gpiobase + STM32_GPIO_BRR_OFFSET; regaddr = gpiobase + STM32_GPIO_BRR_OFFSET;
} }
else else
{ {
/* Neither... we can return early */
return OK; return OK;
} }
} }

9
arch/arm/src/stm32/stm32_gpio.h
View File

@ -148,10 +148,13 @@
/* Port configuration register low */ /* Port configuration register low */
#define GPIO_CR_MODE_SHIFT(n) ((n) << 1) #define GPIO_CR_MODE_SHIFT(n) ((n) << 2)
#define GPIO_CR_MODE_MASK(n) (3 << GPIO_CR_MODE_SHIFT(n)) #define GPIO_CR_MODE_MASK(n) (3 << GPIO_CR_MODE_SHIFT(n))
#define GPIO_CRL_CNF_SHIFT(n) (2+((n) << 1)) #define GPIO_CR_CNF_SHIFT(n) (2 + ((n) << 2))
#define GPIO_CRL_CNF_MASK(n) (3 << GPIO_CRL_CNF_SHIFT(n)) #define GPIO_CR_CNF_MASK(n) (3 << GPIO_CRL_CNF_SHIFT(n))
#define GPIO_CR_MODECNF_SHIFT(n) ((n) << 2)
#define GPIO_CR_MODECNF_MASK(n) (0x0f << GPIO_CR_MODECNF_SHIFT(n))
#define GPIO_CRL_MODE0_SHIFT (0) /* Bits 1:0: Port mode bits */ #define GPIO_CRL_MODE0_SHIFT (0) /* Bits 1:0: Port mode bits */
#define GPIO_CRL_MODE0_MASK (3 << GPIO_CRL_MODE0_SHIFT) #define GPIO_CRL_MODE0_MASK (3 << GPIO_CRL_MODE0_SHIFT)