Add GPIO library functions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2730 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
ee8c1e6a73
commit
738804f105
@ -51,9 +51,9 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
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# Required SAM3U files
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CHIP_ASRCS =
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CHIP_CSRCS = lpc17_start.c
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CHIP_CSRCS = lpc17_gpio.c lpc17_start.c
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#CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpioirq.c \
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# lpc17_irq.c lpc17_lowputc.c lpc17_pio.c lpc17_serial.c \
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# lpc17_irq.c lpc17_lowputc.c lpc17_gpio.c lpc17_serial.c \
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# lpc17_start.c lpc17_timerisr.c
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# Configuration-dependent SAM3U files
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@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lp17_memorymap.h"
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#include "lpc17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lp17_memorymap.h"
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#include "lpc17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lp17_memorymap.h"
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#include "lpc17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lp17_memorymap.h"
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#include "lpc17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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@ -43,7 +43,7 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lp17_memorymap.h"
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#include "lpc17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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652
arch/arm/src/lpc17xx/lpc17_gpio.c
Executable file
652
arch/arm/src/lpc17xx/lpc17_gpio.c
Executable file
@ -0,0 +1,652 @@
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/****************************************************************************
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* arch/arm/src/lpc17xx/lpc17_gpio.c
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "lpc17_gpio.h"
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#include "lpc17_pinconn.h"
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#include "lpc17_internal.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Default input pin configuration */
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#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* We have to remember the configured interrupt setting.. PINs are not
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* actually set up to interrupt until the interrupt is enabled.
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*/
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#ifdef CONFIG_GPIO_IRQ
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static uint32_t g_intedge0[2];
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static uint32_t g_intedge2[2];
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* These tables have global scope because they are also used in
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* lpc17_gpiodbg.c
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*/
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const uint32_t g_fiobase[GPIO_NPORTS] =
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{
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LPC17_FIO0_BASE,
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LPC17_FIO1_BASE,
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LPC17_FIO2_BASE,
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LPC17_FIO3_BASE,
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LPC17_FIO4_BASE
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};
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/* Port 0 and Port 2 can provide a single interrupt for any combination of
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* port pins
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*/
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const uint32_t g_intbase[GPIO_NPORTS] =
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{
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LPC17_GPIOINT0_OFFSET,
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0,
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LPC17_GPIOINT2_OFFSET,
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0,
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0
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};
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const uint32_t g_lopinsel[GPIO_NPORTS] =
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{
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LPC17_PINCONN_PINSEL0,
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LPC17_PINCONN_PINSEL2,
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LPC17_PINCONN_PINSEL4,
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0,
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0
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};
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const uint32_t g_hipinsel[GPIO_NPORTS] =
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{
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LPC17_PINCONN_PINSEL1,
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LPC17_PINCONN_PINSEL3,
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0,
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LPC17_PINCONN_PINSEL7,
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LPC17_PINCONN_PINSEL9
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};
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const uint32_t g_lopinmode[GPIO_NPORTS] =
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{
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LPC17_PINCONN_PINMODE0,
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LPC17_PINCONN_PINMODE2,
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LPC17_PINCONN_PINMODE4,
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0,
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0
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};
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const uint32_t g_hipinmode[GPIO_NPORTS] =
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{
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LPC17_PINCONN_PINMODE1,
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LPC17_PINCONN_PINMODE3,
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0,
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LPC17_PINCONN_PINMODE7,
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LPC17_PINCONN_PINMODE9
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};
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const uint32_t g_odmode[GPIO_NPORTS] =
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{
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LPC17_PINCONN_ODMODE0,
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LPC17_PINCONN_ODMODE1,
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LPC17_PINCONN_ODMODE2,
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LPC17_PINCONN_ODMODE3,
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LPC17_PINCONN_ODMODE4
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc17_pinsel
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*
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* Description:
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* Get the address of the PINSEL register corresponding to this port and
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* pin number.
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*
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****************************************************************************/
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static int lpc17_pinsel(unsigned int port, unsigned int pin, unsigned int value)
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{
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const uint32_t *table;
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uint32_t regaddr;
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uint32_t regval;
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unsigned int shift;
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/* Which table do we use */
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if (pin < 16)
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{
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table = g_lopinsel;
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shift = PINCONN_PINSELL_SHIFT(pin);
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}
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else
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{
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table = g_hipinsel;
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shift = PINCONN_PINSELH_SHIFT(pin);
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}
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/* Fetch the PINSEL register address for this port/pin combination */
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regaddr = table[port];
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if (regaddr != 0)
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{
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/* Set the requested value in the PINSEL register */
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regval = getreg32(regaddr);
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regval &= ~(PINCONN_PINSEL_MASK << shift);
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regval |= (value << shift);
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putreg32(regval, regaddr);
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return OK;
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}
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return -EINVAL;
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}
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/****************************************************************************
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* Name: lpc17_pullup
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*
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* Description:
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* Get the address of the PINMODE register corresponding to this port and
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* pin number.
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*
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****************************************************************************/
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static int lpc17_pullup(uint16_t cfgset, unsigned int port, unsigned int pin)
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{
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const uint32_t *table;
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uint32_t regaddr;
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uint32_t regval;
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uint32_t value;
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unsigned int shift;
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switch (cfgset & GPIO_PUMODE_MASK)
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{
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default:
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case GPIO_PULLUP: /* Pull-up resistor enabled */
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value = PINCONN_PINMODE_PU;
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break;
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case GPIO_REPEATER: /* Repeater mode enabled */
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value = PINCONN_PINMODE_RM;
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break;
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case GPIO_PUNONE: /* Neither pull-up nor -down */
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value = PINCONN_PINMODE_PD;
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break;
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case GPIO_PULLDN: /* Pull-down resistor enabled */
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value = PINCONN_PINMODE_MASK;
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break;
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}
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/* Which table do we use */
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if (pin < 16)
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{
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table = g_lopinmode;
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shift = PINCONN_PINMODEL_SHIFT(pin);
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}
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else
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{
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table = g_hipinmode;
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shift = PINCONN_PINMODEH_SHIFT(pin);
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}
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/* Fetch the PINSEL register address for this port/pin combination */
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regaddr = table[port];
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if (regaddr != 0)
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{
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/* Set the requested value in the PINSEL register */
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regval = getreg32(regaddr);
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regval &= ~(PINCONN_PINMODE_MASK << shift);
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regval |= (value << shift);
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putreg32(regval, regaddr);
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return OK;
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}
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return -EINVAL;
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}
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/****************************************************************************
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* Name: lpc17_setintedge
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*
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* Description:
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* Remember the configured interrupt edge. We can't actually enable the
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* the edge interrupts until the called calls IRQ enabled function.
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*
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****************************************************************************/
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#ifdef CONFIG_GPIO_IRQ
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static int lpc17_setintedge(unsigned int port, unsigned int pin, unsigned int value)
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{
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const uint32_t *table;
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uint32_t tabval;
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unsigned int shift;
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/* Which word to we use? */
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if (port == 0)
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{
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table = g_intedge0;
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}
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else if (port == 2)
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{
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table = g_intedge2;
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}
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else
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{
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return;
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}
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if (pin >= 16)
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{
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table++;
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pin -= 16;
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}
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/* Set the requested value in the PINSEL register */
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*table &= ~(3 << shift);
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*table |= (value << shift);
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}
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#endif
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/****************************************************************************
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* Name: lpc17_setopendrain
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*
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* Description:
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* Set the ODMODE register for open drain mode
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*
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****************************************************************************/
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static void lpc17_setopendrain(unsigned int port, unsigned int pin)
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{
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uint32_t regaddr;
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uint32_t regval;
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regaddr = g_odmode[port];
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regval = getreg32(regaddr);
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regval |= (1 << pin);
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putreg32(regval, regaddr);
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}
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/****************************************************************************
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* Name: lpc17_clropendrain
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*
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* Description:
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* Reset the ODMODE register to disable open drain mode
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*
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****************************************************************************/
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static void lpc17_clropendrain(unsigned int port, unsigned int pin)
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{
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uint32_t regaddr;
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uint32_t regval;
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regaddr = g_odmode[port];
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regval = getreg32(regaddr);
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regval &= ~(1 << pin);
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putreg32(regval, regaddr);
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}
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/****************************************************************************
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* Name: lpc17_configinput
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*
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* Description:
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* Configure a GPIO inpue pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int lpc17_configinput(uint16_t cfgset, unsigned int port, unsigned int pin)
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{
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uint32_t regval;
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uint32_t fiobase;
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uint32_t intbase;
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uint32_t pinmask = (1 << pin);
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/* Set up FIO registers */
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fiobase = g_fiobase[port];
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/* Set as input */
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regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET);
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regval &= ~pinmask;
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putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET);
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/* Set up interrupt registers */
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intbase = g_intbase[port];
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if (intbase != 0)
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{
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/* Disable any rising edge interrupts */
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regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
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regval &= ~pinmask;
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putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET);
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/* Disable any falling edge interrupts */
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regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
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regval &= ~pinmask;
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putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
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/* Forget about any falling/rising edge interrupt enabled */
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#ifdef CONFIG_GPIO_IRQ
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lpc17_setintedge(port, pin, 0);
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#endif
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}
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/* Set up PINSEL registers */
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/* Configure as GPIO */
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lpc17_pinsel(port, pin, PINCONN_PINSEL_GPIO);
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/* Set pull-up mode */
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lpc17_pullup(cfgset, port, pin);
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/* Open drain only applies to outputs */
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lpc17_clropendrain(port, pin);
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return OK;
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}
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/****************************************************************************
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* Name: lpc17_configinterrupt
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*
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* Description:
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* Configure a GPIO interrupt pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int lpc17_configinterrupt(uint16_t cfgset, unsigned int port, unsigned int pin)
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{
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/* First, configure the port as a generic input so that we have a known
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* starting point and consistent behavior during the re-configuration.
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*/
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(void)lpc17_configinput(cfgset, port, pin);
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/* Then just remember the rising/falling edge interrupt enabled */
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DEBUGASSERT(port == 0 || port == 2);
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#ifdef CONFIG_GPIO_IRQ
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lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
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#endif
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return OK;
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}
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/****************************************************************************
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* Name: lpc17_configoutput
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*
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* Description:
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* Configure a GPIO output pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int lpc17_configoutput(uint16_t cfgset, unsigned int port, unsigned int pin)
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{
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uint32_t fiobase;
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uint32_t regval;
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/* First, configure the port as a generic input so that we have a known
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* starting point and consistent behavior during the re-configuration.
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*/
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(void)lpc17_configinput(DEFAULT_INPUT, port, pin);
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/* Now, reconfigure the pin as an output */
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fiobase = g_fiobase[port];
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regval = getreg32(fiobase + LPC17_FIO_DIR_OFFSET);
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regval |= (1 << pin);
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putreg32(regval, fiobase + LPC17_FIO_DIR_OFFSET);
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/* Check for open drain output */
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if ((cfgset & GPIO_OPEN_DRAIN) != 0)
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{
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||||
/* Set pull-up mode. This normally only applies to input pins, but does have
|
||||
* meaning if the port is an open drain output.
|
||||
*/
|
||||
|
||||
lpc17_pullup(cfgset, port, pin);
|
||||
|
||||
/* Select open drain output */
|
||||
|
||||
lpc17_setopendrain(port, pin);
|
||||
}
|
||||
|
||||
/* Set the initial value of the output */
|
||||
|
||||
lpc17_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO));
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configalternate
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO alternate function pin based on bit-encoded description
|
||||
* of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
static int lpc17_configalternate(uint16_t cfgset, unsigned int port, unsigned int pin, uint32_t alt)
|
||||
{
|
||||
/* First, configure the port as an input so that we have a known
|
||||
* starting point and consistent behavior during the re-configuration.
|
||||
*/
|
||||
|
||||
(void)lpc17_configinput(DEFAULT_INPUT, port, pin);
|
||||
|
||||
/* Set up PINSEL registers */
|
||||
/* Configure as GPIO */
|
||||
|
||||
lpc17_pinsel(port, pin, alt);
|
||||
|
||||
/* Set pull-up mode */
|
||||
|
||||
lpc17_pullup(cfgset, port, pin);
|
||||
|
||||
/* Check for open drain output */
|
||||
|
||||
if ((cfgset & GPIO_OPEN_DRAIN) != 0)
|
||||
{
|
||||
/* Select open drain output */
|
||||
|
||||
lpc17_setopendrain(port, pin);
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int lpc17_configgpio(uint16_t cfgset)
|
||||
{
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
int ret = -EINVAL;
|
||||
|
||||
/* Verify that this hardware supports the select GPIO port */
|
||||
|
||||
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the pin number and select the port configuration register for that pin */
|
||||
|
||||
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Handle according to pin function */
|
||||
|
||||
switch (cfgset & GPIO_FUNC_MASK)
|
||||
{
|
||||
case GPIO_INPUT: /* GPIO input pin */
|
||||
ret = lpc17_configinput(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_INTFE: /* GPIO interrupt falling edge */
|
||||
case GPIO_INTRE: /* GPIO interrupt rising edge */
|
||||
case GPIO_INTBOTH: /* GPIO interrupt both edges */
|
||||
ret = lpc17_configinterrupt(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_OUTPUT: /* GPIO outpout pin */
|
||||
ret = lpc17_configoutput(cfgset, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_ALT1: /* Alternate function 1 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT1);
|
||||
break;
|
||||
|
||||
case GPIO_ALT2: /* Alternate function 2 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT2);
|
||||
break;
|
||||
|
||||
case GPIO_ALT3: /* Alternate function 3 */
|
||||
ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT3);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc17_gpiowrite(uint16_t pinset, bool value)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
uint32_t offset;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Get the pin number */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Set or clear the output on the pin */
|
||||
|
||||
if (value)
|
||||
{
|
||||
offset = LPC17_FIO_SET_OFFSET;
|
||||
}
|
||||
else
|
||||
offset = LPC17_FIO_CLR_OFFSET;
|
||||
{
|
||||
}
|
||||
putreg32((1 << pin), fiobase + offset);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool lpc17_gpioread(uint16_t pinset)
|
||||
{
|
||||
uint32_t fiobase;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < GPIO_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
fiobase = g_fiobase[port];
|
||||
|
||||
/* Get the pin number and return the input state of that pin */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
return ((getreg32(fiobase + LPC17_FIO_PIN_OFFSET) & (1 << pin)) != 0);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -66,7 +66,7 @@
|
||||
|
||||
/* GPIO interrupt block register offsets ********************************************/
|
||||
|
||||
#define LPC17_GPIOINT(n) (0x10*(n) + 0x80)
|
||||
#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80)
|
||||
#define LPC17_GPIOINT0_OFFSET 0x0080
|
||||
#define LPC17_GPIOINT2_OFFSET 0x00a0
|
||||
|
||||
@ -80,7 +80,7 @@
|
||||
/* Register addresses ***************************************************************/
|
||||
/* GPIO block register addresses ****************************************************/
|
||||
|
||||
#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT(n))
|
||||
#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n))
|
||||
#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET)
|
||||
#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET)
|
||||
#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET)
|
||||
@ -125,33 +125,33 @@
|
||||
|
||||
/* GPIO interrupt block register addresses ******************************************/
|
||||
|
||||
#define LPC17_GPIOINT(n) (0x10*(n) + 0x80)
|
||||
#define LPC17_GPIOINT0_OFFSET 0x0080
|
||||
#define LPC17_GPIOINT2_OFFSET 0x00a0
|
||||
#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n))
|
||||
#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET)
|
||||
#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET)
|
||||
|
||||
#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_IOINTSTATUS_OFFSET)
|
||||
#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET)
|
||||
|
||||
#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTSTATR_OFFSET)
|
||||
#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTSTATF_OFFSET)
|
||||
#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTCLR_OFFSET)
|
||||
#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTENR_OFFSET)
|
||||
#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTENF_OFFSET)
|
||||
#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET)
|
||||
#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET)
|
||||
#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET)
|
||||
#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET)
|
||||
#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET)
|
||||
|
||||
/* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */
|
||||
|
||||
#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTSTATR_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTSTATF_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTCLR_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTENR_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTENF_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET)
|
||||
#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET)
|
||||
|
||||
/* Pins P2.0-13 (P0.14-31 are reserved) */
|
||||
|
||||
#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTSTATR_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTSTATF_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTCLR_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTENR_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTENF_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET)
|
||||
#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* GPIO block register bit definitions **********************************************/
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -58,30 +58,51 @@
|
||||
|
||||
/* Bit-encoded input to lpc17_configgpio() ******************************************/
|
||||
|
||||
/* Encoding: FFMM OGGG PPPN NNNN
|
||||
/* Encoding: FFFx MMOV PPPN NNNN
|
||||
*
|
||||
* Pin Function: FF
|
||||
* Pin Mode: MM (input pins)
|
||||
* Pin Function: FFF
|
||||
* Pin Mode bits: MM
|
||||
* Open drain: O (output pins)
|
||||
* GPIO Mode bits: GGG
|
||||
* Initial value: V (output pins)
|
||||
* Port number: PPP (0-4)
|
||||
* Pin number: NNNNN (0-31)
|
||||
*/
|
||||
|
||||
/* Pin Function: FF */
|
||||
|
||||
#define GPIO_FUNC_SHIFT (14) /* Bits 14-15: Pin function select */
|
||||
#define GPIO_FUNC_MASK (3 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_PIN 0 (0 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_ALT1 1 (1 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_ALT2 2 (2 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_ALT3 3 (3 << GPIO_FUNC_SHIFT)
|
||||
/* Pin Function bits: FFF
|
||||
* Only meaningful when the GPIO function is GPIO_PIN
|
||||
*/
|
||||
|
||||
#define GPIO_ISGPIO(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_PIN)
|
||||
#define GPIO_FUNC_SHIFT (13) /* Bits 13-15: GPIO mode */
|
||||
#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 000 GPIO input pin */
|
||||
# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 001 GPIO interrupt falling edge */
|
||||
# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 010 GPIO interrupt rising edge */
|
||||
# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 011 GPIO interrupt both edges */
|
||||
# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 100 GPIO outpout pin */
|
||||
# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 101 Alternate function 1 */
|
||||
# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 110 Alternate function 2 */
|
||||
# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 111 Alternate function 3 */
|
||||
|
||||
#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */
|
||||
#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT)
|
||||
|
||||
#define GPIO_INOUT_MASK GPIO_OUTPUT
|
||||
#define GPIO_FE_MASK GPIO_INTFE
|
||||
#define GPIO_RE_MASK GPIO_INTRE
|
||||
|
||||
#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT)
|
||||
#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT)
|
||||
#define GPIO_ISINPUT(ps) ((ps) & GPIO_FUNC_MASK) == GPIO_INPUT)
|
||||
#define GPIO_ISOUTPUT(ps) ((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT)
|
||||
#define GPIO_ISINORINT(ps) ((ps) & GPIO_INOUT_MASK) == 0)
|
||||
#define GPIO_ISOUTORALT(ps) ((ps) & GPIO_INOUT_MASK) != 0)
|
||||
#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps))
|
||||
#define GPIO_ISFE(ps) ((ps) & GPIO_FE_MASK) != 0)
|
||||
#define GPIO_ISRE(ps) ((ps) & GPIO_RE_MASK) != 0)
|
||||
|
||||
/* Pin Mode: MM */
|
||||
|
||||
#define GPIO_PUMODE_SHIFT (12) /* Bits 12-13: Pin pull-up mode */
|
||||
#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */
|
||||
#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT)
|
||||
# define GPIO_PULLUP (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
|
||||
# define GPIO_REPEATER (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
|
||||
@ -90,29 +111,13 @@
|
||||
|
||||
/* Open drain: O */
|
||||
|
||||
#define GPIO_OPEN_DRAIN (1 << 11) /* Bit 11: Open drain mode */
|
||||
#define GPIO_OPEN_DRAIN (1 << 9) /* Bit 9: Open drain mode */
|
||||
|
||||
/* GPIO Mode bits: GGG
|
||||
* Only meaningful when the GPIO function is GPIO_PIN
|
||||
*/
|
||||
/* Initial value: V */
|
||||
|
||||
#define GPIO_GMODE_SHIFT (8) /* Bits 8-10: GPIO mode */
|
||||
#define GPIO_GMODE_MASK (7 << GPIO_GMODE_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_GMODE_SHIFT) /* 000 GPIO input pin */
|
||||
# define GPIO_INTFE (1 << GPIO_GMODE_SHIFT) /* 001 GPIO interrupt falling edge */
|
||||
# define GPIO_INTRE (2 << GPIO_GMODE_SHIFT) /* 010 GPIO interrupt rising edge */
|
||||
# define GPIO_INTBOTH (3 << GPIO_GMODE_SHIFT) /* 011 GPIO interrupt both edges */
|
||||
# define GPIO_OUTPUT (4 << GPIO_GMODE_SHIFT) /* 100 GPIO outpout pin */
|
||||
|
||||
#define GPIO_OUTPUT_MASK GPIO_OUTPUT
|
||||
#define GPIO_FE_MASK GPIO_INTFE
|
||||
#define GPIO_RE_MASK GPIO_INTRE
|
||||
|
||||
#define GPIO_ISINPUT(ps) ((ps) & GPIO_GMODE_MASK) == GPIO_INPUT)
|
||||
#define GPIO_ISOUTPUT(ps) ((ps) & GPIO_OUTPUT_MASK) != 0)
|
||||
#define GPIO_ISINTERRUPT(ps) (!GPIO_ISINPUT(ps) && !GPIO_ISOUTPUT(ps))
|
||||
#define GPIO_ISFE(ps) ((ps) & GPIO_FE_MASK) != 0)
|
||||
#define GPIO_ISRE(ps) ((ps) & GPIO_RE_MASK) != 0)
|
||||
#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */
|
||||
#define GPIO_VALUE_ONE GPIO_VALUE
|
||||
#define GPIO_VALUE_ZERO (0)
|
||||
|
||||
/* Port number: PPP (0-4) */
|
||||
|
||||
@ -124,6 +129,8 @@
|
||||
# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define GPIO_NPORTS 5
|
||||
|
||||
/* Pin number: NNNNN (0-31) */
|
||||
|
||||
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
|
||||
@ -348,6 +355,18 @@ extern "C" {
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* These tables have global scope only because they are shared between lpc_gpio.c
|
||||
* and lpc17_gpiodbg.c
|
||||
*/
|
||||
|
||||
extern const uint32_t g_fiobase[GPIO_NPORTS];
|
||||
extern const uint32_t g_intbase[GPIO_NPORTS];
|
||||
extern const uint32_t g_lopinsel[GPIO_NPORTS];
|
||||
extern const uint32_t g_hipinsel[GPIO_NPORTS];
|
||||
extern const uint32_t g_lopinmode[GPIO_NPORTS];
|
||||
extern const uint32_t g_hipinmode[GPIO_NPORTS];
|
||||
extern const uint32_t g_odmode[GPIO_NPORTS];
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -106,6 +106,12 @@
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */
|
||||
|
||||
#define PINCONN_PINSEL_GPIO (0)
|
||||
#define PINCONN_PINSEL_ALT1 (1)
|
||||
#define PINCONN_PINSEL_ALT2 (2)
|
||||
#define PINCONN_PINSEL_ALT3 (3)
|
||||
#define PINCONN_PINSEL_MASK (3)
|
||||
|
||||
#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */
|
||||
#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n))
|
||||
#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */
|
||||
@ -457,21 +463,21 @@
|
||||
#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */
|
||||
#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */
|
||||
#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */
|
||||
#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */
|
||||
#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */
|
||||
#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */
|
||||
#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */
|
||||
#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */
|
||||
#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */
|
||||
#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT)
|
||||
#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */
|
||||
#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT)
|
||||
/* Bits 28-31: Reserved */
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -44,7 +44,7 @@
|
||||
#include <nuttx/ohci.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lp17_memorymap.h"
|
||||
#include "lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user