From 738be875eb5275eb79a022dde1cb9db227cb1800 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 16 Feb 2019 18:42:26 -0600 Subject: [PATCH] arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h: Correct some kruft that was left behind when this file was split out. Caused failures in build testing. --- arch/arm/src/tiva/hardware/lm/lm_i2c.h | 8 +- arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h | 19 ++-- arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h | 96 +++++++++---------- 3 files changed, 60 insertions(+), 63 deletions(-) diff --git a/arch/arm/src/tiva/hardware/lm/lm_i2c.h b/arch/arm/src/tiva/hardware/lm/lm_i2c.h index 4d874d10dd..ce1da2c427 100644 --- a/arch/arm/src/tiva/hardware/lm/lm_i2c.h +++ b/arch/arm/src/tiva/hardware/lm/lm_i2c.h @@ -368,19 +368,19 @@ /* I2C Master Interrupt Mask (I2CM_IMR) */ -#define I2CM_IMR_MIM (1 << 0) /* Bit 0: Master Interrupt Mask */ +#define I2CM_IMR_MIM (1 << 0) /* Bit 0: Master Interrupt Mask */ /* I2C Master Raw Interrupt Status (I2CM_RIS) */ -#define I2CM_RIS_MRIS (1 << 0) /* Bit 0: Master Raw Interrupt Status */ +#define I2CM_RIS_MRIS (1 << 0) /* Bit 0: Master Raw Interrupt Status */ /* I2C Master Masked Interrupt Status (I2CM_MIS) */ -#define I2CM_MIS_MMIS (1 << 0) /* Bit 0: Maseter Masked Interrupt Status */ +#define I2CM_MIS_MMIS (1 << 0) /* Bit 0: Maseter Masked Interrupt Status */ /* I2C Master Masked Interrupt Status (I2CM_ICR) */ -#define I2CM_ICR_MIC (1 << 0) /* Bit 0: Master Masked Interrupt Clear */ +#define I2CM_ICR_MIC (1 << 0) /* Bit 0: Master Masked Interrupt Clear */ /* I2C Master Configuration (I2CM_CR) */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h b/arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h index dd2d8c126a..e0ed70cff1 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h @@ -511,28 +511,25 @@ #define I2CM_TPR_MASK (0x7f << I2CM_TPR_SHIFT) #define I2CM_TPR_HS (1 << 7) /* Bit 7: High-Speed Enable (write) */ -#define I2CM_TPR_SHIFT (0) /* Bits 7-0: SCL Clock Period */ -#define I2CM_TPR_MASK (0xff << I2CM_TPR_SHIFT) - /* I2C Master Interrupt Mask (I2CM_IMR) */ -#define I2CM_IMR_MIM (1 << 0) /* Bit 0: Master Interrupt Mask */ -#define I2CM_IMR_CLKIM (1 << 1) /* Bit 1: Clock Timeout Interrupt Mask */ +#define I2CM_IMR_MIM (1 << 0) /* Bit 0: Master Interrupt Mask */ +#define I2CM_IMR_CLKIM (1 << 1) /* Bit 1: Clock Timeout Interrupt Mask */ /* I2C Master Raw Interrupt Status (I2CM_RIS) */ -#define I2CM_RIS_MRIS (1 << 0) /* Bit 0: Master Raw Interrupt Status */ -#define I2CM_RIS_CLKRIS (1 << 1) /* Bit 1: Clock Timeout Raw Interrupt Status */ +#define I2CM_RIS_MRIS (1 << 0) /* Bit 0: Master Raw Interrupt Status */ +#define I2CM_RIS_CLKRIS (1 << 1) /* Bit 1: Clock Timeout Raw Interrupt Status */ /* I2C Master Masked Interrupt Status (I2CM_MIS) */ -#define I2CM_MIS_MMIS (1 << 0) /* Bit 0: Maseter Masked Interrupt Status */ -#define I2CM_MIS_CLKMIS (1 << 1) /* Bit 1: Clock Timeout Masked Interrupt Status */ +#define I2CM_MIS_MMIS (1 << 0) /* Bit 0: Maseter Masked Interrupt Status */ +#define I2CM_MIS_CLKMIS (1 << 1) /* Bit 1: Clock Timeout Masked Interrupt Status */ /* I2C Master Masked Interrupt Status (I2CM_ICR) */ -#define I2CM_ICR_MIC (1 << 0) /* Bit 0: Master Masked Interrupt Clear */ -#define I2CM_ICR_CLKC (1 << 1) /* Bit 1: Clock Timeout Interrupt Clear */ +#define I2CM_ICR_MIC (1 << 0) /* Bit 0: Master Masked Interrupt Clear */ +#define I2CM_ICR_CLKC (1 << 1) /* Bit 1: Clock Timeout Interrupt Clear */ /* I2C Master Configuration (I2CM_CR) */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h b/arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h index 544e36cd12..f2d9238d0e 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h @@ -539,63 +539,63 @@ /* I2C Master Interrupt Mask (I2CM_IMR) */ -#define I2CM_IMR_MIM (1 << 0) /* Bit 0: Master Interrupt Mask */ -#define I2CM_IMR_CLKIM (1 << 1) /* Bit 1: Clock Timeout Interrupt Mask */ -#define I2CM_IMR_DMARXIM (1 << 2) /* Bit 2: Receive DMA Interrupt Mask */ -#define I2CM_IMR_DMATXIM (1 << 3) /* Bit 3: Transmit DMA Interrupt Mask */ -#define I2CM_IMR_NACKIM (1 << 4) /* Bit 4: Address/Data NACK Interrupt Mask */ -#define I2CM_IMR_STARTIM (1 << 5) /* Bit 5: START Detection Interrupt Mask */ -#define I2CM_IMR_STOPIM (1 << 6) /* Bit 6: STOP Detection Interrupt Mask */ -#define I2CM_IMR_ARBLOSTIM (1 << 7) /* Bit 7: Arbitration Lost Interrupt Mask */ -#define I2CM_IMR_TXIM (1 << 8) /* Bit 8: Transmit FIFO Request Interrupt Mask */ -#define I2CM_IMR_RXIM (1 << 9) /* Bit 9: Receive FIFO Request Interrupt Mask */ -#define I2CM_IMR_TXFEIM (1 << 10) /* Bit 10: Transmit FIFO Empty Interrupt Mask */ -#define I2CM_IMR_RXFFIM (1 << 11) /* Bit 11: Receive FIFO Full Interrupt Mask */ +#define I2CM_IMR_MIM (1 << 0) /* Bit 0: Master Interrupt Mask */ +#define I2CM_IMR_CLKIM (1 << 1) /* Bit 1: Clock Timeout Interrupt Mask */ +#define I2CM_IMR_DMARXIM (1 << 2) /* Bit 2: Receive DMA Interrupt Mask */ +#define I2CM_IMR_DMATXIM (1 << 3) /* Bit 3: Transmit DMA Interrupt Mask */ +#define I2CM_IMR_NACKIM (1 << 4) /* Bit 4: Address/Data NACK Interrupt Mask */ +#define I2CM_IMR_STARTIM (1 << 5) /* Bit 5: START Detection Interrupt Mask */ +#define I2CM_IMR_STOPIM (1 << 6) /* Bit 6: STOP Detection Interrupt Mask */ +#define I2CM_IMR_ARBLOSTIM (1 << 7) /* Bit 7: Arbitration Lost Interrupt Mask */ +#define I2CM_IMR_TXIM (1 << 8) /* Bit 8: Transmit FIFO Request Interrupt Mask */ +#define I2CM_IMR_RXIM (1 << 9) /* Bit 9: Receive FIFO Request Interrupt Mask */ +#define I2CM_IMR_TXFEIM (1 << 10) /* Bit 10: Transmit FIFO Empty Interrupt Mask */ +#define I2CM_IMR_RXFFIM (1 << 11) /* Bit 11: Receive FIFO Full Interrupt Mask */ /* I2C Master Raw Interrupt Status (I2CM_RIS) */ -#define I2CM_RIS_MRIS (1 << 0) /* Bit 0: Master Raw Interrupt Status */ -#define I2CM_RIS_CLKRIS (1 << 1) /* Bit 1: Clock Timeout Raw Interrupt Status */ -#define I2CM_RIS_DMARXRIS (1 << 2) /* Bit 2: Receive DMA Interrupt Status */ -#define I2CM_RIS_DMATXRIS (1 << 3) /* Bit 3: Transmit DMA Interrupt Status */ -#define I2CM_RIS_NACKRIS (1 << 4) /* Bit 4: Address/Data NACK Interrupt Status */ -#define I2CM_RIS_STARTRIS (1 << 5) /* Bit 5: START Detection Interrupt Status */ -#define I2CM_RIS_STOPRIS (1 << 6) /* Bit 6: STOP Detection Interrupt Status */ -#define I2CM_RIS_ARBLOSTRIS (1 << 7) /* Bit 7: Arbitration Lost Interrupt Status */ -#define I2CM_RIS_TXRIS (1 << 8) /* Bit 8: Transmit FIFO Request Interrupt Status */ -#define I2CM_RIS_RXRIS (1 << 9) /* Bit 9: Receive FIFO Request Interrupt Status */ -#define I2CM_RIS_TXFERIS (1 << 10) /* Bit 10: Transmit FIFO Empty Interrupt Status */ -#define I2CM_RIS_RXFFRIS (1 << 11) /* Bit 11: Receive FIFO Full Interrupt Status */ +#define I2CM_RIS_MRIS (1 << 0) /* Bit 0: Master Raw Interrupt Status */ +#define I2CM_RIS_CLKRIS (1 << 1) /* Bit 1: Clock Timeout Raw Interrupt Status */ +#define I2CM_RIS_DMARXRIS (1 << 2) /* Bit 2: Receive DMA Interrupt Status */ +#define I2CM_RIS_DMATXRIS (1 << 3) /* Bit 3: Transmit DMA Interrupt Status */ +#define I2CM_RIS_NACKRIS (1 << 4) /* Bit 4: Address/Data NACK Interrupt Status */ +#define I2CM_RIS_STARTRIS (1 << 5) /* Bit 5: START Detection Interrupt Status */ +#define I2CM_RIS_STOPRIS (1 << 6) /* Bit 6: STOP Detection Interrupt Status */ +#define I2CM_RIS_ARBLOSTRIS (1 << 7) /* Bit 7: Arbitration Lost Interrupt Status */ +#define I2CM_RIS_TXRIS (1 << 8) /* Bit 8: Transmit FIFO Request Interrupt Status */ +#define I2CM_RIS_RXRIS (1 << 9) /* Bit 9: Receive FIFO Request Interrupt Status */ +#define I2CM_RIS_TXFERIS (1 << 10) /* Bit 10: Transmit FIFO Empty Interrupt Status */ +#define I2CM_RIS_RXFFRIS (1 << 11) /* Bit 11: Receive FIFO Full Interrupt Status */ /* I2C Master Masked Interrupt Status (I2CM_MIS) */ -#define I2CM_MIS_MMIS (1 << 0) /* Bit 0: Maseter Masked Interrupt Status */ -#define I2CM_MIS_CLKMIS (1 << 1) /* Bit 1: Clock Timeout Masked Interrupt Status */ -#define I2CM_MIS_DMARXMIS (1 << 2) /* Bit 2: Receive DMA Interrupt Status */ -#define I2CM_MIS_DMATXMIS (1 << 3) /* Bit 3: Transmit DMA Interrupt Status */ -#define I2CM_MIS_NACKMIS (1 << 4) /* Bit 4: Address/Data NACK Interrupt Status */ -#define I2CM_MIS_STARTMIS (1 << 5) /* Bit 5: START Detection Interrupt Status */ -#define I2CM_MIS_STOPMIS (1 << 6) /* Bit 6: STOP Detection Interrupt Status */ -#define I2CM_MIS_ARBLOSTMIS (1 << 7) /* Bit 7: Arbitration Lost Interrupt Status */ -#define I2CM_MIS_TXMIS (1 << 8) /* Bit 8: Transmit FIFO Request Interrupt Status */ -#define I2CM_MIS_RXMIS (1 << 9) /* Bit 9: Receive FIFO Request Interrupt Status */ -#define I2CM_MIS_TXFEMIS (1 << 10) /* Bit 10: Transmit FIFO Empty Interrupt Status */ -#define I2CM_MIS_RXFFMIS (1 << 11) /* Bit 11: Receive FIFO Full Interrupt Status */ +#define I2CM_MIS_MMIS (1 << 0) /* Bit 0: Maseter Masked Interrupt Status */ +#define I2CM_MIS_CLKMIS (1 << 1) /* Bit 1: Clock Timeout Masked Interrupt Status */ +#define I2CM_MIS_DMARXMIS (1 << 2) /* Bit 2: Receive DMA Interrupt Status */ +#define I2CM_MIS_DMATXMIS (1 << 3) /* Bit 3: Transmit DMA Interrupt Status */ +#define I2CM_MIS_NACKMIS (1 << 4) /* Bit 4: Address/Data NACK Interrupt Status */ +#define I2CM_MIS_STARTMIS (1 << 5) /* Bit 5: START Detection Interrupt Status */ +#define I2CM_MIS_STOPMIS (1 << 6) /* Bit 6: STOP Detection Interrupt Status */ +#define I2CM_MIS_ARBLOSTMIS (1 << 7) /* Bit 7: Arbitration Lost Interrupt Status */ +#define I2CM_MIS_TXMIS (1 << 8) /* Bit 8: Transmit FIFO Request Interrupt Status */ +#define I2CM_MIS_RXMIS (1 << 9) /* Bit 9: Receive FIFO Request Interrupt Status */ +#define I2CM_MIS_TXFEMIS (1 << 10) /* Bit 10: Transmit FIFO Empty Interrupt Status */ +#define I2CM_MIS_RXFFMIS (1 << 11) /* Bit 11: Receive FIFO Full Interrupt Status */ /* I2C Master Masked Interrupt Status (I2CM_ICR) */ -#define I2CM_ICR_MIC (1 << 0) /* Bit 0: Master Masked Interrupt Clear */ -#define I2CM_ICR_CLKC (1 << 1) /* Bit 1: Clock Timeout Interrupt Clear */ -#define I2CM_ICR_DMARXIC (1 << 2) /* Bit 2: Receive DMA Interrupt Clear */ -#define I2CM_ICR_DMATXIC (1 << 3) /* Bit 3: Transmit DMA Interrupt Clear */ -#define I2CM_ICR_NACKIC (1 << 4) /* Bit 4: Address/Data NACK Interrupt Clear */ -#define I2CM_ICR_STARTIC (1 << 5) /* Bit 5: START Detection Interrupt Clear */ -#define I2CM_ICR_STOPIC (1 << 6) /* Bit 6: STOP Detection Interrupt Clear */ -#define I2CM_ICR_ARBLOSTIC (1 << 7) /* Bit 7: Arbitration Lost Interrupt Clear */ -#define I2CM_ICR_TXIC (1 << 8) /* Bit 8: Transmit FIFO Request Interrupt Clear */ -#define I2CM_ICR_RXIC (1 << 9) /* Bit 9: Receive FIFO Request Interrupt Clear */ -#define I2CM_ICR_TXFEIC (1 << 10) /* Bit 10: Transmit FIFO Empty Interrupt Mask */ -#define I2CM_ICR_RXFFIC (1 << 11) /* Bit 11: Receive FIFO Full Interrupt Clear */ +#define I2CM_ICR_MIC (1 << 0) /* Bit 0: Master Masked Interrupt Clear */ +#define I2CM_ICR_CLKC (1 << 1) /* Bit 1: Clock Timeout Interrupt Clear */ +#define I2CM_ICR_DMARXIC (1 << 2) /* Bit 2: Receive DMA Interrupt Clear */ +#define I2CM_ICR_DMATXIC (1 << 3) /* Bit 3: Transmit DMA Interrupt Clear */ +#define I2CM_ICR_NACKIC (1 << 4) /* Bit 4: Address/Data NACK Interrupt Clear */ +#define I2CM_ICR_STARTIC (1 << 5) /* Bit 5: START Detection Interrupt Clear */ +#define I2CM_ICR_STOPIC (1 << 6) /* Bit 6: STOP Detection Interrupt Clear */ +#define I2CM_ICR_ARBLOSTIC (1 << 7) /* Bit 7: Arbitration Lost Interrupt Clear */ +#define I2CM_ICR_TXIC (1 << 8) /* Bit 8: Transmit FIFO Request Interrupt Clear */ +#define I2CM_ICR_RXIC (1 << 9) /* Bit 9: Receive FIFO Request Interrupt Clear */ +#define I2CM_ICR_TXFEIC (1 << 10) /* Bit 10: Transmit FIFO Empty Interrupt Mask */ +#define I2CM_ICR_RXFFIC (1 << 11) /* Bit 11: Receive FIFO Full Interrupt Clear */ /* I2C Master Configuration (I2CM_CR) */