arch/mips/src/mips32: In up_idle, the kludge that was conditionally enabled if the work queue was enable appears to be needed even when he work queue is not enabled on the PIC32MZ.
arch/mips/src/pic32mz: Fix some typos in debug instrumentation in pic32mz-gpio.c; fix some types releated to UART5 configuration in pic32mz-serial.c. configs/flipnclick-pic32mz/nsh: Switch serial console to UART3. There is some problem with the UART4 RX pin documentation or configuration.
This commit is contained in:
Gregory Nutt
parent
0e6ef003ff
commit
73ec87109f
@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/mips/src/common/up_idle.c
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*
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* Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2011-2012, 2016, 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -69,27 +69,23 @@ void up_idle(void)
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sched_process_timer();
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#else
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irqstate_t flags;
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/* This would be an appropriate place to put some MCU-specific logic to
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* sleep in a reduced power mode until an interrupt occurs to save power
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*/
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/* This is a kludge that I still don't understand. The call to kmm_trysemaphore()
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* in the os_start.c IDLE loop seems necessary for the good health of the IDLE
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* loop. When the work queue is enabled, this logic is removed from the IDLE
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* loop and it appears that we are somehow left idling with interrupts non-
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* functional. The following should be no-op, it just disables then re-enables
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* interrupts. But it fixes the problem and will stay here until I understand
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* the problem/fix better.
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/* This is a kludge that I still don't understand. It appears that we are
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* somehow left idling with interrupts non-functional. The following should
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* be no-op, it just disables then re-enables interrupts. But it fixes the
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* problem and will stay here until I understand the problem/fix better.
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*
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* And no, the contents of the CP0 status register are not incorrect. But for
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* some reason the status register needs to be re-written again on this thread
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* for it to take effect. This might be a PIC32-only issue?
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* And no, the contents of the CP0 status register are not incorrect. But
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* for some reason the status register needs to be re-written again on this
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* thread for it to take effect. This might be a PIC32-only issue?
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*/
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#ifdef CONFIG_SCHED_WORKQUEUE
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irqstate_t flags = enter_critical_section();
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leave_critical_section(flags);
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#endif
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flags = up_irq_save();
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up_irq_restore(flags);
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#endif
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}
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/mips/src/pic32mz/pic32mz-gpio.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -332,10 +332,10 @@ void pic32mz_dumpgpio(uint32_t pinset, const char *msg)
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getreg32(base + PIC32MZ_IOPORT_PORT_OFFSET),
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getreg32(base + PIC32MZ_IOPORT_LAT_OFFSET),
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getreg32(base + PIC32MZ_IOPORT_ODC_OFFSET));
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gpioinfo(" CNCON: %08x CNEN: %08x CNPUE: %08x\n",
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getreg32(PIC32MZ_IOPORT_CNCON),
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getreg32(PIC32MZ_IOPORT_CNEN),
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getreg32(PIC32MZ_IOPORT_CNPUE));
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gpioinfo(" CNCON: %08x CNEN: %08x CNPU: %08x\n",
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getreg32(base + PIC32MZ_IOPORT_CNCON_OFFSET),
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getreg32(base + PIC32MZ_IOPORT_CNEN_OFFSET),
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getreg32(base + PIC32MZ_IOPORT_CNPU_OFFSET));
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sched_unlock();
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}
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}
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/mips/src/pic32mz/pic32mz-serial.c
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*
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* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2017-2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -96,10 +96,10 @@
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# define CONSOLE_DEV g_uart4port /* UART4 is console */
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# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */
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# define UART4_ASSIGNED 1
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#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart5port /* UART4 is console */
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# define TTYS0_DEV g_uart5port /* UART4 is ttyS0 */
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# define UART4_ASSIGNED 1
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#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart5port /* UART5 is console */
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# define TTYS0_DEV g_uart5port /* UART5 is ttyS0 */
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# define UART5_ASSIGNED 1
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#elif defined(CONFIG_UART6_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart6port /* UART6 is console */
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# define TTYS5_DEV g_uart6port /* UART6 is ttyS0 */
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@ -118,9 +118,9 @@
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# elif defined(CONFIG_PIC32MZ_UART4)
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# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */
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# define UART4_ASSIGNED 1
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# elif defined(CONFIG_PIC32MZ_UART4)
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# define TTYS0_DEV g_uart5port /* UART4 is ttyS0 */
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# define UART4_ASSIGNED 1
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# elif defined(CONFIG_PIC32MZ_UART5)
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# define TTYS0_DEV g_uart5port /* UART5 is ttyS0 */
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# define UART5_ASSIGNED 1
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# elif defined(CONFIG_PIC32MZ_UART6)
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# define TTYS0_DEV g_uart6port /* UART6 is ttyS0 */
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# define UART6_ASSIGNED 1
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@ -1,4 +1,6 @@
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# CONFIG_ARCH_RAMFUNCS is not set
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# CONFIG_PIC32MZ_DEBUGGER_ENABLE is not set
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# CONFIG_PIC32MZ_TRACE_ENABLE is not set
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CONFIG_ARCH_BOARD_FLIPNCLICK_PIC32MZ=y
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CONFIG_ARCH_BOARD="flipnclick-pic32mz"
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CONFIG_ARCH_CHIP_PIC32MZ=y
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@ -32,7 +34,7 @@ CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LINELEN=64
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CONFIG_NSH_READLINE=y
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CONFIG_PIC32MZ_ICESEL_CH2=y
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CONFIG_PIC32MZ_UART4=y
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CONFIG_PIC32MZ_UART3=y
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CONFIG_PREALLOC_MQ_MSGS=4
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_PREALLOC_WDOGS=8
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@ -44,6 +46,6 @@ CONFIG_SDCLONE_DISABLE=y
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CONFIG_START_DAY=7
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CONFIG_START_MONTH=3
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CONFIG_START_YEAR=2012
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CONFIG_UART4_SERIAL_CONSOLE=y
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CONFIG_UART3_SERIAL_CONSOLE=y
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CONFIG_USER_ENTRYPOINT="nsh_main"
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CONFIG_WDOG_INTRESERVE=1
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