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xtensa_context.S: Save and restore SCOMPARE1 when necessary.

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SCOMPARE1 is used by some atomic instructions and need to be preserved
during a context switch.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2021-10-12 14:32:55 +02:00 committed by Gustavo Henrique Nihei
parent 1bc3ab513d
commit 7420f245bc
2 changed files with 19 additions and 2 deletions
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9
arch/xtensa/include/irq.h
View File

@ -86,7 +86,14 @@
#define REG_EXCCAUSE (19) #define REG_EXCCAUSE (19)
#define REG_EXCVADDR (20) #define REG_EXCVADDR (20)
#define _REG_LOOPS_START (21) #define _REG_EXTRA_START (21)
#if XCHAL_HAVE_S32C1I != 0
# define REG_SCOMPARE1 (_REG_EXTRA_START + 0)
# define _REG_LOOPS_START (_REG_EXTRA_START + 1)
#else
# define _REG_LOOPS_START _REG_EXTRA_START
#endif
#if XCHAL_HAVE_LOOPS != 0 #if XCHAL_HAVE_LOOPS != 0
# define REG_LBEG (_REG_LOOPS_START + 0) # define REG_LBEG (_REG_LOOPS_START + 0)

12
arch/xtensa/src/common/xtensa_context.S
View File

@ -344,6 +344,11 @@ _xtensa_save_hook:
rsr a3, SAR rsr a3, SAR
s32i a3, a2, (4 * REG_SAR) s32i a3, a2, (4 * REG_SAR)
#if XCHAL_HAVE_S32C1I != 0
rsr a3, SCOMPARE1
s32i a3, a2, (4 * REG_SCOMPARE1)
#endif
#if XCHAL_HAVE_LOOPS != 0 #if XCHAL_HAVE_LOOPS != 0
rsr a3, LBEG rsr a3, LBEG
s32i a3, a2, (4 * REG_LBEG) s32i a3, a2, (4 * REG_LBEG)
@ -469,9 +474,14 @@ _xtensa_context_restore:
#error Overly support is not implemented #error Overly support is not implemented
#endif #endif
#if XCHAL_HAVE_S32C1I != 0
l32i a3, a2, (4 * REG_SCOMPARE1)
wsr a3, SCOMPARE1
#endif
l32i a3, a2, (4 * REG_SAR) l32i a3, a2, (4 * REG_SAR)
l32i sp, a2, (4 * REG_A1)
wsr a3, SAR wsr a3, SAR
l32i sp, a2, (4 * REG_A1)
l32i a3, a2, (4 * REG_A3) l32i a3, a2, (4 * REG_A3)
l32i a4, a2, (4 * REG_A4) l32i a4, a2, (4 * REG_A4)
l32i a5, a2, (4 * REG_A5) l32i a5, a2, (4 * REG_A5)