diff --git a/arch/arm/src/sam3u/sam3u_hsmci.c b/arch/arm/src/sam3u/sam3u_hsmci.c
index 17604ae03b..d41546058a 100755
--- a/arch/arm/src/sam3u/sam3u_hsmci.c
+++ b/arch/arm/src/sam3u/sam3u_hsmci.c
@@ -289,12 +289,10 @@ struct sam3u_dev_s
 #if defined(CONFIG_HSMCI_XFRDEBUG) || defined(CONFIG_HSMCI_CMDDEBUG)
 struct sam3u_hsmciregs_s
 {
-  uint32_t cr;    /* Control Register */
   uint32_t mr;    /* Mode Register */
   uint32_t dtor;  /* Data Timeout Register */
   uint32_t sdcr;  /* SD/SDIO Card Register */
   uint32_t argr;  /* Argument Register */
-  uint32_t cmdr;  /* Command Register */
   uint32_t blkr;  /* Block Register */
   uint32_t cstor; /* Completion Signal Timeout Register */
   uint32_t rsp0;  /* Response Register 0 */
@@ -635,7 +633,7 @@ static void sam3u_disablexfrints(struct sam3u_dev_s *priv)
  * Name: sam3u_disable
  *
  * Description:
- *   Enable/disable the HSMCI
+ *   Disable the HSMCI
  *
  ****************************************************************************/
 
@@ -688,12 +686,10 @@ static inline void sam3u_enable(void)
 #if defined(CONFIG_HSMCI_XFRDEBUG) || defined(CONFIG_HSMCI_CMDDEBUG)
 static void sam3u_hsmcisample(struct sam3u_hsmciregs_s *regs)
 {
-  regs->cr    = getreg32(SAM3U_HSMCI_CR);
   regs->mr    = getreg32(SAM3U_HSMCI_MR);
   regs->dtor  = getreg32(SAM3U_HSMCI_DTOR);
   regs->sdcr  = getreg32(SAM3U_HSMCI_SDCR);
   regs->argr  = getreg32(SAM3U_HSMCI_ARGR);
-  regs->cmdr  = getreg32(SAM3U_HSMCI_CMDR);
   regs->blkr  = getreg32(SAM3U_HSMCI_BLKR);
   regs->cstor = getreg32(SAM3U_HSMCI_CSTOR);
   regs->rsp0  = getreg32(SAM3U_HSMCI_RSPR0);
@@ -721,12 +717,10 @@ static void sam3u_hsmcisample(struct sam3u_hsmciregs_s *regs)
 static void sam3u_hsmcidump(struct sam3u_hsmciregs_s *regs, const char *msg)
 {
   fdbg("HSMCI Registers: %s\n", msg);
-  fdbg("     CR[%08x]: %08x\n", SAM3U_HSMCI_CR,    regs->cr);
   fdbg("     MR[%08x]: %08x\n", SAM3U_HSMCI_MR,    regs->mr);
   fdbg("   DTOR[%08x]: %08x\n", SAM3U_HSMCI_DTOR,  regs->dtor);
   fdbg("   SDCR[%08x]: %08x\n", SAM3U_HSMCI_SDCR,  regs->sdcr);
   fdbg("   ARGR[%08x]: %08x\n", SAM3U_HSMCI_ARGR,  regs->argr);
-  fdbg("   CMDR[%08x]: %08x\n", SAM3U_HSMCI_CMDR,  regs->cmdr);
   fdbg("   BLKR[%08x]: %08x\n", SAM3U_HSMCI_BLKR,  regs->blkr);
   fdbg("  CSTOR[%08x]: %08x\n", SAM3U_HSMCI_CSTOR, regs->cstor);
   fdbg("  RSPR0[%08x]: %08x\n", SAM3U_HSMCI_RSPR0, regs->rsp0);
@@ -1226,6 +1220,7 @@ static void sam3u_reset(FAR struct sdio_dev_s *dev)
 
   flags = irqsave();
   putreg32((1 << SAM3U_PID_HSMCI), SAM3U_PMC_PCER);
+  fdbg("PCSR: %08x\n", getreg32(SAM3U_PMC_PCSR));
   
   /* Reset the MCI */
 
@@ -1251,7 +1246,7 @@ static void sam3u_reset(FAR struct sdio_dev_s *dev)
 
   putreg32(HSMCI_SDCR_SDCSEL_SLOTA | HSMCI_SDCR_SDCBUS_4BIT, SAM3U_HSMCI_SDCR);
 
-  /* Enable the MCI and the Power Saving */
+  /* Enable the MCI controller */
 
   putreg32(HSMCI_CR_MCIEN, SAM3U_HSMCI_CR);
 
@@ -2408,6 +2403,11 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
   sam3u_configgpio(GPIO_MCI_CK);     /* SD clock */
   sam3u_configgpio(GPIO_MCI_DA);     /* Command/Response */
 
+#ifdef CONFIG_DEBUG_FS
+  sam3u_dumpgpio(GPIO_PORT_PIOA, "Pins: 3-8");
+  sam3u_dumpgpio(GPIO_PORT_PIOB, "Pins: 28-31");
+#endif
+
   /* Reset the card and assure that it is in the initial, unconfigured
    * state.
    */
diff --git a/arch/arm/src/sam3u/sam3u_internal.h b/arch/arm/src/sam3u/sam3u_internal.h
index 96cb97008d..f38dea92dc 100755
--- a/arch/arm/src/sam3u/sam3u_internal.h
+++ b/arch/arm/src/sam3u/sam3u_internal.h
@@ -518,6 +518,20 @@ EXTERN void sam3u_gpioirqdisable(int irq);
 #  define sam3u_gpioirqdisable(irq)
 #endif
 
+/************************************************************************************
+ * Function:  sam3u_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the base address of the provided pinset.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG
+EXTERN int sam3u_dumpgpio(uint32_t pinset, const char *msg);
+#else
+#  define sam3u_dumpgpio(p,m)
+#endif
+
 /****************************************************************************
  * Name: sam3u_dmachannel
  *
diff --git a/arch/arm/src/sam3u/sam3u_pio.c b/arch/arm/src/sam3u/sam3u_pio.c
index 29eb5e833b..1300aeb376 100755
--- a/arch/arm/src/sam3u/sam3u_pio.c
+++ b/arch/arm/src/sam3u/sam3u_pio.c
@@ -66,6 +66,10 @@
  * Private Data
  ****************************************************************************/
 
+#ifdef CONFIG_DEBUG
+static const char g_portchar[4]   = { 'A', 'B', 'C', 'D' };
+#endif
+
 /****************************************************************************
  * Private Function Prototypes
  ****************************************************************************/
@@ -337,3 +341,54 @@ bool sam3u_gpioread(uint16_t pinset)
 
   return (regval & pin) != 0;
 }
+
+/************************************************************************************
+ * Function:  sam3u_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the base address of the provided pinset.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG
+int sam3u_dumpgpio(uint32_t pinset, const char *msg)
+{
+  irqstate_t    flags;
+  uintptr_t     base;
+  unsigned int  pin;
+  unsigned int  port;
+
+  /* Get the base address associated with the PIO port */
+
+  pin  = sam3u_gpiopin(pinset);
+  port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  base = SAM3U_PION_BASE(port);
+
+  /* The following requires exclusive access to the GPIO registers */
+
+  flags = irqsave();
+  lldbg("PIO%c pinset: %08x base: %08x -- %s\n",
+        g_portchar[port], pinset, base, msg);
+  lldbg("    PSR: %08x    OSR: %08x   IFSR: %08x   ODSR: %08x\n",
+        getreg32(base + SAM3U_PIO_PSR_OFFSET), getreg32(base + SAM3U_PIO_OSR_OFFSET),
+        getreg32(base + SAM3U_PIO_IFSR_OFFSET), getreg32(base + SAM3U_PIO_ODSR_OFFSET));
+  lldbg("   PDSR: %08x    IMR: %08x    ISR: %08x   MDSR: %08x\n",
+        getreg32(base + SAM3U_PIO_PDSR_OFFSET), getreg32(base + SAM3U_PIO_IMR_OFFSET),
+        getreg32(base + SAM3U_PIO_ISR_OFFSET), getreg32(base + SAM3U_PIO_MDSR_OFFSET));
+  lldbg("   PUSR: %08x   ABSR: %08x SCIFSR: %08x  DIFSR: %08x\n",
+        getreg32(base + SAM3U_PIO_PUSR_OFFSET), getreg32(base + SAM3U_PIO_ABSR_OFFSET),
+        getreg32(base + SAM3U_PIO_SCIFSR_OFFSET), getreg32(base + SAM3U_PIO_DIFSR_OFFSET));
+  lldbg(" IFDGSR: %08x   SCDR: %08x   OWSR: %08x  AIMMR: %08x\n",
+        getreg32(base + SAM3U_PIO_IFDGSR_OFFSET), getreg32(base + SAM3U_PIO_SCDR_OFFSET),
+        getreg32(base + SAM3U_PIO_OWSR_OFFSET), getreg32(base + SAM3U_PIO_AIMMR_OFFSET));
+  lldbg("    ESR: %08x    LSR: %08x   ELSR: %08x FELLSR: %08x\n",
+        getreg32(base + SAM3U_PIO_ESR_OFFSET), getreg32(base + SAM3U_PIO_LSR_OFFSET),
+        getreg32(base + SAM3U_PIO_ELSR_OFFSET), getreg32(base + SAM3U_PIO_FELLSR_OFFSET));
+  lldbg(" FRLHSR: %08x LOCKSR: %08x   WPMR: %08x   WPSR: %08x\n",
+        getreg32(base + SAM3U_PIO_FRLHSR_OFFSET), getreg32(base + SAM3U_PIO_LOCKSR_OFFSET),
+        getreg32(base + SAM3U_PIO_WPMR_OFFSET), getreg32(base + SAM3U_PIO_WPSR_OFFSET));
+  irqrestore(flags);
+  return OK;
+}
+#endif
+