SAMV71: Quick'n'dirty port of the SAMA5 SSC driver to the SAM7. The IP is compatible but there are still some DMA- and Cache-related issues that need to be worked out.

arch/arm/include/samv7/samv71_irq.h

@@ -72,7 +72,7 @@
 #define SAM_PID_TWIHS0        (19)  /* Two-Wire Interface 0 */
 #define SAM_PID_TWIHS1        (20)  /* Two-Wire Interface 1 */
 #define SAM_PID_SPI0          (21)  /* Serial Peripheral Interface 0 */
-#define SAM_PID_SSC           (22)  /* Synchronous Serial Controller */
+#define SAM_PID_SSC0          (22)  /* Synchronous Serial Controller */
 #define SAM_PID_TC0           (23)  /* Timer Counter 0 */
 #define SAM_PID_TC1           (24)  /* Timer Counter 1 */
 #define SAM_PID_TC2           (25)  /* Timer Counter 2 */
@@ -142,7 +142,7 @@
 #define SAM_IRQ_TWIHS0        (SAM_IRQ_EXTINT+SAM_PID_TWIHS0) /* Two-Wire Interface 0 */
 #define SAM_IRQ_TWIHS1        (SAM_IRQ_EXTINT+SAM_PID_TWIHS1) /* Two-Wire Interface 1 */
 #define SAM_IRQ_SPI0          (SAM_IRQ_EXTINT+SAM_PID_SPI0)   /* Serial Peripheral Interface 0 */
-#define SAM_IRQ_SSC           (SAM_IRQ_EXTINT+SAM_PID_SSC)    /* Synchronous Serial Controller */
+#define SAM_IRQ_SSC0          (SAM_IRQ_EXTINT+SAM_PID_SSC)    /* Synchronous Serial Controller */
 #define SAM_IRQ_TC0           (SAM_IRQ_EXTINT+SAM_PID_TC0)    /* Timer Counter 0 */
 #define SAM_IRQ_TC1           (SAM_IRQ_EXTINT+SAM_PID_TC1)    /* Timer Counter 1 */
 #define SAM_IRQ_TC2           (SAM_IRQ_EXTINT+SAM_PID_TC2)    /* Timer Counter 2 */

arch/arm/src/sama5/sam_ssc.c

@@ -88,8 +88,8 @@
 #  error CONFIG_AUDIO required by this driver
 #endif
 
-#ifndef SAMA5_SSC_MAXINFLIGHT
+#ifndef CONFIG_SAMA5_SSC_MAXINFLIGHT
-#  define SAMA5_SSC_MAXINFLIGHT 16
+#  define CONFIG_SAMA5_SSC_MAXINFLIGHT 16
 #endif
 
 /* Assume no RX/TX support until we learn better */
@@ -348,8 +348,7 @@
 #elif defined(ATSAMA5D4)
   /* System Bus Interfaces
    *
-   * Both SSC0 and SSC1 are APB1; HSMCI1 is on H32MX.  Both are accessible
+   * Both SSC0 and SSC1 are APB1.  Both are accessible on MATRIX IF1.
-   * on MATRIX IF1.
    *
    * Memory is available on either port 5 (IF0 for both XDMAC0 and 1) or
    * port 6 (IF1 for both XDMAC0 and 1).
@@ -508,7 +507,7 @@ struct sam_ssc_s
 
   sem_t bufsem;                   /* Buffer wait semaphore */
   struct sam_buffer_s *freelist;  /* A list a free buffer containers */
-  struct sam_buffer_s containers[SAMA5_SSC_MAXINFLIGHT];
+  struct sam_buffer_s containers[CONFIG_SAMA5_SSC_MAXINFLIGHT];
 
   /* Debug stuff */
 
@@ -792,7 +791,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset,
  * Name: ssc_physregaddr
  *
  * Description:
- *   Return the physical address of an HSMCI register
+ *   Return the physical address of an SSC register
  *
  ****************************************************************************/
 
@@ -1058,9 +1057,9 @@ static void ssc_buf_initialize(struct sam_ssc_s *priv)
   int i;
 
   priv->freelist = NULL;
-  sem_init(&priv->bufsem, 0, SAMA5_SSC_MAXINFLIGHT);
+  sem_init(&priv->bufsem, 0, CONFIG_SAMA5_SSC_MAXINFLIGHT);
 
-  for (i = 0; i < SAMA5_SSC_MAXINFLIGHT; i++)
+  for (i = 0; i < CONFIG_SAMA5_SSC_MAXINFLIGHT; i++)
     {
       ssc_buf_free(priv, &priv->containers[i]);
     }

arch/arm/src/samv7/Kconfig

@@ -142,6 +142,10 @@ config SAMV7_QSPI_IS_SPI
 	bool
 	default n
 
+config SAMV7_SSC
+	bool
+	default n
+
 config SAMV7_HAVE_TWIHS2
 	bool
 	default n
@@ -278,9 +282,10 @@ config SAMV7_SPI1
 	select SAMV7_HAVE_SPI
 	select SPI
 
-config SAMV7_SSC
+config SAMV7_SSC0
 	bool "Synchronous Serial Controller (SSC)"
 	default n
+	select SAMV7_SSC
 
 config SAMV7_TC0
 	bool "Timer/Counter 0 (TC0)"
@@ -540,3 +545,394 @@ config SAMV7_TWIHS_REGDEBUG
 
 endmenu # TWIHS device driver options
 endif # SAMV7_TWIHS0 || SAMV7_TWIHS1 || SAMV7_TWIHS2
+
+if SAMV7_SSC
+menu "SSC Configuration"
+
+config SAMV7_SSC_MAXINFLIGHT
+	int "SSC queue size"
+	default 16
+	---help---
+		This is the total number of transfers, both RX and TX, that can be
+		enqueue before the caller is required to wait.  This setting
+		determines the number certain queue data structures that will be
+		pre-allocated.
+
+if SAMV7_SSC0
+comment "SSC0 Configuration"
+
+config SAMV7_SSC0_DATALEN
+	int "Data width (bits)"
+	default 16
+	---help---
+		Data width in bits.  This is a default value and may be change
+		via the I2S interface
+
+config SAMV7_SSC0_RX
+	bool "Enable I2C receiver"
+	default n
+	---help---
+		Enable I2S receipt logic
+
+if SAMV7_SSC0_RX
+
+choice
+	prompt "Receiver clock source"
+	default SAMV7_SSC0_RX_MCKDIV
+
+config SAMV7_SSC0_RX_RKINPUT
+	bool "RK input"
+	---help---
+		The SSC receiver clock is an external clock provided on the RK input
+		pin.  Sample rate determined by the external clock frequency.
+
+config SAMV7_SSC0_RX_TXCLK
+	bool "Transmitter Clock"
+	---help---
+		The SSC receiver clock is transmitter clock.  RX sample rate is the same
+		as the TX sample rate.
+
+config SAMV7_SSC0_RX_MCKDIV
+	bool "MCK/2"
+	---help---
+		The SSC receiver clock is the MCK/2 divided by a up to 4095.  Desired
+		sample rate must be provided below.
+
+endchoice # Receiver clock source
+
+if !SAMV7_SSC0_RX_RKINPUT
+choice
+	prompt "Receiver output clock"
+	default SAMV7_SSC0_RX_RKOUTPUT_NONE
+
+config SAMV7_SSC0_RX_RKOUTPUT_NONE
+	bool "None"
+
+config SAMV7_SSC0_RX_RKOUTPUT_CONT
+	bool "Continuous"
+
+config SAMV7_SSC0_RX_RKOUTPUT_XFR
+	bool "Only during transfers"
+
+endchoice # Receiver output clock
+endif # !SAMV7_SSC0_RX_RKINPUT
+
+config SAMV7_SSC0_RX_FSLEN
+	int "Receive Frame Sync Length"
+	default 1
+	range 1 255
+	---help---
+		This setting determines the pulse length of the Receive Frame Sync
+		signal in units of receive clock periods.
+
+config SAMV7_SSC0_RX_STTDLY
+	int "Receive Start Delay Length"
+	default 0
+	range 0 255
+	---help---
+		This setting determines the pulse length to the start of data in
+		receive clock periods.  It must be greater than or equal to the RX
+		frame synch length.  Zero means no start delay.
+
+endif # SAMV7_SSC0_RX
+
+config SAMV7_SSC0_TX
+	bool "Enable I2C transmitter"
+	default n
+	---help---
+		Enable I2S transmission logic
+
+if SAMV7_SSC0_TX
+
+choice
+	prompt "Transmitter clock source"
+	default SAMV7_SSC0_TX_MCKDIV
+
+config SAMV7_SSC0_TX_TKINPUT
+	bool "TK input"
+	---help---
+		The SSC transmitter clock is an external clock provided on the TK input
+		pin.  Sample rate determined by the external clock frequency.
+
+config SAMV7_SSC0_TX_RXCLK
+	bool "Receiver Clock"
+	---help---
+		The SSC transmitter clock is receiver clock.  TX sample rate is the same
+		as the RX sample rate.
+
+config SAMV7_SSC0_TX_MCKDIV
+	bool "MCK/2"
+	---help---
+		The SSC transmitter clock is the MCK/2 divided by a up to 4095.  Desired
+		sample rate must be provided below.
+
+endchoice # Transmitter clock source
+
+if !SAMV7_SSC0_TX_TKINPUT
+choice
+	prompt "Transmitter output clock"
+	default SAMV7_SSC0_TX_TKOUTPUT_NONE
+
+config SAMV7_SSC0_TX_TKOUTPUT_NONE
+	bool "None"
+
+config SAMV7_SSC0_TX_TKOUTPUT_CONT
+	bool "Continuous"
+
+config SAMV7_SSC0_TX_TKOUTPUT_XFR
+	bool "Only during transfers"
+
+endchoice # Receiver output clock
+endif # !SAMV7_SSC0_TX_TKINPUT
+
+config SAMV7_SSC0_TX_FSLEN
+	int "Transmit Frame Sync Length"
+	default 1
+	range 0 255
+	---help---
+		This setting define the length of the Transmit Frame Sync signal in
+		units of transmit clock periods.  A value of zero disables this
+		feature.  In that case the TD line is driven with the default value
+		during the Transmit Frame Sync signal.
+
+config SAMV7_SSC0_TX_STTDLY
+	int "Transmit Start Delay Length"
+	default 0
+	range 0 255
+	---help---
+		This setting determines the pulse length to the start of data in
+		transmit clock periods.  It must be greater than or equal to the RX
+		frame synch length.  Zero means no start delay.
+
+endif # SAMV7_SSC0_TX
+
+config SAMV7_SSC0_MCKDIV_SAMPLERATE
+	int "Sample rate"
+	default 48000
+	depends on SAMV7_SSC0_RX_MCKDIV || SAMV7_SSC0_TX_MCKDIV
+	---help---
+		If the either the receiver or transmitter clock is provided by MCK/2 divided
+		down, then the sample rate must be provided.  The bit rate will be the product
+		of the sample rate and the data width.  The SSC driver will determine the best
+		divider to obtain that bit rate (up to 4095).  If the bit rate can be realized
+		by dividing down the MCK/2, a compile time error will occur.
+
+config SAMV7_SSC0_LOOPBACK
+	bool "Loopback mode"
+	default n
+	depends on SAMV7_SSC0_TX && SAMV7_SSC0_RX
+	---help---
+		If both the receiver and transmitter are enabled, then the SSC can
+		be configured in loopback mode.  This setting selects SSC loopback
+		and will cause the LOOP bit to be set in the SSC_RFMR register. In
+		this case, RD is connected to TD, RF is connected to TF and RK is
+		connected to TK.
+
+endif # SAMV7_SSC0
+
+if SAMV7_SSC1
+comment "SSC1 Configuration"
+
+config SAMV7_SSC1_DATALEN
+	int "Data width (bits)"
+	default 16
+	---help---
+		Data width in bits.  This is a default value and may be change
+		via the I2S interface
+
+config SAMV7_SSC1_RX
+	bool "Enable I2C receiver"
+	default n
+	---help---
+		Enable I2S receipt logic
+
+if SAMV7_SSC1_RX
+
+choice
+	prompt "Receiver clock source"
+	default SAMV7_SSC1_RX_MCKDIV
+
+config SAMV7_SSC1_RX_RKINPUT
+	bool "RK input"
+	---help---
+		The SSC receiver clock is an external clock provided on the RK input
+		pin.  Sample rate determined by the external clock frequency.
+
+config SAMV7_SSC1_RX_TXCLK
+	bool "Transmitter Clock"
+	---help---
+		The SSC receiver clock is transmitter clock.  RX sample rate is the same
+		as the TX sample rate.
+
+config SAMV7_SSC1_RX_MCKDIV
+	bool "MCK/2"
+	---help---
+		The SSC receiver clock is the MCK/2 divided by a up to 4095.  Desired
+		sample rate must be provided below.
+
+endchoice # Receiver clock source
+
+if !SAMV7_SSC1_RX_RKINPUT
+choice
+	prompt "Receiver output clock"
+	default SAMV7_SSC1_RX_RKOUTPUT_NONE
+
+config SAMV7_SSC1_RX_RKOUTPUT_NONE
+	bool "None"
+
+config SAMV7_SSC1_RX_RKOUTPUT_CONT
+	bool "Continuous"
+
+config SAMV7_SSC1_RX_RKOUTPUT_XFR
+	bool "Only during transfers"
+
+endchoice # Receiver output clock
+endif # !SAMV7_SSC1_RX_RKINPUT
+
+config SAMV7_SSC1_RX_FSLEN
+	int "Receive Frame Sync Length"
+	default 1
+	range 1 255
+	---help---
+		This setting determines the pulse length of the Receive Frame Sync
+		signal in units of receive clock periods.
+
+config SAMV7_SSC1_RX_STTDLY
+	int "Receive Start Delay Length"
+	default 0
+	range 0 255
+	---help---
+		This setting determines the pulse length to the start of data of
+		receive clock periods.  It must be greater than or equal to the RX
+		frame synch length.  Zero means no start delay.
+
+endif # SAMV7_SSC1_RX
+
+config SAMV7_SSC1_TX
+	bool "Enable I2C transmitter"
+	default n
+	---help---
+		Enable I2S transmission logic
+
+if SAMV7_SSC1_TX
+
+choice
+	prompt "Transmitter clock source"
+	default SAMV7_SSC1_TX_MCKDIV
+
+config SAMV7_SSC1_TX_TKINPUT
+	bool "TK input"
+	---help---
+		The SSC transmitter clock is an external clock provided on the TK input
+		pin.  Sample rate determined by the external clock frequency.
+
+config SAMV7_SSC1_TX_RXCLK
+	bool "Receiver Clock"
+	---help---
+		The SSC transmitter clock is receiver clock.  TX sample rate is the same
+		as the RX sample rate.
+
+config SAMV7_SSC1_TX_MCKDIV
+	bool "MCK/2"
+	---help---
+		The SSC transmitter clock is the MCK/2 divided by a up to 4095.  Desired
+		sample rate must be provided below.
+
+endchoice # Transmitter clock source
+
+if !SAMV7_SSC1_TX_TKINPUT
+choice
+	prompt "Transmitter output clock"
+	default SAMV7_SSC1_TX_TKOUTPUT_NONE
+
+config SAMV7_SSC1_TX_TKOUTPUT_NONE
+	bool "None"
+
+config SAMV7_SSC1_TX_TKOUTPUT_CONT
+	bool "Continuous"
+
+config SAMV7_SSC1_TX_TKOUTPUT_XFR
+	bool "Only during transfers"
+
+endchoice # Receiver output clock
+endif # !SAMV7_SSC1_TX_TKINPUT
+
+config SAMV7_SSC1_TX_FSLEN
+	int "Receive Frame Sync Length"
+	default 1
+	range 0 255
+	---help---
+		This setting define the length of the Transmit Frame Sync signal in
+		units of transmit clock periods.  A value of zero disables this
+		feature.  In that case the TD line is driven with the default value
+		during the Transmit Frame Sync signal.
+
+config SAMV7_SSC1_TX_STTDLY
+	int "Transmit Start Delay Length"
+	default 0
+	range 0 255
+	---help---
+		This setting determines the pulse length to the start of data in
+		transmit clock periods.  It must be greater than or equal to the RX
+		frame synch length.  Zero means no start delay.
+
+endif # SAMV7_SSC1_TX
+
+config SAMV7_SSC1_MCKDIV_SAMPLERATE
+	int "Sample rate"
+	default 48000
+	depends on SAMV7_SSC1_RX_MCKDIV || SAMV7_SSC1_TX_MCKDIV
+	---help---
+		If the either the receiver or transmitter clock is provided by MCK/2 divided
+		down, then the sample rate must be provided.  The bit rate will be the product
+		of the sample rate and the data width.  The SSC driver will determine the best
+		divider to obtain that bit rate (up to 4095).  If the bit rate can be realized
+		by dividing down the MCK/2, a compile time error will occur.
+
+config SAMV7_SSC1_LOOPBACK
+	bool "Loopback mode"
+	default n
+	depends on SAMV7_SSC1_TX && SAMV7_SSC1_RX
+	---help---
+		If both the receiver and transmitter are enabled, then the SSC can
+		be configured in loopback mode.  This setting selects SSC loopback
+		and will cause the LOOP bit to be set in the SSC_RFMR register. In
+		this case, RD is connected to TD, RF is connected to TF and RK is
+		connected to TK.
+
+endif # SAMV7_SSC1
+
+config SAMV7_SSC_DMADEBUG
+	bool "SSC DMA transfer debug"
+	depends on DEBUG && DEBUG_DMA
+	default n
+	---help---
+		Enable special debug instrumentation analyze SSC DMA data transfers.
+		This logic is as non-invasive as possible:  It samples DMA
+		registers at key points in the data transfer and then dumps all of
+		the registers at the end of the transfer.
+
+config SAMV7_SSC_REGDEBUG
+	bool "SSC Register level debug"
+	depends on DEBUG
+	default n
+	---help---
+		Output detailed register-level SSC device debug information.
+		Very invasive! Requires also DEBUG.
+
+config SAMV7_SSC_QDEBUG
+	bool "SSC Queue debug"
+	depends on DEBUG_I2S
+	default n
+	---help---
+		Enable instrumentation to debug audio buffer queue logic.
+
+config SAMV7_SSC_DUMPBUFFERS
+	bool "Dump Buffers"
+	depends on DEBUG_I2S
+	default n
+	---help---
+		Enable instrumentation to dump TX and RX buffers.
+
+endmenu # SSC Configuration
+endif # SAMV7_SSC

arch/arm/src/samv7/Make.defs

@@ -132,3 +132,7 @@ CHIP_CSRCS += sam_twihs.c
 else ifeq ($(CONFIG_SAMV7_TWIHS2),y)
 CHIP_CSRCS += sam_twihs.c
 endif
+
+ifeq ($(CONFIG_SAMV7_SSC),y)
+CHIP_CSRCS += sam_ssc.c
+endif

arch/arm/src/samv7/chip/sam_ssc.h

@@ -0,0 +1,318 @@
+/************************************************************************************
+ * arch/arm/src/samv7/chip/sam_ssc.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SSC_H
+#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SSC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/samv7/chip.h>
+
+#include "chip/sam_memorymap.h"
+
+#if SAMV7_NSSC > 0
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+ /* The maximum clock speed allowed on the TK and RK pins is the peripheral clock
+  * divided by 2.
+  */
+
+#define SAM_SSC_MAXPERCLK         (BOARD_MCK_FREQUENCY >> 1)
+
+/* SSC Register Offsets *************************************************************/
+
+#define SAM_SSC_CR_OFFSET         0x0000 /* Control Register */
+#define SAM_SSC_CMR_OFFSET        0x0004 /* Clock Mode Register */
+                                         /* 0x0008-0x000c Reserved */
+#define SAM_SSC_RCMR_OFFSET       0x0010 /* Receive Clock Mode Register */
+#define SAM_SSC_RFMR_OFFSET       0x0014 /* Receive Frame Mode Register */
+#define SAM_SSC_TCMR_OFFSET       0x0018 /* Transmit Clock Mode Register */
+#define SAM_SSC_TFMR_OFFSET       0x001c /* Transmit Frame Mode Register */
+#define SAM_SSC_RHR_OFFSET        0x0020 /* Receive Holding Register */
+#define SAM_SSC_THR_OFFSET        0x0024 /* Transmit Holding Register */
+                                         /* 0x0028-0x002c Reserved */
+#define SAM_SSC_RSHR_OFFSET       0x0030 /* Receive Sync. Holding Register */
+#define SAM_SSC_TSHR_OFFSET       0x0034 /* Transmit Sync. Holding Register */
+#define SAM_SSC_RC0R_OFFSET       0x0038 /* Receive Compare 0 Register */
+#define SAM_SSC_RC1R_OFFSET       0x003c /* Receive Compare 1 Register */
+#define SAM_SSC_SR_OFFSET         0x0040 /* Status Register */
+#define SAM_SSC_IER_OFFSET        0x0044 /* Interrupt Enable Register */
+#define SAM_SSC_IDR_OFFSET        0x0048 /* Interrupt Disable Register */
+#define SAM_SSC_IMR_OFFSET        0x004c /* Interrupt Mask Register */
+                                         /* 0x0050-0x00e0: Reserved */
+#define SAM_SSC_WPMR_OFFSET       0x00e4 /* Write Protect Mode Register */
+#define SAM_SSC_WPSR_OFFSET       0x00e8 /* Write Protect Status Register */
+                                         /* 0x00ec-0x0124 Reserved */
+
+/* SSC Register Addresses ***********************************************************/
+
+#define SAM_SSC0_CR               (SAM_SSC0_BASE+SAM_SSC_CR_OFFSET)
+#define SAM_SSC0_CMR              (SAM_SSC0_BASE+SAM_SSC_CMR_OFFSET)
+#define SAM_SSC0_RCMR             (SAM_SSC0_BASE+SAM_SSC_RCMR_OFFSET)
+#define SAM_SSC0_RFMR             (SAM_SSC0_BASE+SAM_SSC_RFMR_OFFSET)
+#define SAM_SSC0_TCMR             (SAM_SSC0_BASE+SAM_SSC_TCMR_OFFSET)
+#define SAM_SSC0_TFMR             (SAM_SSC0_BASE+SAM_SSC_TFMR_OFFSET)
+#define SAM_SSC0_RHR              (SAM_SSC0_BASE+SAM_SSC_RHR_OFFSET)
+#define SAM_SSC0_THR              (SAM_SSC0_BASE+SAM_SSC_THR_OFFSET)
+#define SAM_SSC0_RSHR             (SAM_SSC0_BASE+SAM_SSC_RSHR_OFFSET)
+#define SAM_SSC0_TSHR             (SAM_SSC0_BASE+SAM_SSC_TSHR_OFFSET)
+#define SAM_SSC0_RC0R             (SAM_SSC0_BASE+SAM_SSC_RC0R_OFFSET)
+#define SAM_SSC0_RC1R             (SAM_SSC0_BASE+SAM_SSC_RC1R_OFFSET)
+#define SAM_SSC0_SR               (SAM_SSC0_BASE+SAM_SSC_SR_OFFSET)
+#define SAM_SSC0_IER              (SAM_SSC0_BASE+SAM_SSC_IER_OFFSET)
+#define SAM_SSC0_IDR              (SAM_SSC0_BASE+SAM_SSC_IDR_OFFSET)
+#define SAM_SSC0_IMR              (SAM_SSC0_BASE+SAM_SSC_IMR_OFFSET)
+#define SAM_SSC0_WPMR             (SAM_SSC0_BASE+SAM_SSC_WPMR_OFFSET)
+#define SAM_SSC0_WPSR             (SAM_SSC0_BASE+SAM_SSC_WPSR_OFFSET)
+
+#if SAMV7_NSSC > 1
+#  define SAM_SSC1_CR             (SAM_SSC1_BASE+SAM_SSC_CR_OFFSET)
+#  define SAM_SSC1_CMR            (SAM_SSC1_BASE+SAM_SSC_CMR_OFFSET)
+#  define SAM_SSC1_RCMR           (SAM_SSC1_BASE+SAM_SSC_RCMR_OFFSET)
+#  define SAM_SSC1_RFMR           (SAM_SSC1_BASE+SAM_SSC_RFMR_OFFSET)
+#  define SAM_SSC1_TCMR           (SAM_SSC1_BASE+SAM_SSC_TCMR_OFFSET)
+#  define SAM_SSC1_TFMR           (SAM_SSC1_BASE+SAM_SSC_TFMR_OFFSET)
+#  define SAM_SSC1_RHR            (SAM_SSC1_BASE+SAM_SSC_RHR_OFFSET)
+#  define SAM_SSC1_THR            (SAM_SSC1_BASE+SAM_SSC_THR_OFFSET)
+#  define SAM_SSC1_RSHR           (SAM_SSC1_BASE+SAM_SSC_RSHR_OFFSET)
+#  define SAM_SSC1_TSHR           (SAM_SSC1_BASE+SAM_SSC_TSHR_OFFSET)
+#  define SAM_SSC1_RC0R           (SAM_SSC1_BASE+SAM_SSC_RC0R_OFFSET)
+#  define SAM_SSC1_RC1R           (SAM_SSC1_BASE+SAM_SSC_RC1R_OFFSET)
+#  define SAM_SSC1_SR             (SAM_SSC1_BASE+SAM_SSC_SR_OFFSET)
+#  define SAM_SSC1_IER            (SAM_SSC1_BASE+SAM_SSC_IER_OFFSET)
+#  define SAM_SSC1_IDR            (SAM_SSC1_BASE+SAM_SSC_IDR_OFFSET)
+#  define SAM_SSC1_IMR            (SAM_SSC1_BASE+SAM_SSC_IMR_OFFSET)
+#  define SAM_SSC1_WPMR           (SAM_SSC1_BASE+SAM_SSC_WPMR_OFFSET)
+#  define SAM_SSC1_WPSR           (SAM_SSC1_BASE+SAM_SSC_WPSR_OFFSET)
+#endif
+
+/* SSC Register Bit Definitions *****************************************************/
+
+/* Control Register */
+
+#define SSC_CR_RXEN               (1 << 0)  /* Bit 0:  Receive Enable */
+#define SSC_CR_RXDIS              (1 << 1)  /* Bit 1:  Receive Disable */
+#define SSC_CR_TXEN               (1 << 8)  /* Bit 8:  Transmit Enable */
+#define SSC_CR_TXDIS              (1 << 9)  /* Bit 9:  Transmit Disable */
+#define SSC_CR_SWRST              (1 << 15) /* Bit 15: Software Reset */
+
+/* Clock Mode Register */
+
+#define SSC_CMR_DIV_MASK          (0x00000fff) /* Bits 0-11: DIV: Clock Divider */
+
+/* Receive Clock Mode Register */
+
+#define SSC_RCMR_CKS_SHIFT        (0)       /* Bits 0-1: Receive Clock Selection */
+#define SSC_RCMR_CKS_MASK         (3 << SSC_RCMR_CKS_SHIFT)
+#  define SSC_RCMR_CKS_MCK        (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */
+#  define SSC_RCMR_CKS_TK         (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */
+#  define SSC_RCMR_CKS_RK         (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */
+#define SSC_RCMR_CKO_SHIFT        (2)       /* Bits 2-4: Receive Clock Output Mode Selection */
+#define SSC_RCMR_CKO_MASK         (7 << SSC_RCMR_CKO_SHIFT)
+#  define SSC_RCMR_CKO_NONE       (0 << SSC_RCMR_CKO_SHIFT) /* None, RK pin is an input */
+#  define SSC_RCMR_CKO_CONT       (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock, RK pin is an output */
+#  define SSC_RCMR_CKO_TRANSFER   (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock during transfers, RK pin is an output */
+#define SSC_RCMR_CKI              (1 << 5)  /* Bit 5:  Receive Clock Inversion */
+#define SSC_RCMR_CKG_SHIFT        (6)       /* Bits 6-7: Receive Clock Gating Selection */
+#define SSC_RCMR_CKG_MASK         (3 << SSC_RCMR_CKG_SHIFT)
+#  define SSC_RCMR_CKG_CONT       (0 << SSC_RCMR_CKG_SHIFT) /* None */
+#  define SSC_RCMR_CKG_ENRFLOW    (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Pin is Low */
+#  define SSC_RCMR_CKG_ENRFHIGH   (3 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Pin is High */
+#define SSC_RCMR_START_SHIFT      (8)       /* Bits 8-11: Receive Start Selection */
+#define SSC_RCMR_START_MASK       (15 << SSC_RCMR_START_SHIFT)
+#  define SSC_RCMR_START_CONT     (0 << SSC_RCMR_START_SHIFT) /* Continuous */
+#  define SSC_RCMR_START_TRANSMIT (1 << SSC_RCMR_START_SHIFT) /* Transmit start */
+#  define SSC_RCMR_START_LOW      (2 << SSC_RCMR_START_SHIFT) /* Detection of a low level on RF signal */
+#  define SSC_RCMR_START_HIGH     (3 << SSC_RCMR_START_SHIFT) /* Detection of a high level on RF signal */
+#  define SSC_RCMR_START_FALLING  (4 << SSC_RCMR_START_SHIFT) /* Detection of a falling edge on RF signal */
+#  define SSC_RCMR_START_RISING   (5 << SSC_RCMR_START_SHIFT) /* Detection of a rising edge on RF signal */
+#  define SSC_RCMR_START_LEVEL    (6 << SSC_RCMR_START_SHIFT) /* Detection of any level change on RF signal */
+#  define SSC_RCMR_START_EDGE     (7 << SSC_RCMR_START_SHIFT) /* Detection of any edge on RF signal */
+#  define SSC_RCMR_START_CMP0     (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */
+#define SSC_RCMR_STOP             (1 << 12) /* Bit 12: Receive Stop Selection */
+#define SSC_RCMR_STTDLY_SHIFT     (16)      /* Bits 16-23: Receive Start Delay */
+#define SSC_RCMR_STTDLY_MASK      (0xff << SSC_RCMR_STTDLY_SHIFT)
+#  define SSC_RCMR_STTDLY(n)      ((uint32_t)(n) << SSC_RCMR_STTDLY_SHIFT)
+#define SSC_RCMR_PERIOD_SHIFT     (24)       /* Bits 24-31: Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD_MASK      (0xff << SSC_RCMR_PERIOD_SHIFT)
+#  define SSC_RCMR_PERIOD(n)      ((uint32_t)(n) << SSC_RCMR_PERIOD_SHIFT)
+
+/* Receive Frame Mode Register */
+
+#define SSC_RFMR_DATLEN_SHIFT     (0)       /* Bits 0-4: Data Length */
+#define SSC_RFMR_DATLEN_MASK      (15 << SSC_RFMR_DATLEN_SHIFT)
+#  define SSC_RFMR_DATLEN(n)      ((uint32_t)(n) << SSC_RFMR_DATLEN_SHIFT)
+#define SSC_RFMR_LOOP             (1 << 5)  /* Bit 5:  Loop Mode */
+#define SSC_RFMR_MSBF             (1 << 7)  /* Bit 7:  Most Significant Bit First */
+#define SSC_RFMR_DATNB_SHIFT      (8)       /* Bits 8-11: Data Number per Frame */
+#define SSC_RFMR_DATNB_MASK       (15 << SSC_RFMR_DATNB_SHIFT)
+#  define SSC_RFMR_DATNB(n)       ((uint32_t)(n) << SSC_RFMR_DATNB_SHIFT)
+#define SSC_RFMR_FSLEN_SHIFT      (16)      /* Bits 16-19: Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN_MASK       (15 << SSC_RFMR_FSLEN_SHIFT)
+#  define SSC_RFMR_FSLEN(n)       ((uint32_t)(n) << SSC_RFMR_FSLEN_SHIFT)
+#define SSC_RFMR_FSOS_SHIFT       (20)      /* Bits 20-22: Receive Frame Sync Output Selection */
+#define SSC_RFMR_FSOS_MASK        (7 << SSC_RFMR_FSOS_SHIFT)
+#  define SSC_RFMR_FSOS_NONE      (0 << SSC_RFMR_FSOS_SHIFT) /* None, RF pin is an input */
+#  define SSC_RFMR_FSOS_NEGATIVE  (1 << SSC_RFMR_FSOS_SHIFT) /* Negative Pulse, RF pin is an output */
+#  define SSC_RFMR_FSOS_POSITIVE  (2 << SSC_RFMR_FSOS_SHIFT) /* Positive Pulse, RF pin is an output */
+#  define SSC_RFMR_FSOS_LOW       (3 << SSC_RFMR_FSOS_SHIFT) /* Low during transfer, RF pin is an output */
+#  define SSC_RFMR_FSOS_HIGH      (4 << SSC_RFMR_FSOS_SHIFT) /* High during transfer, RF pin is an output */
+#  define SSC_RFMR_FSOS_TOGGLING  (5 << SSC_RFMR_FSOS_SHIFT) /* Toggling each transfer, RF pin is an output */
+#define SSC_RFMR_FSEDGE           (1 << 24) /* Bit 24: Frame Sync Edge Detection */
+#  define SSC_RFMR_FSEDGE_POS     (0)       /* Bit 24: 0=Positive Edge Detection */
+#  define SSC_RFMR_FSEDGE_NEG     (1 << 24) /* Bit 24: 1=Negative Edge Detection */
+#define SSC_RFMR_FSLENEXT_SHIFT   (28)      /* Bits 28-31: FSLEN Field Extension */
+#define SSC_RFMR_FSLENEXT_MASK    (15 << SSC_RFMR_FSLENEXT_SHIFT)
+#  define SSC_RFMR_FSLENEXT(n)    ((uint32_t)(n) << SSC_RFMR_FSLENEXT_SHIFT)
+
+/* Transmit Clock Mode Register */
+
+#define SSC_TCMR_CKS_SHIFT        (0)       /* Bits 0-1: Transmit Clock Selection */
+#define SSC_TCMR_CKS_MASK         (3 << SSC_TCMR_CKS_SHIFT)
+#  define SSC_TCMR_CKS_MCK        (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */
+#  define SSC_TCMR_CKS_RK         (1 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */
+#  define SSC_TCMR_CKS_TK         (2 << SSC_TCMR_CKS_SHIFT) /* TK pin */
+#define SSC_TCMR_CKO_SHIFT        (2)       /* Bits 2-4: Transmit Clock Output Mode Selection */
+#define SSC_TCMR_CKO_MASK         (7 << SSC_TCMR_CKO_SHIFT)
+#  define SSC_TCMR_CKO_NONE       (0 << SSC_TCMR_CKO_SHIFT) /* None, TK pin is an input */
+#  define SSC_TCMR_CKO_CONT       (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock, TK pin is an output */
+#  define SSC_TCMR_CKO_TRANSFER   (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock during transfers, TK pin is an output */
+#define SSC_TCMR_CKI              (1 << 5)  /* Bit 5:  Transmit Clock Inversion */
+#define SSC_TCMR_CKG_SHIFT        (6)       /* Bits 6-7: Transmit Clock Gating Selection */
+#define SSC_TCMR_CKG_MASK         (3 << SSC_TCMR_CKG_SHIFT)
+#  define SSC_TCMR_CKG_CONT       (0 << SSC_TCMR_CKG_SHIFT) /* None */
+#  define SSC_TCMR_CKG_ENTFLOW    (1 << SSC_TCMR_CKG_SHIFT) /* Transmit Clock enabled only if TF pin is Low */
+#  define SSC_TCMR_CKG_ENTFHIGH   (2 << SSC_TCMR_CKG_SHIFT) /*Transmit Clock enabled only if TF pin is High */
+#define SSC_TCMR_START_SHIFT      (8)       /* Bits 8-11: Transmit Start Selection */
+#define SSC_TCMR_START_MASK       (15 << SSC_TCMR_START_SHIFT)
+#  define SSC_TCMR_START_CONT     (0 << SSC_TCMR_START_SHIFT) /* Continuous */
+#  define SSC_TCMR_START_RECEIVE  (1 << SSC_TCMR_START_SHIFT) /* Receive start */
+#  define SSC_TCMR_START_LOW      (2 << SSC_TCMR_START_SHIFT) /* Detection of a low level on TF signal */
+#  define SSC_TCMR_START_HIGH     (3 << SSC_TCMR_START_SHIFT) /* Detection of a high level on TF signal */
+#  define SSC_TCMR_START_FALLING  (4 << SSC_TCMR_START_SHIFT) /* Detection of a falling edge on TF signal */
+#  define SSC_TCMR_START_RISING   (5 << SSC_TCMR_START_SHIFT) /* Detection of a rising edge on TF signal */
+#  define SSC_TCMR_START_LEVEL    (6 << SSC_TCMR_START_SHIFT) /* Detection of any level change on TF signal */
+#  define SSC_TCMR_START_EDGE     (7 << SSC_TCMR_START_SHIFT) /* Detection of any edge on TF signal */
+#define SSC_TCMR_STTDLY_SHIFT     (16)       /* Bits 15-23: Transmit Start Delay */
+#define SSC_TCMR_STTDLY_MASK      (0xff << SSC_TCMR_STTDLY_SHIFT)
+#  define SSC_TCMR_STTDLY(n)      ((uint32_t)(n) << SSC_TCMR_STTDLY_SHIFT)
+#define SSC_TCMR_PERIOD_SHIFT     (24)       /* Bits 24-31: Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD_MASK      (0xff << SSC_TCMR_PERIOD_SHIFT)
+#  define SSC_TCMR_PERIOD(n)      ((uint32_t)(n) << SSC_TCMR_PERIOD_SHIFT)
+
+/* Transmit Frame Mode Register */
+
+#define SSC_TFMR_DATLEN_SHIFT     (0)       /* Bits 0-4: Data Length */
+#define SSC_TFMR_DATLEN_MASK      (31 << SSC_TFMR_DATLEN_SHIFT)
+#  define SSC_TFMR_DATLEN(n)      ((uint32_t)(n) << SSC_TFMR_DATLEN_SHIFT)
+#define SSC_TFMR_DATDEF           (1 << 5)  /* Bit 5:  Data Default Value */
+#define SSC_TFMR_MSBF             (1 << 7)  /* Bit 7:  Most Significant Bit First */
+#define SSC_TFMR_DATNB_SHIFT      (8)       /* Bits 8-11: Data Number per frame */
+#define SSC_TFMR_DATNB_MASK       (15 << SSC_TFMR_DATNB_SHIFT)
+#  define SSC_TFMR_DATNB(n)       ((uint32_t)(n) << SSC_TFMR_DATNB_SHIFT)
+#define SSC_TFMR_FSLEN_SHIFT      (16)      /* Bits 16-19: Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN_MASK       (15 << SSC_TFMR_FSLEN_SHIFT)
+#  define SSC_TFMR_FSLEN(n)       ((uint32_t)(n) << SSC_TFMR_FSLEN_SHIFT)
+#define SSC_TFMR_FSOS_SHIFT       (20)      /* Bits 20-22: Transmit Frame Sync Output Selection */
+#define SSC_TFMR_FSOS_MASK        (7 << SSC_TFMR_FSOS_SHIFT)
+#  define SSC_TFMR_FSOS_NONE      (0 << SSC_TFMR_FSOS_SHIFT) /* None, TF pin is an input */
+#  define SSC_TFMR_FSOS_NEGATIVE  (1 << SSC_TFMR_FSOS_SHIFT) /* Negative Pulse, TF pin is an output */
+#  define SSC_TFMR_FSOS_POSITIVE  (2 << SSC_TFMR_FSOS_SHIFT) /* Positive Pulse, TF pin is an output */
+#  define SSC_TFMR_FSOS_LOW       (3 << SSC_TFMR_FSOS_SHIFT) /* TF pin Driven Low during data transfer */
+#  define SSC_TFMR_FSOS_HIGH      (4 << SSC_TFMR_FSOS_SHIFT) /* TF pin Driven High during data transfer */
+#  define SSC_TFMR_FSOS_TOGGLING  (5 << SSC_TFMR_FSOS_SHIFT) /* TF pin Toggles at each start of data transfer */
+#define SSC_TFMR_FSDEN            (1 << 23) /* Bit 23: Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE           (1 << 24) /* Bit 24: Frame Sync Edge Detection */
+#  define SSC_TFMR_FSEDGE_POS     (0)       /* Bit 24: 0=Positive Edge Detection */
+#  define SSC_TFMR_FSEDGE_NEG     (1 << 24) /* Bit 24: 1=Negative Edge Detection */
+#define SSC_TFMR_FSLENEXT_SHIFT   (28)      /* Bits 28-31: FSLEN Field Extension */
+#define SSC_TFMR_FSLENEXT_MASK    (15 << SSC_TFMR_FSLENEXT_SHIFT)
+#  define SSC_TFMR_FSLENEXT(n)    ((uint32_t)(n) << SSC_TFMR_FSLENEXT_SHIFT)
+
+/* Receive Holding Register (32-bit data value) */
+/* Transmit Holding Register (32-bit data value) */
+
+/* Receive Sync. Holding Register */
+
+#define SSC_RSHR_MASK             (0x0000ffff) /* Bit 0-15: Receive Synchronization Data */
+
+/* Transmit Sync. Holding Register */
+
+#define SSC_TSHR_MASK             (0x0000ffff) /* Bit 0-15: Transmit Synchronization Data */
+
+/* Receive Compare 0 Register */
+
+#define SSC_RC0R_MASK             (0x0000ffff) /* Bit 0-15: Receive Compare Data 0 */
+
+/* Receive Compare 1 Register */
+
+#define SSC_RC1R_MASK             (0x0000ffff) /* Bit 0-15: Receive Compare Data 1 */
+
+/* Status Register , Interrupt Enable Register, Interrupt Disable Register, and
+ * Interrupt Mask Register
+ */
+
+#define SSC_INT_TXRDY             (1 << 0)  /* Bit 0:  Transmit Ready */
+#define SSC_INT_TXEMPTY           (1 << 1)  /* Bit 1:  Transmit Empty */
+#define SSC_INT_RXRDY             (1 << 4)  /* Bit 4:  Receive Ready */
+#define SSC_INT_OVRUN             (1 << 5)  /* Bit 5:  Receive Overrun */
+#define SSC_INT_CP0               (1 << 8)  /* Bit 8:  Compare 0 */
+#define SSC_INT_CP1               (1 << 9)  /* Bit 9:  Compare 1 */
+#define SSC_INT_TXSYN             (1 << 10) /* Bit 10: Transmit Sync */
+#define SSC_INT_RXSYN             (1 << 11) /* Bit 11: Receive Sync */
+#define SSC_SR_TXEN               (1 << 16) /* Bit 16: Transmit Enable (SR only) */
+#define SSC_SR_RXEN               (1 << 17) /* Bit 17: Receive Enable (SR only) */
+
+/* Write Protect Mode Register */
+
+#define SSC_WPMR_WPEN             (1 << 0)  /* Bit 0:  Write Protect Enable */
+#define SSC_WPMR_WPKEY_SHIFT      (8)       /* Bits 8-31: Write Protect KEY */
+#define SSC_WPMR_WPKEY_MASK       (0x00ffffff << SSC_WPMR_WPKEY_SHIFT)
+#  define SSC_WPMR_WPKEY          (0x00535343 << SSC_WPMR_WPKEY_SHIFT) /* "SSC" in ASCII */
+
+/* Write Protect Status Register */
+
+#define SSC_WPSR_WPVS              (1 << 0)  /* Bit 0:  Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_SHIFT      (8)       /* Bits 8-23: Write Protect Violation Source */
+#define SSC_WPSR_WPVSRC_MASK       (0xffff << SSC_WPSR_WPVSRC_SHIFT)
+
+#endif /* SAMV7_NSSC > 0 */
+#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SSC_H */

arch/arm/src/samv7/chip/samv71_memorymap.h

@@ -73,7 +73,7 @@
 /* Peripherals address region */
 
 #define SAM_HSMCI_BASE         0x40000000 /* 0x40000000-0x40003fff: High Speed Multimedia Card Interface */
-#define SAM_SSC_BASE           0x40004000 /* 0x40004000-0x40007fff: Serial Synchronous Controller */
+#define SAM_SSC0_BASE          0x40004000 /* 0x40004000-0x40007fff: Serial Synchronous Controller */
 #define SAM_SPI0_BASE          0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface 0 */
 #define SAM_TC012_BASE         0x4000c000 /* 0x4000c000-0x4000ffff: Timer Counters 0-2 */
 #  define SAM_TC0_BASE         0x4000c000 /* 0x4000c000-0x4000c03f:   Timer Counter 0 */

arch/arm/src/samv7/chip/samv71_pinmap.h

@@ -419,14 +419,14 @@
 
 /* Synchronous Serial Controller (SSC) */
 
-#define GPIO_SSC_RD          (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10)
+#define GPIO_SSC0_RD         (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10)
-#define GPIO_SSC_RF          (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN24)
+#define GPIO_SSC0_RF         (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN24)
-#define GPIO_SSC_RK          (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
+#define GPIO_SSC0_RK         (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
-#define GPIO_SSC_TD_1        (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN26)
+#define GPIO_SSC0_TD_1       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN26)
-#define GPIO_SSC_TD_2        (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN10)
+#define GPIO_SSC0_TD_2       (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN10)
-#define GPIO_SSC_TD_3        (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5)
+#define GPIO_SSC0_TD_3       (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5)
-#define GPIO_SSC_TF          (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0)
+#define GPIO_SSC0_TF         (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0)
-#define GPIO_SSC_TK          (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1)
+#define GPIO_SSC0_TK         (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1)
 
 /* Timer/Counters (TC) */
 

arch/arm/src/samv7/sam_ssc.h

@@ -0,0 +1,101 @@
+/************************************************************************************
+ * arch/arm/src/samv7/sam_ssc.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMV7_SAM_SSC_H
+#define __ARCH_ARM_SRC_SAMV7_SAM_SSC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/audio/i2s.h>
+
+#include "chip/sam_ssc.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: sam_ssc_initialize
+ *
+ * Description:
+ *   Initialize the selected I2S port.
+ *
+ * Input Parameter:
+ *   Port number (for hardware that has multiple I2S interfaces)
+ *
+ * Returned Value:
+ *   Valid I2S device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct i2s_dev_s *sam_ssc_initialize(int port);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAMV7_SAM_SSC_H */

arch/arm/src/samv7/sam_xdmac.c

@@ -174,7 +174,7 @@ static const struct sam_pidmap_s g_xdmac_rxchan[] =
   { SAM_PID_UART2,  XDMACH_UART2_RX  }, /* UART2 Receive */
   { SAM_PID_UART3,  XDMACH_UART3_RX  }, /* UART3 Receive */
   { SAM_PID_UART4,  XDMACH_UART4_RX  }, /* UART4 Receive */
-  { SAM_PID_SSC,    XDMACH_SSC_RX    }, /* SSC Receive */
+  { SAM_PID_SSC0,   XDMACH_SSC_RX    }, /* SSC Receive */
   { SAM_PID_PIOA,   XDMACH_PIOA_RX   }, /* PIOA Receive */
   { SAM_PID_AFEC0,  XDMACH_AFEC0_RX  }, /* AFEC0 Receive */
   { SAM_PID_AFEC1,  XDMACH_AFEC1_RX  }, /* AFEC1 Receive */
@@ -207,7 +207,7 @@ static const struct sam_pidmap_s g_xdmac_txchan[] =
   { SAM_PID_UART3,  XDMACH_UART3_TX  }, /* UART3 Transmit */
   { SAM_PID_UART4,  XDMACH_UART4_TX  }, /* UART4 Transmit */
   { SAM_PID_DACC,   XDMACH_DACC_TX   }, /* DACC Transmit */
-  { SAM_PID_SSC,    XDMACH_SSC_TX    }, /* SSC Transmit */
+  { SAM_PID_SSC0,   XDMACH_SSC_TX    }, /* SSC Transmit */
   { SAM_PID_AES,    XDMACH_AES_TX    }, /* AES Transmit */
   { SAM_PID_PWM1,   XDMACH_PWM1_TX   }  /* PWM01Transmit */
 };

arch/arm/src/samv7/samv71_periphclks.h

@@ -78,7 +78,7 @@
 #define sam_twihs0_enableclk()     sam_enableperiph0(SAM_PID_TWIHS0)
 #define sam_twihs1_enableclk()     sam_enableperiph0(SAM_PID_TWIHS1)
 #define sam_spi0_enableclk()       sam_enableperiph0(SAM_PID_SPI0)
-#define sam_ssc_enableclk()        sam_enableperiph0(SAM_PID_SSC)
+#define sam_ssc_enableclk()        sam_enableperiph0(SAM_PID_SSC0)
 #define sam_tc0_enableclk()        sam_enableperiph0(SAM_PID_TC0)
 #define sam_tc1_enableclk()        sam_enableperiph0(SAM_PID_TC1)
 #define sam_tc2_enableclk()        sam_enableperiph0(SAM_PID_TC2)
@@ -146,7 +146,7 @@
 #define sam_twihs0_disableclk()    sam_disableperiph0(SAM_PID_TWIHS0)
 #define sam_twihs1_disableclk()    sam_disableperiph0(SAM_PID_TWIHS1)
 #define sam_spi0_disableclk()      sam_disableperiph0(SAM_PID_SPI0)
-#define sam_ssc_disableclk()       sam_disableperiph0(SAM_PID_SSC)
+#define sam_ssc_disableclk()       sam_disableperiph0(SAM_PID_SSC0)
 #define sam_tc0_disableclk()       sam_disableperiph0(SAM_PID_TC0)
 #define sam_tc1_disableclk()       sam_disableperiph0(SAM_PID_TC1)
 #define sam_tc2_disableclk()       sam_disableperiph0(SAM_PID_TC2)

configs/samv71-xult/include/board.h

@@ -317,6 +317,14 @@
  *    There are no alternative pin selections for USART1.
  */
 
+/* SSC
+ *
+ * Alternative pin selections are available only for SSC0 TD.
+ * On the SAMV71-XULT board, PD26 supports the I2S TD function
+ */
+
+#define GPIO_SSC0_TD   GPIO_SSC0_TD_1
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/