arch/arm/src/lpc2378/Kconfig: Create Kconfig for the platform; Adjust configuration names for compatibility, configs/olimex-lpc2378/nsh: Convert to use the kconfig-frontends tools
This commit is contained in:
Gregory Nutt
parent
740a3ce1b9
commit
74414b9762
@ -37,7 +37,7 @@ config DEFAULT_MODE
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endchoice
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config CODE_BASE
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hex "Execuation Base Address"
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hex "Execution Base Address"
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default 0x00000000
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---help---
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This must match the expected address for the selected "Memory
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@ -45,7 +45,7 @@ config CODE_BASE
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EXTMEM_MODE: 0x8000:0000
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RAM_MODE: 0x4000:0000
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DEFAULT)MODE: 0x0000:0000
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DEFAULT_MODE: 0x0000:0000
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config PLL_SETUP
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bool "Configure the PLL"
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@ -4,3 +4,163 @@
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#
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comment "LPC2378 Configuration Options"
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choice
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prompt "Memory Execution Mode"
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default LPC2378_DEFAULT_MODE
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config LPC2378_EXTMEM_MODE
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bool "External Memory Mode"
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depends on EXPERIMENTAL # Not used
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---help---
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Code executes from external memory starting at address 0x8000:0000.
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config LPC2378_RAM_MODE
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bool "RAM Memory Mode"
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depends on EXPERIMENTAL # Not used
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---help---
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Code executes from on-chip RAM at address 0x4000:0000.
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config LPC2378_DEFAULT_MODE
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bool "Default Memory Mode"
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---help---
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Executes from 0x0000:0000. In non-default modes, the MEMAP register
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is set override the settings of the CPU configuration pins.
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endchoice
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config LPC2378_CODE_BASE
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hex "Execution Base Address"
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default 0x00000000
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---help---
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This must match the expected address for the selected "Memory
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Execution Address":
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LPC2378_EXTMEM_MODE: 0x8000:0000
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LPC2378_RAM_MODE: 0x4000:0000
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LPC2378_DEFAULT_MODE: 0x0000:0000
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config LPC2378_PLL_SETUP
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bool "Configure the PLL"
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default y
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config LPC2378_PLL_CLKSRC
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int "PLL clock source"
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default 1
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range 0 2
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depends on LPC2378_PLL_SETUP
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---help---
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PLL clock source
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config LPC2378_MAM_SETUP
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bool "Configure the Memory Accelerator Module (MAM)"
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default y
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config LPC2378_LPC2378_MAMCR_VALUE
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int "Memory accelerator mode"
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default 1
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range 0 2
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---help---
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Memory accelerator mode:
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OFF 0
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PART 1
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FULL 2
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config LPC2378_LPC2378_MAMTIM_VALUE
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int "Memory accelerator timing value"
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default 3
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---help---
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Memory accelerator timing value
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config LPC2378_APBDIV_SETUP
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bool "Configure the APB Divider"
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default y
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depends on EXPERIMENTAL # Not used
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config LPC2378_APBDIV_VALUE
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int "APB Divisor"
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default 1
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depends on EXPERIMENTAL # Not used
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config LPC2378_EMC_SETUP
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bool "Configure EMC"
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default n
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depends on EXPERIMENTAL # Not used
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config LPC2378_BCFG0_SETUP
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bool "Configure BCFG0"
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default n
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depends on EXPERIMENTAL # Not used
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config LPC2378_BCFG1_SETUP
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bool "Configure BCFG1"
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default n
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depends on EXPERIMENTAL # Not used
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config LPC2378_BCFG2_SETUP
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bool "Configure BCFG2"
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default n
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depends on EXPERIMENTAL # Not used
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config BCFG3_SETUP
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bool "Configure BCFG3"
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default n
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depends on EXPERIMENTAL # Not used
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config LPC2378_ADC_SETUP
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bool "Configure ADC"
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default y
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depends on EXPERIMENTAL # Not used
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menu "LPC2378 Peripheral Support"
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config LPC2378_UART0
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bool "UART0"
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default y
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select ARCH_HAVE_UART0
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config LPC2378_UART1
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bool "UART1"
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default y
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select ARCH_HAVE_UART1
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config LPC2378_UART2
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bool "UART2"
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default y
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select ARCH_HAVE_UART2
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config LPC2378_USBDEV
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bool "USB Device"
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default y
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depends on USBDEV
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endmenu
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if LPC2378_USBDEV
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menu "LPC2378 USB Device Configuration"
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config LPC2378_USBDEV_DMA
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bool "USB Device DMA Support"
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default n
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config LPC2378_USBDEV_NDMADESCRIPTORS
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int "Number of USB DMA Descriptors"
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default 8
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depends on LPC2378_USBDEV_DMA
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config LPC2378_USBDEV_EPFAST_INTERRUPT
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bool "USB Device Fast Endpoint Interrupts"
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default n
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config LPC2378_USBDEV_FRAME_INTERRUPT
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bool "USB Device Frame Interrupts"
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default n
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config LPC2378_USBDEV_REGDEBUG
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bool "USB Device Register-Level Debug Output"
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default n
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depends on DEBUG
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endmenu
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endif
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@ -6,7 +6,7 @@
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*
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* This file is part of the NuttX RTOS and based on the lpc2148 port:
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*
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* Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
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* Copyright (C) 2010, 2012, 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -59,6 +59,7 @@
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/* Print a character on the UART to show boot status. This macro will
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* modify r0, r1, r2 and r14
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*/
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#ifdef CONFIG_DEBUG
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.macro showprogress, code
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mov r0, #\code
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@ -80,7 +81,7 @@
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*
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* Description:
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* Interrrupt vector table. This must be located at the beginning
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* of the memory space (at CONFIG_CODE_BASE). The first entry in
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* of the memory space (at CONFIG_LPC2378_CODE_BASE). The first entry in
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* the vector table is the reset vector and this is the code that
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* will execute whn the processor is reset.
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*
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@ -136,6 +137,7 @@ _vector_table:
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__start:
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/* Call lowlevel init C-function */
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.extern ConfigurePLL
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ldr r0, =ConfigurePLL
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mov lr, pc
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@ -153,7 +155,6 @@ __start:
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showprogress 'A'
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/* Setup system stack (and get the BSS range) */
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adr r0, LC0
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@ -231,4 +232,3 @@ g_idle_topstack:
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.size g_idle_topstack, .-g_idle_topstack
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.end
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@ -6,7 +6,7 @@
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*
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* This file is part of the NuttX RTOS:
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -46,13 +46,13 @@
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* MEMAP register is set override the settings of the CPU configuration
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* pins.
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*
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* CONFIG_EXTMEM_MODE: Code executes from external memory starting at
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* CONFIG_LPC2378_EXTMEM_MODE: Code executes from external memory starting at
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* address 0x8000:0000.
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*
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* CONFIG_RAM_MODE: Code executes from on-chip RAM at address
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* CONFIG_LPC2378_RAM_MODE: Code executes from on-chip RAM at address
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* 0x4000:0000.
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*
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* Starupt Code must be linked to run at the correct address
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* Start-up Code must be linked to run at the correct address
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* corresponding to the selected mode.
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*/
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@ -70,10 +70,10 @@
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#include "lpc23xx_pinsel.h"
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#include "lpc23xx_scb.h"
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extern void IO_Init(void);
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void IO_Init(void);
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/***********************************************************************
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* Definitions
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* Pre-processor Definitions
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**********************************************************************/
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#if ((FOSC < 32000) || (FOSC > 50000000))
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@ -105,8 +105,8 @@ extern void IO_Init(void);
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* RTC 2
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*/
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#ifdef CONFIG_PLL_CLKSRC
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# if ( (CONFIG_PLL_CLKSRC < 0) || (CONFIG_PLL_CLKSRC > 2) )
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#ifdef CONFIG_LPC2378_PLL_CLKSRC
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# if ( (CONFIG_LPC2378_PLL_CLKSRC < 0) || (CONFIG_LPC2378_PLL_CLKSRC > 2) )
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# error "PLL clock source not valid, check configuration "
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# endif
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#else
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@ -138,13 +138,13 @@ extern void IO_Init(void);
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/* LPC2378 Rev. '-' errata MAM may not work if fully enabled */
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#ifdef CONFIG_MAM_SETUP
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# ifndef CONFIG_MAMCR_VALUE /* Can be selected from config file */
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# define CONFIG_MAMCR_VALUE (MAMCR_PART)
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#ifdef CONFIG_LPC2378_MAM_SETUP
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# ifndef CONFIG_LPC2378_MAMCR_VALUE /* Can be selected from config file */
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# define CONFIG_LPC2378_MAMCR_VALUE (MAMCR_PART)
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# endif
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# ifndef CONFIG_MAMTIM_VALUE /* Can be selected from config file */
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# define CONFIG_MAMTIM_VALUE (0x00000003)
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# ifndef CONFIG_LPC2378_MAMTIM_VALUE /* Can be selected from config file */
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# define CONFIG_LPC2378_MAMTIM_VALUE (0x00000003)
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# endif
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#endif
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@ -171,12 +171,15 @@ void ConfigurePLL(void)
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uint32_t MSel, NSel;
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/* LPC2378 Rev.'-' errata Enable the Ethernet block to enable 16k EnetRAM */
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SCB_PCONP |= PCENET;
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/* Vectors are remapped to Flash */
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SCB_MEMMAP = MEMMAP2FLASH;
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/* Enable PLL, disconnected */
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if (SCB_PLLSTAT & (1 << 25))
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{
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SCB_PLLCON = 0x01;
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@ -184,37 +187,48 @@ void ConfigurePLL(void)
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}
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/* Disable PLL, disconnected */
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SCB_PLLCON = 0;
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up_scbpllfeed();
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/* Enable main OSC */
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SCB_SCS |= 0x20;
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/* Wait until main OSC is usable */
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while (!(SCB_SCS & 0x40));
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/* select main OSC, 12MHz, as the PLL clock source */
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SCB_CLKSRCSEL = CONFIG_PLL_CLKSRC;
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SCB_CLKSRCSEL = CONFIG_LPC2378_PLL_CLKSRC;
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/* Reconfigure PLL */
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SCB_PLLCFG = PLL;
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up_scbpllfeed();
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/* Enable PLL */
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SCB_PLLCON = 0x01;
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up_scbpllfeed();
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/* Set clock divider */
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SCB_CCLKCFG = CCLK_DIV;
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#ifdef CONFIG_USBDEV
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/* usbclk = 288 MHz/6 = 48 MHz */
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SCB_USBCLKCFG = USBCLK_DIV;
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/* Turn On USB PCLK */
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SCB_PCONP |= PCUSB;
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#endif
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/* Wait for PLL to lock */
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while ((SCB_PLLSTAT & (1 << 26)) == 0);
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MSel = SCB_PLLSTAT & 0x00007FFF;
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@ -222,18 +236,22 @@ void ConfigurePLL(void)
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while ((MSel != PLL_M) && (NSel != PLL_N));
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/* Enable and connect */
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SCB_PLLCON = 0x03;
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up_scbpllfeed();
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/* Check connect bit status */
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while ((SCB_PLLSTAT & (1 << 25)) == 0);
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/* Set memory accelerater module */
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SCB_MAMCR = 0;
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SCB_MAMTIM = CONFIG_MAMTIM_VALUE;
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SCB_MAMCR = CONFIG_MAMCR_VALUE;
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SCB_MAMTIM = CONFIG_LPC2378_MAMTIM_VALUE;
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SCB_MAMCR = CONFIG_LPC2378_MAMCR_VALUE;
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/* Enable FastIO on P0:P1 */
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SCB_SCS |= 0x01;
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IO_Init();
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@ -6,7 +6,7 @@
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*
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* This file is part of the NuttX RTOS and based on the lpc2148 port:
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -49,17 +49,20 @@
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#include "lpc23xx_vic.h"
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/****************************************************************************************************
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* Definitions
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* Pre-processor Definitions
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****************************************************************************************************/
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#define scb_getreg(o) getreg32(LPC23XX_SCB_BASE + (o))
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#define scb_putreg(v,o) putreg32((v),LPC23XX_SCB_BASE + (o))
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/* Memory Accelerator Mode */
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#define MAMCR_OFF 0
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#define MAMCR_PART 1
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#define MAMCR_FULL 2
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/* Memory Mapping */
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#define MEMMAP2BBLK 0 /* Interrupt Vectors in Boot Block */
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#define MEMMAP2FLASH 1 /* Interrupt Vectors in FLASH */
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#define MEMMAP2SRAM 2 /* Interrupt Vectors in RAM */
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@ -68,58 +71,58 @@
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/* PLL Control Register Bit Settings */
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#define PLLCON_PLLE (1 << 0) /* PLL Enable */
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#define PLLCON_PLLC (1 << 1) /* PLL Connect */
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#define PLLCON_PLLE (1 << 0) /* PLL Enable */
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#define PLLCON_PLLC (1 << 1) /* PLL Connect */
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/* PLL Configuration Register Bit Settings */
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#define PLLCFG_MSEL (0x0000FFFF << 0) /* PLL Multiplier (minus 1) */
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#define PLLCFG_NSEL (0x000000FF << 16) /* PLL Divider */
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#define PLLCFG_MSEL (0x0000ffff << 0) /* PLL Multiplier (minus 1) */
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#define PLLCFG_NSEL (0x000000ff << 16) /* PLL Divider */
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/* PLL Status Register Bit Settings */
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#define PLLSTAT_MSEL (0x7FFF << 0) /* PLL Multiplier Readback */
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#define PLLSTAT_NSEL (0xFF << 16) /* PLL Divider Readback */
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#define PLLSTAT_PLLE (1 << 24) /* PLL Enable Readback */
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#define PLLSTAT_PLLC (1 << 25) /* PLL Connect Readback */
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#define PLLSTAT_PLOCK (1 << 26) /* PLL Lock Status */
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#define PLLSTAT_MSEL (0x7fff << 0) /* PLL Multiplier Readback */
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#define PLLSTAT_NSEL (0xff << 16) /* PLL Divider Readback */
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#define PLLSTAT_PLLE (1 << 24) /* PLL Enable Readback */
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#define PLLSTAT_PLLC (1 << 25) /* PLL Connect Readback */
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#define PLLSTAT_PLOCK (1 << 26) /* PLL Lock Status */
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/* PLL Feed Register values */
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#define PLLFEED1 0xaa
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#define PLLFEED2 0x55
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#define PLLFEED1 0xaa
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#define PLLFEED2 0x55
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/* Peripheral Power Control (PCONP) Register 0xE01FC0C4 */
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#define PCTIM0 (1 << 1) /* Timer/Counter 0 */
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#define PCTIM1 (1 << 2) /* Timer/Counter 1 */
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#define PCUART0 (1 << 3) /* UART0 power/clock */
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#define PCUART1 (1 << 4) /* UART1 power/clock */
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#define PCPWM1 (1 << 5) /* Unused, always 0 */
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#define PWM1 (1 << 6) /* Pulse Width Modulation 1 */
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#define PCI2C0 (1 << 7) /* I2C0 interface */
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#define PCSPI (1 << 8) /* SPI */
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#define PCRTC (1 << 9) /* Real Time Clock*/
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#define PCSSP1 (1 << 10) /* SSP1 */
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#define PCEMC (1 << 11) /* External Memory Controller */
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#define PCAD (1 << 12) /* A/D converter (ADC) Note: Clear the PDN bit in the AD0CR before
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clearing this bit, and set this bit before setting PDN */
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#define PCAN1 (1 << 13) /* CAN Controller 1 */
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#define PCAN2 (1 << 14) /* CAN Controller 2 */
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#define PCI2C1 (1 << 19) /* The I2C1 interface power/clock control bit */
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#define PCSSP0 (1 << 21) /* The SSP0 interface power/clock control bit */
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#define PCTIM2 (1 << 22) /* Timer 2 */
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#define PCTIM3 (1 << 23) /* Timer 3 */
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#define PCUART2 (1 << 24) /* UART 2 */
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#define PCUART3 (1 << 25) /* UART 3 */
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#define PCI2C2 (1 << 26) /* I2C interface 2 */
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#define PCI2S (1 << 27) /* I2S interface */
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#define PCSDC (1 << 28) /* SD card interface */
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#define PCGPDMA (1 << 29) /* GP DMA function */
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#define PCENET (1 << 30) /* Ethernet block */
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#define PCUSB (1 << 31) /* USB interface */
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#define PCTIM0 (1 << 1) /* Timer/Counter 0 */
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#define PCTIM1 (1 << 2) /* Timer/Counter 1 */
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#define PCUART0 (1 << 3) /* UART0 power/clock */
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#define PCUART1 (1 << 4) /* UART1 power/clock */
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#define PCPWM1 (1 << 5) /* Unused, always 0 */
|
||||
#define PWM1 (1 << 6) /* Pulse Width Modulation 1 */
|
||||
#define PCI2C0 (1 << 7) /* I2C0 interface */
|
||||
#define PCSPI (1 << 8) /* SPI */
|
||||
#define PCRTC (1 << 9) /* Real Time Clock*/
|
||||
#define PCSSP1 (1 << 10) /* SSP1 */
|
||||
#define PCEMC (1 << 11) /* External Memory Controller */
|
||||
#define PCAD (1 << 12) /* A/D converter (ADC) Note: Clear the PDN
|
||||
* bit in the AD0CR before clearing this bit,
|
||||
* and set this bit before setting PDN */
|
||||
#define PCAN1 (1 << 13) /* CAN Controller 1 */
|
||||
#define PCAN2 (1 << 14) /* CAN Controller 2 */
|
||||
#define PCI2C1 (1 << 19) /* The I2C1 interface power/clock control bit */
|
||||
#define PCSSP0 (1 << 21) /* The SSP0 interface power/clock control bit */
|
||||
#define PCTIM2 (1 << 22) /* Timer 2 */
|
||||
#define PCTIM3 (1 << 23) /* Timer 3 */
|
||||
#define PCUART2 (1 << 24) /* UART 2 */
|
||||
#define PCUART3 (1 << 25) /* UART 3 */
|
||||
#define PCI2C2 (1 << 26) /* I2C interface 2 */
|
||||
#define PCI2S (1 << 27) /* I2S interface */
|
||||
#define PCSDC (1 << 28) /* SD card interface */
|
||||
#define PCGPDMA (1 << 29) /* GP DMA function */
|
||||
#define PCENET (1 << 30) /* Ethernet block */
|
||||
#define PCUSB (1 << 31) /* USB interface */
|
||||
|
||||
/****************************************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
@ -136,7 +136,7 @@ static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
|
||||
|
||||
/* This describes the state of the LPC214X uart0 port. */
|
||||
|
||||
#ifdef CONFIG_UART0
|
||||
#ifdef CONFIG_LPC2378_UART0
|
||||
static struct up_dev_s g_uart0priv =
|
||||
{
|
||||
.uartbase = UART0_BASE_ADDR,
|
||||
@ -164,7 +164,7 @@ static uart_dev_t g_uart0port =
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART2
|
||||
#ifdef CONFIG_LPC2378_UART2
|
||||
|
||||
/* This describes the state of the LPC23XX uart2 port. */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user