MPFS: Use riscv_mhartid to obtain hartid

Preparation for S-mode, read mhartid via function call instead of
directly from the machine mode register
This commit is contained in:
Ville Juven 2022-02-24 09:10:34 +02:00 committed by Xiang Xiao
parent f8ffcbbf36
commit 745f00e77d
7 changed files with 43 additions and 10 deletions

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@ -26,12 +26,30 @@
#include <stdint.h>
#include <nuttx/arch.h>
#include <arch/csr.h>
#include "riscv_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: riscv_mhartid
*
* Description:
* Context aware way to query hart id
*
* Returned Value:
* Hart id
*
****************************************************************************/
uintptr_t riscv_mhartid(void)
{
return READ_CSR(mhartid);
}
/****************************************************************************
* Name: up_cpu_index
*
@ -48,10 +66,9 @@
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void)
{
int mhartid;
asm volatile ("csrr %0, mhartid": "=r" (mhartid));
return mhartid;
return (int)riscv_mhartid();
}
#endif

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@ -253,6 +253,19 @@ void riscv_cpu_boot(int cpu);
int riscv_pause_handler(int irq, void *c, void *arg);
#endif
/****************************************************************************
* Name: riscv_mhartid
*
* Description:
* Context aware way to query hart id
*
* Returned Value:
* Hart id
*
****************************************************************************/
uintptr_t riscv_mhartid(void);
#undef EXTERN
#ifdef __cplusplus
}

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@ -32,6 +32,7 @@ CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
CMN_CSRCS += riscv_mdelay.c riscv_udelay.c riscv_copyfullstate.c
CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c
CMN_CSRCS += riscv_cpuindex.c
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += riscv_backtrace.c

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@ -62,7 +62,7 @@ void up_irqinitialize(void)
/* Disable all global interrupts for current hart */
uint64_t hart_id = READ_CSR(mhartid);
uintptr_t hart_id = riscv_mhartid();
uint32_t *miebase;
if (hart_id == 0)
@ -180,7 +180,7 @@ void up_disable_irq(int irq)
/* Clear enable bit for the irq */
uint64_t hart_id = READ_CSR(mhartid);
uintptr_t hart_id = riscv_mhartid();
uintptr_t miebase;
if (hart_id == 0)
@ -234,7 +234,7 @@ void up_enable_irq(int irq)
/* Set enable bit for the irq */
uint64_t hart_id = READ_CSR(mhartid);
uintptr_t hart_id = riscv_mhartid();
uintptr_t miebase;
if (hart_id == 0)

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@ -33,6 +33,7 @@
#include <arch/board/board.h>
#include "riscv_internal.h"
#include "group/group.h"
#include "hardware/mpfs_memorymap.h"
#include "hardware/mpfs_plic.h"
@ -70,7 +71,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
/* Firstly, check if the irq is machine external interrupt */
uint64_t hart_id = READ_CSR(mhartid);
uintptr_t hart_id = riscv_mhartid();
uintptr_t claim_address;
if (hart_id == 0)

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@ -111,7 +111,7 @@ const uint64_t g_entrypoints[5] =
* Name: __mpfs_start
****************************************************************************/
void __mpfs_start(uint32_t mhartid)
void __mpfs_start(uint64_t mhartid)
{
const uint32_t *src;
uint32_t *dest;

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@ -33,6 +33,7 @@
#include <nuttx/spinlock.h>
#include "riscv_internal.h"
#include "mpfs.h"
#include "mpfs_clockconfig.h"
@ -114,7 +115,7 @@ void up_timer_initialize(void)
{
/* what is our timecmp address for this hart */
uint64_t hart_id = READ_CSR(mhartid);
uintptr_t hart_id = riscv_mhartid();
_mtime_cmp = (uint64_t *)MPFS_CLINT_MTIMECMP0 + hart_id;
/* Attach timer interrupt handler */