From 7475712d87b72ccf5bdb6b2df15dc731502b5496 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Dec 2015 12:32:32 -0600 Subject: [PATCH] ARMv7-R: Review/update cache operations --- arch/arm/src/armv7-r/cp15_cacheops.h | 20 ++++++++++++++------ arch/arm/src/armv7-r/sctlr.h | 2 +- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/armv7-r/cp15_cacheops.h b/arch/arm/src/armv7-r/cp15_cacheops.h index 3338aefda2..aa0dee9906 100644 --- a/arch/arm/src/armv7-r/cp15_cacheops.h +++ b/arch/arm/src/armv7-r/cp15_cacheops.h @@ -6,10 +6,8 @@ * * References: * - * "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1, Copyright © 2010 - * ARM. All rights reserved. ARM DDI 0434B (ID101810) * "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright © - * 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.b (ID072512) + * 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.c (ID051414) * * Portions of this file derive from Atmel sample code for the SAMA5D3 Cortex-A5 * which also has a modified BSD-style license: @@ -62,9 +60,7 @@ #define CP15_L1_LINESIZE 32 /* CP15 Registers *******************************************************************/ -/* Reference: Cortex-A5™ MPCore Paragraph 4.1.5, "Cache Operations Registers." - * - * Terms: +/* Terms: * 1) Point of coherency (PoC) * The PoC is the point at which all agents that can access memory are guaranteed * to see the same copy of a memory location @@ -92,6 +88,10 @@ * Description: Invalidate instruction cache by VA to PoU. * Register Format: VA * Instruction: MCR p15, 0, , c7, c5, 1 + * CP15 Register: CP15ISB + * Description: Instruction Synchronization Barrier operation + * NOTE: Deprecated and no longer documented + * Instruction: MCR p15, 0, , c7, c5, 4 * CP15 Register: BPIALL * Description: Invalidate entire branch predictor array. * Register Format: Should be zero (SBZ) @@ -116,6 +116,14 @@ * Description: Clean data cache line by Set/Way. * Register Format: Set/Way * Instruction: MCR p15, 0, , c7, c10, 2 + * CP15 Register: CP15DSB + * Description: Data Synchronization Barrier operation + * NOTE: Deprecated and no longer documented + * Instruction: MCR p15, 0, , c7, c10, 4 + * CP15 Register: CP15DMB + * Description: Data Memory Barrier operation + * NOTE: Deprecated and no longer documented + * Instruction: MCR p15, 0, , c7, c10, 5 * CP15 Register: DCCMVAU * Description: Clean data or unified cache line by VA to PoU. * Register Format: VA diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h index 983d64e2d3..bc942db38b 100644 --- a/arch/arm/src/armv7-r/sctlr.h +++ b/arch/arm/src/armv7-r/sctlr.h @@ -8,7 +8,7 @@ * References: * * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright - * 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.b (ID072512) + * 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.c (ID051414) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions