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arch/arm/src/s32k1xx/Kconfig: Break out some feature configurations instead of relying os MCU selections for conditional logic.

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This commit is contained in:
Gregory Nutt 2019-08-15 17:17:38 -06:00
parent b7f1c21b36
commit 74d76786de
2 changed files with 9 additions and 4 deletions
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5
arch/arm/src/s32k1xx/Kconfig
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@ -64,6 +64,7 @@ config ARCH_CHIP_S32K14X
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
select S32K1XX_HAVE_EWM select S32K1XX_HAVE_EWM
select S32K1XX_HAVE_SPLL
select S32K1XX_HAVE_HSRUN select S32K1XX_HAVE_HSRUN
# Chip Capabilities # Chip Capabilities
@ -88,6 +89,10 @@ config S32K1XX_HAVE_SAI
bool bool
default n default n
config S32K1XX_HAVE_SPLL
bool
default n
# Peripheral Selection # Peripheral Selection
menu "S32K1XX Peripheral Selection" menu "S32K1XX Peripheral Selection"

8
arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
View File

@ -200,7 +200,7 @@ struct scg_sosc_config_s
bool locked; /* true: Lock System OSC Control Register */ bool locked; /* true: Lock System OSC Control Register */
}; };
#ifdef CONFIG_ARCH_CHIP_S32K14X #ifdef CONFIG_S32K1XX_HAVE_SPLL
/* SCG SPLL Clock Configuration */ /* SCG SPLL Clock Configuration */
enum scg_spll_monitor_mode_e enum scg_spll_monitor_mode_e
@ -276,7 +276,7 @@ enum scg_system_clock_src_e
SCG_SYSTEM_CLOCK_SRC_SYS_OSC = 1, /* System OSC */ SCG_SYSTEM_CLOCK_SRC_SYS_OSC = 1, /* System OSC */
SCG_SYSTEM_CLOCK_SRC_SIRC = 2, /* Slow IRC */ SCG_SYSTEM_CLOCK_SRC_SIRC = 2, /* Slow IRC */
SCG_SYSTEM_CLOCK_SRC_FIRC = 3, /* Fast IRC */ SCG_SYSTEM_CLOCK_SRC_FIRC = 3, /* Fast IRC */
#ifdef CONFIG_ARCH_CHIP_S32K14X #ifdef CONFIG_S32K1XX_HAVE_SPLL
SCG_SYSTEM_CLOCK_SRC_SYS_PLL = 6, /* System PLL */ SCG_SYSTEM_CLOCK_SRC_SYS_PLL = 6, /* System PLL */
#endif #endif
SCG_SYSTEM_CLOCK_SRC_NONE = 255 /* MAX value */ SCG_SYSTEM_CLOCK_SRC_NONE = 255 /* MAX value */
@ -294,7 +294,7 @@ struct scg_clock_mode_config_s
{ {
struct scg_system_clock_config_s rccr; /* Run Clock Control configuration */ struct scg_system_clock_config_s rccr; /* Run Clock Control configuration */
struct scg_system_clock_config_s vccr; /* VLPR Clock Control configuration */ struct scg_system_clock_config_s vccr; /* VLPR Clock Control configuration */
#ifdef CONFIG_ARCH_CHIP_S32K14X #ifdef CONFIG_S32K1XX_HAVE_HSRUN
struct scg_system_clock_config_s hccr; /* HSRUN Clock Control configuration */ struct scg_system_clock_config_s hccr; /* HSRUN Clock Control configuration */
#endif #endif
enum scg_system_clock_src_e altclk; /* Alternate clock used during initialization */ enum scg_system_clock_src_e altclk; /* Alternate clock used during initialization */
@ -308,7 +308,7 @@ struct scg_config_s
struct scg_sirc_config_s sirc; /* Slow internal reference clock configuration */ struct scg_sirc_config_s sirc; /* Slow internal reference clock configuration */
struct scg_firc_config_s firc; /* Fast internal reference clock configuration */ struct scg_firc_config_s firc; /* Fast internal reference clock configuration */
struct scg_sosc_config_s sosc; /* System oscillator configuration */ struct scg_sosc_config_s sosc; /* System oscillator configuration */
#ifdef CONFIG_ARCH_CHIP_S32K14X #ifdef CONFIG_S32K1XX_HAVE_SPLL
struct scg_spll_config_s spll; /* System Phase locked loop configuration */ struct scg_spll_config_s spll; /* System Phase locked loop configuration */
#endif #endif
struct scg_rtc_config_s rtc; /* Real Time Clock configuration */ struct scg_rtc_config_s rtc; /* Real Time Clock configuration */