Merged in slorquet/nuttx/32l4_qepsc (pull request #169)
Change the way to configure quadrature encoder prescalers.
This commit is contained in:
Gregory Nutt
commit
750a25a086
@ -2807,11 +2807,12 @@ config STM32L4_TIM1_QE
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if STM32L4_TIM1_QE
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config STM32L4_TIM1_QECLKOUT
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int "TIM1 output clock"
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default 2800000
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config STM32L4_TIM1_QEPSC
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int "TIM1 pulse prescaler"
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default 1
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---help---
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The output clock of TIM1.
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This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
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Replaces the obscure "output clock of TIM1." (CONFIG_TIM1_QECLKOUT).
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endif
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@ -2824,11 +2825,12 @@ config STM32L4_TIM2_QE
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if STM32L4_TIM2_QE
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config STM32L4_TIM2_QECLKOUT
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int "TIM2 output clock"
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default 2800000
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config STM32L4_TIM2_QEPSC
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int "TIM2 pulse prescaler"
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default 1
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---help---
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The output clock of TIM2.
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This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
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Replaces the obscure "output clock of TIM2." (CONFIG_TIM2_QECLKOUT).
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endif
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@ -2841,11 +2843,12 @@ config STM32L4_TIM3_QE
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if STM32L4_TIM3_QE
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config STM32L4_TIM3_QECLKOUT
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int "TIM3 output clock"
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default 2800000
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config STM32L4_TIM3_QEPSC
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int "TIM3 pulse prescaler"
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default 1
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---help---
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The output clock of TIM3.
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This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
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Replaces the obscure "output clock of TIM3." (CONFIG_TIM3_QECLKOUT).
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endif
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@ -2858,11 +2861,12 @@ config STM32L4_TIM4_QE
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if STM32L4_TIM4_QE
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config STM32L4_TIM4_QECLKOUT
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int "TIM4 output clock"
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default 2800000
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config STM32L4_TIM4_QEPSC
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int "TIM4 pulse prescaler"
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default 1
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---help---
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The output clock of TIM4.
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This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
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Replaces the obscure "output clock of TIM4." (CONFIG_TIM4_QECLKOUT).
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endif
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@ -2875,11 +2879,12 @@ config STM32L4_TIM5_QE
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if STM32L4_TIM5_QE
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config STM32L4_TIM5_QECLKOUT
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int "TIM5 output clock"
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default 2800000
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config STM32L4_TIM5_QEPSC
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int "TIM5 pulse prescaler"
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default 1
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---help---
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The output clock of TIM5.
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This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
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Replaces the obscure "output clock of TIM5." (CONFIG_TIM5_QECLKOUT).
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endif
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@ -2892,11 +2897,12 @@ config STM32L4_TIM8_QE
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if STM32L4_TIM8_QE
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config STM32L4_TIM8_QECLKOUT
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int "TIM8 output clock"
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default 2800000
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config STM32L4_TIM8_QEPSC
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int "TIM8 pulse prescaler"
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default 1
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---help---
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The output clock of TIM8.
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This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
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Replaces the obscure "output clock of TIM8." (CONFIG_TIM8_QECLKOUT).
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endif
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@ -66,31 +66,6 @@
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The CLKOUT value should not exceed the CLKIN value */
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#if defined(CONFIG_STM32L4_TIM1_QE) && CONFIG_STM32L4_TIM1_QECLKOUT > STM32L4_APB2_TIM1_CLKIN
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# warning "CONFIG_STM32L4_TIM1_QECLKOUT exceeds STM32L4_APB2_TIM1_CLKIN"
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#endif
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#if defined(CONFIG_STM32L4_TIM2_QE) && CONFIG_STM32L4_TIM2_QECLKOUT > STM32L4_APB1_TIM2_CLKIN
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# warning "CONFIG_STM32L4_TIM2_QECLKOUT exceeds STM32L4_APB2_TIM2_CLKIN"
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#endif
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#if defined(CONFIG_STM32L4_TIM3_QE) && CONFIG_STM32L4_TIM3_QECLKOUT > STM32L4_APB1_TIM3_CLKIN
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# warning "CONFIG_STM32L4_TIM3_QECLKOUT exceeds STM32L4_APB2_TIM3_CLKIN"
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#endif
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#if defined(CONFIG_STM32L4_TIM4_QE) && CONFIG_STM32L4_TIM4_QECLKOUT > STM32L4_APB1_TIM4_CLKIN
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# warning "CONFIG_STM32L4_TIM4_QECLKOUT exceeds STM32L4_APB2_TIM4_CLKIN"
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#endif
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#if defined(CONFIG_STM32L4_TIM5_QE) && CONFIG_STM32L4_TIM5_QECLKOUT > STM32L4_APB1_TIM5_CLKIN
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# warning "CONFIG_STM32L4_TIM5_QECLKOUT exceeds STM32L4_APB2_TIM5_CLKIN"
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#endif
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#if defined(CONFIG_STM32L4_TIM8_QE) && CONFIG_STM32L4_TIM8_QECLKOUT > STM32L4_APB2_TIM8_CLKIN
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# warning "CONFIG_STM32L4_TIM8_QECLKOUT exceeds STM32L4_APB2_TIM8_CLKIN"
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#endif
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/* Timers ***************************************************************************/
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@ -223,7 +198,7 @@ struct stm32l4_qeconfig_s
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uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */
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uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */
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uint32_t base; /* Register base address */
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uint32_t psc; /* Timer input clock prescaler */
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uint32_t psc; /* Encoder pulses prescaler */
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xcpt_t handler; /* Interrupt handler for this IRQ */
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};
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@ -323,7 +298,7 @@ static const struct stm32l4_qeconfig_s g_tim1config =
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.width = TIM1_BITWIDTH,
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#endif
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.base = STM32L4_TIM1_BASE,
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.psc = (STM32L4_APB2_TIM1_CLKIN / CONFIG_STM32L4_TIM1_QECLKOUT) - 1,
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.psc = CONFIG_STM32L4_TIM1_QEPSC,
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.ti1cfg = GPIO_TIM1_CH1IN,
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.ti2cfg = GPIO_TIM1_CH2IN,
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#if TIM1_BITWIDTH == 16
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@ -349,7 +324,7 @@ static const struct stm32l4_qeconfig_s g_tim2config =
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.width = TIM2_BITWIDTH,
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#endif
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.base = STM32L4_TIM2_BASE,
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.psc = (STM32L4_APB1_TIM2_CLKIN / CONFIG_STM32L4_TIM2_QECLKOUT) - 1,
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.psc = CONFIG_STM32L4_TIM2_QEPSC,
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.ti1cfg = GPIO_TIM2_CH1IN,
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.ti2cfg = GPIO_TIM2_CH2IN,
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#if TIM2_BITWIDTH == 16
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@ -375,7 +350,7 @@ static const struct stm32l4_qeconfig_s g_tim3config =
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.width = TIM3_BITWIDTH,
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#endif
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.base = STM32L4_TIM3_BASE,
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.psc = (STM32L4_APB1_TIM3_CLKIN / CONFIG_STM32L4_TIM3_QECLKOUT) - 1,
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.psc = CONFIG_STM32L4_TIM3_QEPSC,
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.ti1cfg = GPIO_TIM3_CH1IN,
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.ti2cfg = GPIO_TIM3_CH2IN,
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#if TIM3_BITWIDTH == 16
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@ -401,7 +376,7 @@ static const struct stm32l4_qeconfig_s g_tim4config =
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.width = TIM4_BITWIDTH,
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#endif
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.base = STM32L4_TIM4_BASE,
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.psc = (STM32L4_APB1_TIM4_CLKIN / CONFIG_STM32L4_TIM4_QECLKOUT) - 1,
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.psc = CONFIG_STM32L4_TIM4_QEPSC,
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.ti1cfg = GPIO_TIM4_CH1IN,
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.ti2cfg = GPIO_TIM4_CH2IN,
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#if TIM4_BITWIDTH == 16
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@ -427,7 +402,7 @@ static const struct stm32l4_qeconfig_s g_tim5config =
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.width = TIM5_BITWIDTH,
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#endif
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.base = STM32L4_TIM5_BASE,
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.psc = (STM32L4_APB1_TIM5_CLKIN / CONFIG_STM32L4_TIM5_QECLKOUT) - 1,
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.psc = CONFIG_STM32L4_TI55_QEPSC,
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.ti1cfg = GPIO_TIM5_CH1IN,
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.ti2cfg = GPIO_TIM5_CH2IN,
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#if TIM5_BITWIDTH == 16
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@ -453,7 +428,7 @@ static const struct stm32l4_qeconfig_s g_tim8config =
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.width = TIM8_BITWIDTH,
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#endif
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.base = STM32L4_TIM8_BASE,
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.psc = (STM32L4_APB2_TIM8_CLKIN / CONFIG_STM32L4_TIM8_QECLKOUT) - 1,
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.psc = CONFIG_STM32L4_TIM8_QEPSC,
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.ti1cfg = GPIO_TIM8_CH1IN,
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.ti2cfg = GPIO_TIM8_CH2IN,
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#if TIM8_BITWIDTH == 16
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@ -804,10 +779,23 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower)
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stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff);
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#endif
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/* Set the timer prescaler value. The clock input value (CLKIN) is based on the
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* peripheral clock (PCLK) and a multiplier. These CLKIN values are provided in
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* the board.h file. The prescaler value is then that CLKIN value divided by the
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* configured CLKOUT value (minus one)
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/* Set the timer prescaler value.
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*
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* Previously, and still in the stm32fx driver, the clock input value (CLKIN)
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* was based on the peripheral clock (PCLK) and a multiplier.
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* These CLKIN values are provided in the board.h file.
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* The prescaler value is then that CLKIN value divided by the configured
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* CLKOUT value (minus one).
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*
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* It was determined that this configration makes no sense for a qencoder.
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* If we are doing precise shaft positioning, each qe pulse is important.
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* So the STM32L4 has direct config control on the pulse count prescaler,
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* instead of deriving this value from an obscure "output"setting AND the
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* timer input clock. This input clock just limits the incoming pulse rate,
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* which should be lower than the peripheral clock due to resynchronization,
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* but it is the responsibility of the system designer to decide the
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* correct prescaler value, because it has a direct influence on the
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* encoder resolution.
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*/
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stm32l4_putreg16(priv, STM32L4_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc);
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@ -1184,6 +1172,8 @@ static int stm32l4_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned lon
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{
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/* No ioctl commands supported */
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/* TODO add an IOCTL to control the encoder pulse count prescaler */
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return -ENOTTY;
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}
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