diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index b439bc6048..2c5d208cb9 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -5287,53 +5287,6 @@ config STM32L4_ADC3_DMA_CFG ---help--- 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode -config STM32L4_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32L4_ADC1 && STM32L4_DFSDM1 && (STM32L4_STM32L496XX || STM32L4_STM32L4XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32L4_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32L4_ADC2 && STM32L4_DFSDM1 && STM32L4_STM32L496XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32L4_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32L4_ADC3 && STM32L4_DFSDM1 && STM32L4_STM32L496XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -menu "STM32L4 ADCx triggering Configuration" - -config STM32L4_ADC1_TIMTRIG - int "ADC1 regular channel trigger" - default 0 - range 0 4 - depends on STM32L4_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L4_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32L4_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L4_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32L4_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - config STM32L4_ADC1_INJ_CHAN int "ADC1 configured injected channels" depends on STM32L4_ADC1 @@ -5358,39 +5311,188 @@ config STM32L4_ADC3_INJ_CHAN ---help--- Number of configured ADC3 injected channels. +config STM32L4_ADC1_OUTPUT_DFSDM + bool "ADC1 output to DFSDM" + depends on STM32L4_ADC1 && STM32L4_DFSDM1 && (STM32L4_STM32L496XX || STM32L4_STM32L4XR) + default n + ---help--- + Route ADC1 output directly to DFSDM parallel inputs. + +config STM32L4_ADC2_OUTPUT_DFSDM + bool "ADC2 output to DFSDM" + depends on STM32L4_ADC2 && STM32L4_DFSDM1 && STM32L4_STM32L496XX + default n + ---help--- + Route ADC2 output directly to DFSDM parallel inputs. + +config STM32L4_ADC3_OUTPUT_DFSDM + bool "ADC3 output to DFSDM" + depends on STM32L4_ADC3 && STM32L4_DFSDM1 && STM32L4_STM32L496XX + default n + ---help--- + Route ADC3 output directly to DFSDM parallel inputs. + +menu "STM32L4 ADCx triggering Configuration" + +config STM32L4_ADC1_EXTTRIG + int "ADC1 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32L4_ADC1 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32L4_ADC1_EXTTRIG > 0 + +config STM32L4_ADC1_EXTSEL + int "ADC1 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32L4_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for mor information. + +endif + +config STM32L4_ADC2_EXTTRIG + int "ADC2 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32L4_ADC2 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32L4_ADC2_EXTTRIG > 0 + +config STM32L4_ADC2_EXTSEL + int "ADC2 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32L4_ADC2 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for mor information. + +endif + +config STM32L4_ADC3_EXTTRIG + int "ADC3 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32L4_ADC3 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32L4_ADC3_EXTTRIG > 0 + +config STM32L4_ADC3_EXTSEL + int "ADC3 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32L4_ADC3 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for mor information. + +endif + if STM32L4_ADC1_INJ_CHAN > 0 -config STM32L4_ADC1_JTIMTRIG - int "ADC1 external trigger for injected channels" +config STM32L4_ADC1_JEXTTRIG + int "ADC1 External Trigger Enable and Polarity Selection for injected channels" default 0 - range 0 5 - depends on STM32L4_HAVE_ADC1_TIMER + range 0 4 + depends on STM32L4_ADC1 ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32L4_ADC1_JEXTTRIG > 0 + +config STM32L4_ADC1_JEXTSEL + int "ADC1 External Trigger Selection for injected group" + default 0 + range 0 15 + depends on STM32L4_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif endif if STM32L4_ADC2_INJ_CHAN > 0 -config STM32L4_ADC2_JTIMTRIG - int "ADC2 external trigger for injected channels" +config STM32L4_ADC2_JEXTTRIG + int "ADC2 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32L4_ADC2 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32L4_ADC2_JEXTTRIG > 0 + +config STM32L4_ADC2_JEXTSEL + int "ADC2 External Trigger Selection for injected group" default 0 range 0 5 - depends on STM32L4_HAVE_ADC2_TIMER + depends on STM32L4_ADC2 ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + Select the external event used to trigger the start of conversion of an + injected group + +endif endif if STM32L4_ADC3_INJ_CHAN > 0 -config STM32L4_ADC3_JTIMTRIG - int "ADC3 external trigger for injected channels" +config STM32L4_ADC3_JEXTTRIG + int "ADC3 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32L4_ADC3 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32L4_ADC3_JEXTTRIG > 0 + +config STM32L4_ADC3_JEXTSEL + int "ADC3 External Trigger Selection for injected group" default 0 range 0 5 - depends on STM32L4_HAVE_ADC3_TIMER + depends on STM32L4_ADC3 ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + Select the external event used to trigger the start of conversion of an + injected group + +endif endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h index f136fd465b..bb6803da71 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h @@ -245,6 +245,7 @@ # endif #define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ #define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT) +# define ADC_CFGR_EXTEN(pol) ((pol) << ADC_CFGR_EXTEN_SHIFT) /* Trigger polarity = 0..3 */ # define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */ # define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */ # define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */ @@ -463,6 +464,8 @@ # define ADC_JEXTSEL_T15TRGO ADC_JSQR_JEXTSEL(15) /* 1111 TIM15_TRGO */ #define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */ #define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT) +# define ADC_JSQR_JEXTEN(pol) ((pol) << ADC_JSQR_JEXTEN_SHIFT) + /* Trigger polarity = 0..3 */ # define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ # define ADC_JSQR_JEXTEN_RISING (1 << ADC_JSQR_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ # define ADC_JSQR_JEXTEN_FALLING (2 << ADC_JSQR_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index 7d4a4a3ce9..eb165c5dc6 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -1690,7 +1690,7 @@ static int adc_jextsel_set(struct stm32_dev_s *priv, uint32_t jextcfg) setbits = (jexten | jextsel); clrbits = (ADC_JSQR_JEXTEN_MASK | ADC_JSQR_JEXTSEL_MASK); - ainfo("Initializing jextsel = 0x%08x\n", jextsel); + ainfo("Initializing jextsel = 0x%08" PRIx32 "\n", jextsel); /* Write register */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index b1e8a33b74..ec8df411e5 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -216,9 +216,9 @@ # ifndef CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY # error "CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32L4_ADC1_TIMTRIG -# error "CONFIG_STM32L4_ADC1_TIMTRIG not defined" -# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" +# if ((CONFIG_STM32L4_ADC1_EXTTRIG == 0) && \ + (CONFIG_STM32L4_ADC1_JEXTTRIG == 0)) +# error "ADC1 External trigger must be enabled" # endif #endif @@ -265,9 +265,9 @@ # ifndef CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY # error "CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32L4_ADC2_TIMTRIG -# error "CONFIG_STM32L4_ADC2_TIMTRIG not defined" -# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" +# if ((CONFIG_STM32L4_ADC2_EXTTRIG == 0) && \ + (CONFIG_STM32L4_ADC2_JEXTTRIG == 0)) +# error "ADC2 External trigger must be enabled" # endif #endif @@ -314,9 +314,9 @@ # ifndef CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY # error "CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32L4_ADC3_TIMTRIG -# error "CONFIG_STM32L4_ADC3_TIMTRIG not defined" -# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" +# if ((CONFIG_STM32L4_ADC3_EXTTRIG == 0) && \ + (CONFIG_STM32L4_ADC3_JEXTTRIG == 0)) +# error "ADC3 External trigger must be enabled" # endif #endif @@ -327,741 +327,96 @@ # undef ADC_HAVE_TIMER #endif -/* NOTE: The following assumes that all possible combinations of timers and - * values are support EXTSEL. That is not so and it varies from one STM32 - * to another. But this (wrong) assumptions keeps the logic as simple as - * possible. If unsupported combination is used, an error will show up - * later during compilation although it may be difficult to track it back - * to this simplification. - */ - -#define ADC1_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1 -#define ADC1_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2 -#define ADC1_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3 -#define ADC1_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4 -#define ADC1_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO -#define ADC1_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2 -#define ADC2_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1 -#define ADC2_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2 -#define ADC2_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3 -#define ADC2_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4 -#define ADC2_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO -#define ADC2_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2 -#define ADC3_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1 -#define ADC3_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2 -#define ADC3_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3 -#define ADC3_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4 -#define ADC3_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO -#define ADC3_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2 - -#define ADC1_EXTSEL_T2CC1 ADC_CFGR_EXTSEL_T2CC1 -#define ADC1_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2 -#define ADC1_EXTSEL_T2CC3 ADC_CFGR_EXTSEL_T2CC3 -#define ADC1_EXTSEL_T2CC4 ADC_CFGR_EXTSEL_T2CC4 -#define ADC1_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO -#define ADC2_EXTSEL_T2CC1 ADC_CFGR_EXTSEL_T2CC1 -#define ADC2_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2 -#define ADC2_EXTSEL_T2CC3 ADC_CFGR_EXTSEL_T2CC3 -#define ADC2_EXTSEL_T2CC4 ADC_CFGR_EXTSEL_T2CC4 -#define ADC2_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO -#define ADC3_EXTSEL_T2CC1 ADC_CFGR_EXTSEL_T2CC1 -#define ADC3_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2 -#define ADC3_EXTSEL_T2CC3 ADC_CFGR_EXTSEL_T2CC3 -#define ADC3_EXTSEL_T2CC4 ADC_CFGR_EXTSEL_T2CC4 -#define ADC3_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO - -#define ADC1_EXTSEL_T3CC1 ADC_CFGR_EXTSEL_T3CC1 -#define ADC1_EXTSEL_T3CC2 ADC_CFGR_EXTSEL_T3CC2 -#define ADC1_EXTSEL_T3CC3 ADC_CFGR_EXTSEL_T3CC3 -#define ADC1_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4 -#define ADC1_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO -#define ADC2_EXTSEL_T3CC1 ADC_CFGR_EXTSEL_T3CC1 -#define ADC2_EXTSEL_T3CC2 ADC_CFGR_EXTSEL_T3CC2 -#define ADC2_EXTSEL_T3CC3 ADC_CFGR_EXTSEL_T3CC3 -#define ADC2_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4 -#define ADC2_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO -#define ADC3_EXTSEL_T3CC1 ADC_CFGR_EXTSEL_T3CC1 -#define ADC3_EXTSEL_T3CC2 ADC_CFGR_EXTSEL_T3CC2 -#define ADC3_EXTSEL_T3CC3 ADC_CFGR_EXTSEL_T3CC3 -#define ADC3_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4 -#define ADC3_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO - -#define ADC1_EXTSEL_T4CC1 ADC_CFGR_EXTSEL_T4CC1 -#define ADC1_EXTSEL_T4CC2 ADC_CFGR_EXTSEL_T4CC2 -#define ADC1_EXTSEL_T4CC3 ADC_CFGR_EXTSEL_T4CC3 -#define ADC1_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4 -#define ADC1_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO -#define ADC2_EXTSEL_T4CC1 ADC_CFGR_EXTSEL_T4CC1 -#define ADC2_EXTSEL_T4CC2 ADC_CFGR_EXTSEL_T4CC2 -#define ADC2_EXTSEL_T4CC3 ADC_CFGR_EXTSEL_T4CC3 -#define ADC2_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4 -#define ADC2_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO -#define ADC3_EXTSEL_T4CC1 ADC_CFGR_EXTSEL_T4CC1 -#define ADC3_EXTSEL_T4CC2 ADC_CFGR_EXTSEL_T4CC2 -#define ADC3_EXTSEL_T4CC3 ADC_CFGR_EXTSEL_T4CC3 -#define ADC3_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4 -#define ADC3_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO - -#define ADC1_EXTSEL_T6CC1 ADC_CFGR_EXTSEL_T6CC1 -#define ADC1_EXTSEL_T6CC2 ADC_CFGR_EXTSEL_T6CC2 -#define ADC1_EXTSEL_T6CC3 ADC_CFGR_EXTSEL_T6CC3 -#define ADC1_EXTSEL_T6CC4 ADC_CFGR_EXTSEL_T6CC4 -#define ADC1_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO -#define ADC2_EXTSEL_T6CC1 ADC_CFGR_EXTSEL_T6CC1 -#define ADC2_EXTSEL_T6CC2 ADC_CFGR_EXTSEL_T6CC2 -#define ADC2_EXTSEL_T6CC3 ADC_CFGR_EXTSEL_T6CC3 -#define ADC2_EXTSEL_T6CC4 ADC_CFGR_EXTSEL_T6CC4 -#define ADC2_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO -#define ADC3_EXTSEL_T6CC1 ADC_CFGR_EXTSEL_T6CC1 -#define ADC3_EXTSEL_T6CC2 ADC_CFGR_EXTSEL_T6CC2 -#define ADC3_EXTSEL_T6CC3 ADC_CFGR_EXTSEL_T6CC3 -#define ADC3_EXTSEL_T6CC4 ADC_CFGR_EXTSEL_T6CC4 -#define ADC3_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO - -#define ADC1_EXTSEL_T8CC1 ADC_CFGR_EXTSEL_T8CC1 -#define ADC1_EXTSEL_T8CC2 ADC_CFGR_EXTSEL_T8CC2 -#define ADC1_EXTSEL_T8CC3 ADC_CFGR_EXTSEL_T8CC3 -#define ADC1_EXTSEL_T8CC4 ADC_CFGR_EXTSEL_T8CC4 -#define ADC1_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO -#define ADC1_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2 -#define ADC2_EXTSEL_T8CC1 ADC_CFGR_EXTSEL_T8CC1 -#define ADC2_EXTSEL_T8CC2 ADC_CFGR_EXTSEL_T8CC2 -#define ADC2_EXTSEL_T8CC3 ADC_CFGR_EXTSEL_T8CC3 -#define ADC2_EXTSEL_T8CC4 ADC_CFGR_EXTSEL_T8CC4 -#define ADC2_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO -#define ADC2_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2 -#define ADC3_EXTSEL_T8CC1 ADC_CFGR_EXTSEL_T8CC1 -#define ADC3_EXTSEL_T8CC2 ADC_CFGR_EXTSEL_T8CC2 -#define ADC3_EXTSEL_T8CC3 ADC_CFGR_EXTSEL_T8CC3 -#define ADC3_EXTSEL_T8CC4 ADC_CFGR_EXTSEL_T8CC4 -#define ADC3_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO -#define ADC3_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2 - -#define ADC1_EXTSEL_T15CC1 ADC_CFGR_EXTSEL_T15CC1 -#define ADC1_EXTSEL_T15CC2 ADC_CFGR_EXTSEL_T15CC2 -#define ADC1_EXTSEL_T15CC3 ADC_CFGR_EXTSEL_T15CC3 -#define ADC1_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4 -#define ADC1_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO -#define ADC2_EXTSEL_T15CC1 ADC_CFGR_EXTSEL_T15CC1 -#define ADC2_EXTSEL_T15CC2 ADC_CFGR_EXTSEL_T15CC2 -#define ADC2_EXTSEL_T15CC3 ADC_CFGR_EXTSEL_T15CC3 -#define ADC2_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4 -#define ADC2_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO -#define ADC3_EXTSEL_T15CC1 ADC_CFGR_EXTSEL_T15CC1 -#define ADC3_EXTSEL_T15CC2 ADC_CFGR_EXTSEL_T15CC2 -#define ADC3_EXTSEL_T15CC3 ADC_CFGR_EXTSEL_T15CC3 -#define ADC3_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4 -#define ADC3_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO - /* EXTSEL configuration *****************************************************/ -/* ADCx_EXTSEL_VALUE can be set by this driver or by board specific logic in - * board.h file. +/* If external trigger is enabled, (CONFIG_STM32L4_ADC1_EXTTRIG > 0), + * ADCx_EXTSEL_VALUE is set based on trigger polarity and event number. No + * effort is made to check if the configuration is valid. */ -#ifndef ADC_EXTREG_EXTEN_DEFAULT -# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR_EXTEN_RISING -#endif +#ifdef CONFIG_STM32L4_ADC1_EXTTRIG +# if CONFIG_STM32L4_ADC1_EXTTRIG > 0 +# define ADC1_EXTCFG_VALUE \ + ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC1_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL) +# endif +#endif /* CONFIG_STM32L4_ADC1_EXTTRIG */ -#if defined(CONFIG_STM32L4_TIM1_ADC1) -# if CONFIG_STM32L4_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 5 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM2_ADC1) -# if CONFIG_STM32L4_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM3_ADC1) -# if CONFIG_STM32L4_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM4_ADC1) -# if CONFIG_STM32L4_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM6_ADC1) -# if CONFIG_STM32L4_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM8_ADC1) -# if CONFIG_STM32L4_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 5 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM15_ADC1) -# if CONFIG_STM32L4_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4 -# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#endif - -#if defined(CONFIG_STM32L4_TIM1_ADC2) -# if CONFIG_STM32L4_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 5 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM2_ADC2) -# if CONFIG_STM32L4_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM3_ADC2) -# if CONFIG_STM32L4_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM4_ADC2) -# if CONFIG_STM32L4_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM6_ADC2) -# if CONFIG_STM32L4_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM8_ADC2) -# if CONFIG_STM32L4_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 5 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM15_ADC2) -# if CONFIG_STM32L4_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4 -# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#endif - -#if defined(CONFIG_STM32L4_TIM1_ADC3) -# if CONFIG_STM32L4_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 5 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM2_ADC3) -# if CONFIG_STM32L4_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM3_ADC3) -# if CONFIG_STM32L4_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM4_ADC3) -# if CONFIG_STM32L4_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM6_ADC3) -# if CONFIG_STM32L4_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM8_ADC3) -# if CONFIG_STM32L4_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 5 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32L4_TIM15_ADC3) -# if CONFIG_STM32L4_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4 -# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#endif - -#ifdef ADC1_EXTSEL_VALUE +#ifdef ADC1_EXTCFG_VALUE # define ADC1_HAVE_EXTCFG 1 -# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) #else # undef ADC1_HAVE_EXTCFG #endif -#ifdef ADC2_EXTSEL_VALUE + +#ifdef CONFIG_STM32L4_ADC2_EXTTRIG +# if CONFIG_STM32L4_ADC2_EXTTRIG > 0 +# define ADC2_EXTCFG_VALUE \ + ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC2_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL) +# endif +#endif /* CONFIG_STM32L4_ADC2_EXTTRIG */ + +#ifdef ADC2_EXTCFG_VALUE # define ADC2_HAVE_EXTCFG 1 -# define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) #else # undef ADC2_HAVE_EXTCFG #endif -#ifdef ADC3_EXTSEL_VALUE + +#ifdef CONFIG_STM32L4_ADC3_EXTTRIG +# if CONFIG_STM32L4_ADC3_EXTTRIG > 0 +# define ADC3_EXTCFG_VALUE \ + ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC3_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL) +# endif +#endif /* CONFIG_STM32L4_ADC3_EXTTRIG */ + +#ifdef ADC3_EXTCFG_VALUE # define ADC3_HAVE_EXTCFG 1 -# define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) #else # undef ADC3_HAVE_EXTCFG #endif #if defined(ADC1_HAVE_EXTCFG) || defined(ADC2_HAVE_EXTCFG) || \ - defined(ADC3_HAVE_EXTCFG) || defined(ADC3_HAVE_EXTCFG) + defined(ADC3_HAVE_EXTCFG) # define ADC_HAVE_EXTCFG #endif /* JEXTSEL configuration ****************************************************/ -#ifndef ADC_JEXTREG_JEXTEN_DEFAULT -# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_JSQR_JEXTEN_RISING -#endif - -#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM1) -# if CONFIG_STM32L4_ADC1_JTIMTRIG == 3 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T1CC4 -# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 4 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO -# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 5 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" +#ifdef CONFIG_STM32L4_ADC1_JEXTTRIG +# if CONFIG_STM32L4_ADC1_JEXTTRIG > 0 +# define ADC1_JEXTCFG_VALUE \ + ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC1_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL) # endif -#endif +#endif /* CONFIG_STM32L4_ADC1_JEXTTRIG */ -#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM2) -# if CONFIG_STM32L4_ADC1_JTIMTRIG == 0 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T2CC1 -# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 4 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T2TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#endif - -#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM3) -# if CONFIG_STM32L4_ADC1_JTIMTRIG == 0 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T3CC1 -# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 2 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T3CC3 -# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 3 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T3CC4 -# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 4 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T3TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#endif - -#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM4) -# if CONFIG_STM32L4_ADC1_JTIMTRIG == 4 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T4TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#endif - -#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM6) -# if CONFIG_STM32L4_ADC1_JTIMTRIG == 4 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T6TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#endif - -#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM8) -# if CONFIG_STM32L4_ADC1_JTIMTRIG == 3 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T8CC4 -# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 4 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO -# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 5 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#endif - -#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM15) -# if CONFIG_STM32L4_ADC1_JTIMTRIG == 4 -# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T15TRGO -# else -# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range" -# endif -#endif - -#ifdef ADC1_JEXTSEL_VALUE +#ifdef ADC1_JEXTCFG_VALUE # define ADC1_HAVE_JEXTCFG 1 -# define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) #endif -#ifdef CONFIG_STM32L4_ADC2 -#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM1) -# if CONFIG_STM32L4_ADC2_JTIMTRIG == 3 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T1CC4 -# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 4 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO -# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 5 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" +#ifdef CONFIG_STM32L4_ADC2_JEXTTRIG +# if CONFIG_STM32L4_ADC2_JEXTTRIG > 0 +# define ADC2_JEXTCFG_VALUE \ + ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC2_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL) # endif -#endif -#endif +#endif /* CONFIG_STM32L4_ADC2_JEXTTRIG */ -#ifdef CONFIG_STM32L4_ADC2 -#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM2) -# if CONFIG_STM32L4_ADC2_JTIMTRIG == 0 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T2CC1 -# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 4 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T2TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC2 -#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM3) -# if CONFIG_STM32L4_ADC2_JTIMTRIG == 0 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T3CC1 -# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 2 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T3CC3 -# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 3 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T3CC4 -# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 4 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T3TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC2 -#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM4) -# if CONFIG_STM32L4_ADC2_JTIMTRIG == 4 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T4TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC2 -#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM6) -# if CONFIG_STM32L4_ADC2_JTIMTRIG == 4 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T6TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC2 -#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM8) -# if CONFIG_STM32L4_ADC2_JTIMTRIG == 3 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T8CC4 -# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 4 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO -# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 5 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC2 -#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM15) -# if CONFIG_STM32L4_ADC2_JTIMTRIG == 4 -# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T15TRGO -# else -# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef ADC2_JEXTSEL_VALUE +#ifdef ADC2_JEXTCFG_VALUE # define ADC2_HAVE_JEXTCFG 1 -# define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) #endif -#ifdef CONFIG_STM32L4_ADC3 -#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM1) -# if CONFIG_STM32L4_ADC3_JTIMTRIG == 3 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T1CC4 -# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 4 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO -# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 5 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" +#ifdef CONFIG_STM32L4_ADC3_JEXTTRIG +# if CONFIG_STM32L4_ADC3_JEXTTRIG > 0 +# define ADC3_JEXTCFG_VALUE \ + ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC3_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL) # endif -#endif -#endif +#endif /* CONFIG_STM32L4_ADC3_JEXTTRIG */ -#ifdef CONFIG_STM32L4_ADC3 -#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM2) -# if CONFIG_STM32L4_ADC3_JTIMTRIG == 0 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T2CC1 -# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 4 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T2TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC3 -#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM3) -# if CONFIG_STM32L4_ADC3_JTIMTRIG == 0 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T3CC1 -# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 2 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T3CC3 -# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 3 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T3CC4 -# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 4 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T3TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC3 -#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM4) -# if CONFIG_STM32L4_ADC3_JTIMTRIG == 4 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T4TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC3 -#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM6) -# if CONFIG_STM32L4_ADC3_JTIMTRIG == 4 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T6TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC3 -#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM8) -# if CONFIG_STM32L4_ADC3_JTIMTRIG == 3 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T8CC4 -# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 4 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO -# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 5 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef CONFIG_STM32L4_ADC3 -#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM15) -# if CONFIG_STM32L4_ADC3_JTIMTRIG == 4 -# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T15TRGO -# else -# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range" -# endif -#endif -#endif - -#ifdef ADC3_JEXTSEL_VALUE +#ifdef ADC3_JEXTCFG_VALUE # define ADC3_HAVE_JEXTCFG 1 -# define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) #endif #if defined(ADC1_HAVE_JEXTCFG) || defined(ADC2_HAVE_JEXTCFG) || \ @@ -1107,7 +462,7 @@ (adc)->llops->regbuf_reg(adc, buffer, len) #define ADC_REG_STARTCONV(adc, state) \ (adc)->llops->reg_startconv(adc, state) -#define ADC_INJ_STARTCONV(adc, state) \ +#define ADC_INJ_STARTCONV(adc, state) \ (adc)->llops->inj_startconv(adc, state) #define ADC_OFFSET_SET(adc, ch, i, o) \ (adc)->llops->offset_set(adc, ch, i, o)