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arch/arm/src/samd5e5: Leverage the SAMD2L2 DMA controller.

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This commit is contained in:
Gregory Nutt 2018-07-29 11:31:26 -06:00
parent a29223c156
commit 754c8493ff
11 changed files with 1745 additions and 25 deletions
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21
arch/arm/include/samd5e5/chip.h
View File

@ -65,6 +65,7 @@
# define SAMD5E5_NTCCOMP 2 /* TC compare */
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NSDHC 2 /* SDHC0-1 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -89,6 +90,7 @@
# define SAMD5E5_NTC 8 /* TC0-TC7 */
# define SAMD5E5_NTCCOMP 2 /* TC compare */
# define SAMD5E5_NSDHC 2 /* SDHC0-1 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -113,6 +115,7 @@
# define SAMD5E5_NTC 8 /* TC0-TC7 */
# define SAMD5E5_NTCCOMP 2 /* TC compare */
# define SAMD5E5_NSDHC 2 /* SDHC0-1 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -137,6 +140,7 @@
# define SAMD5E5_NTC 8 /* TC0-TC7 */
# define SAMD5E5_NTCCOMP 2 /* TC compare */
# define SAMD5E5_NSDHC 2 /* SDHC0-1 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -161,6 +165,7 @@
# define SAMD5E5_NTC 6 /* TC0-TC5 */
# define SAMD5E5_NTCCOMP 2 /* TC compare */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 10 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -185,6 +190,7 @@
# define SAMD5E5_NTC 6 /* TC0-TC5 */
# define SAMD5E5_NTCCOMP 2 /* TC compare */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 10 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -209,6 +215,7 @@
# define SAMD5E5_NTC 6 /* TC0-TC5 */
# define SAMD5E5_NTCCOMP 2 /* TC compare */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 10 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -235,6 +242,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 1 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 10 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -261,6 +269,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 1 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 10 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -287,6 +296,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -313,6 +323,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -339,6 +350,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 10 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -383,6 +395,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 2 /* SDHC0-1 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -409,6 +422,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 2 /* SDHC0-1 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -435,6 +449,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 10 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -461,6 +476,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 10 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -487,6 +503,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 10 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -513,6 +530,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 2 /* SDHC0-1 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -539,6 +557,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 2 /* SDHC0-1 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -565,6 +584,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */
@ -591,6 +611,7 @@
# define SAMD5E5_NTCC24 2 /* TCC 24-bit */
# define SAMD5E5_NTCC16 3 /* TCC 16-bit */
# define SAMD5E5_NSDHC 1 /* SDHC0 */
# define SAMD5E5_NDMACHAN 32 /* 32 DMA channels */
# define SAMD5E5_PCCSIZE 14 /* PCC data size */
# define SAMD5E5_NCCL 4 /* CCL */
# define SAMD5E5_NEVTCHAN 32 /* Event system channels */

3
arch/arm/src/samd5e5/Kconfig
View File

@ -348,8 +348,6 @@ config SAMD5E5_ADC
config SAMD5E5_CMCC
bool "Cortex M Cache Controller (CMCC)"
default n
depends on ARCH_CHIP_SAM4E
config SAMD5E5_DAC
bool "Digital-to-Analog Converter"
default n
@ -358,7 +356,6 @@ config SAMD5E5_DMAC
bool "DMA Controller"
default n
select ARCH_DMA
depends on EXPERIMENTAL
config SAMD5E5_EVSYS
bool "Event System"

4
arch/arm/src/samd5e5/Make.defs
View File

@ -124,6 +124,10 @@ ifeq ($(CONFIG_SAMD5E5_CMCC),y)
CHIP_CSRCS += sam_cmcc.c
endif
ifeq ($(CONFIG_SAMD5E5_DMAC),y)
CHIP_CSRCS += sam_dmac.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += sam_idle.c
endif

31
arch/arm/src/samd5e5/chip/sam_dmac.h
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@ -42,14 +42,12 @@
#include <nuttx/config.h>
#include "chip/sam_memporymap.h"
#include "chip/sam_memorymap.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
#define SAM_DMAC_NCHANNELS 32 /* 32-DMA channels (max) */
/* DMAC register offsets ********************************************************************/
#define SAM_DMAC_CTRL_OFFSET 0x0000 /* Control Register */
@ -68,7 +66,7 @@
#define SAM_DMAC_BASEADDR_OFFSET 0x0034 /* Descriptor Memory Section Base Address Register */
#define SAM_DMAC_WRBADDR_OFFSET 0x0038 /* Write-Back Memory Section Base Address Register */
#define SAM_DMAC_CHAN_OFFSET(n) (0x0040 + ((n) << 4)
#define SAM_DMAC_CHAN_OFFSET(n) (0x0040 + ((n) << 4))
# define SAM_DMAC_CHCTRLA_OFFSET 0x0000 /* Channel Control A Register */
# define SAM_DMAC_CHCTRLB_OFFSET 0x0004 /* Channel Control B Register */
# define SAM_DMAC_CHPRILVL_OFFSET 0x0005 /* Channel Priority Level */
@ -246,11 +244,13 @@
# define DMAC_CHCTRLA_TRIGSRC(n) ((uint32_t)(n) << DMAC_CHCTRLA_TRIGSRC_SHIFT)
#define DMAC_CHCTRLA_TRIGACT_SHIFT (21) /* Bits 20-21: Trigger Action */
#define DMAC_CHCTRLA_TRIGACT_MASK (3 << DMAC_CHCTRLA_TRIGACT_SHIFT)
# define DMAC_CHCTRLA_TRIGACT(n) ((uint32_t)(n) << DMAC_CHCTRLA_TRIGACT_SHIFT)
# define DMAC_CHCTRLA_TRIGACT_BLOCK (0 << DMAC_CHCTRLA_TRIGACT_SHIFT) /* Trigger per block transfer */
# define DMAC_CHCTRLA_TRIGACT_BURST (2 << DMAC_CHCTRLA_TRIGACT_SHIFT) /* Trigger per burst transfer */
# define DMAC_CHCTRLA_TRIGACT_TRANS (3 << DMAC_CHCTRLA_TRIGACT_SHIFT) /* Trigger for each transaction */
#define DMAC_CHCTRLA_BURSTLEN_SHIFT (24) /* Bits 24-27: Burst Length (beats-1) */
#define DMAC_CHCTRLA_BURSTLEN_MASK (15 << DMAC_CHCTRLA_BURSTLEN_SHIFT)
# define DMAC_CHCTRLA_BURSTLEN(n) ((uint32_t)((n) - 1) << DMAC_CHCTRLA_BURSTLEN_SHIFT)
# define DMAC_CHCTRLA_BURSTLEN_1BEAT (0 << DMAC_CHCTRLA_BURSTLEN_SHIFT) /* Single-beat burst */
# define DMAC_CHCTRLA_BURSTLEN_2BEATS (1 << DMAC_CHCTRLA_BURSTLEN_SHIFT) /* 2-beats burst length */
# define DMAC_CHCTRLA_BURSTLEN_3BEATS (2 << DMAC_CHCTRLA_BURSTLEN_SHIFT) /* 3-beats burst length */
@ -269,6 +269,7 @@
# define DMAC_CHCTRLA_BURSTLEN_16BEATS (15 << DMAC_CHCTRLA_BURSTLEN_SHIFT) /* 16-beats burst length */
#define DMAC_CHCTRLA_THRESHOLD_SHIFT (28) /* Bits 28-29: FIFO Threshold (log2 beats) */
#define DMAC_CHCTRLA_THRESHOLD_MASK (3 << DMAC_CHCTRLA_THRESHOLD_SHIFT)
# define DMAC_CHCTRLA_THRESHOLD(n) ((uint32_t)(n) << DMAC_CHCTRLA_THRESHOLD_SHIFT)
# define DMAC_CHCTRLA_THRESHOLD_1BEAT (0 << DMAC_CHCTRLA_THRESHOLD_SHIFT) /* Write after 1 beat */
# define DMAC_CHCTRLA_THRESHOLD_2BEATS (1 << DMAC_CHCTRLA_THRESHOLD_SHIFT) /* Write after 2 beats */
# define DMAC_CHCTRLA_THRESHOLD_4BEATS (2 << DMAC_CHCTRLA_THRESHOLD_SHIFT) /* Write after 3 beats */
@ -285,9 +286,9 @@
#define DMAC_CHCTRLA_TRIGSRC_SERCOM1_RX 0x06 /* Index of SERCOM1 DMA RX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM1_TX 0x07 /* Index of SERCOM1 DMA TX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM2_RX 0x08 /* Index of SERCOM2 DMA RX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM2_tX 0x09 /* Index of SERCOM2 DMA TX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM2_TX 0x09 /* Index of SERCOM2 DMA TX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM3_RX 0x0a /* Index of SERCOM3 DMA RX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM3_tX 0x0b /* Index of SERCOM3 DMA TX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM3_TX 0x0b /* Index of SERCOM3 DMA TX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM4_RX 0x0c /* Index of SERCOM4 DMA RX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM4_TX 0x0d /* Index of SERCOM4 DMA TX trigger */
#define DMAC_CHCTRLA_TRIGSRC_SERCOM5_RX 0x0e /* Index of SERCOM5 DMA RX trigger */
@ -314,9 +315,9 @@
#define DMAC_CHCTRLA_TRIGSRC_TCC2_MC0 0x23 /* Index of TCC2 DMA Match/Compare trigger 0 */
#define DMAC_CHCTRLA_TRIGSRC_TCC2_MC1 0x24 /* Index of TCC2 DMA Match/Compare trigger 1 */
#define DMAC_CHCTRLA_TRIGSRC_TCC2_MC2 0x25 /* Index of TCC2 DMA Match/Compare trigger 2 */
#define DMAC_CHCTRLA_TRIGSRC_TCC2_OVF 0x26 /* TCC3 DMA overflow/underflow/retrigger trigger */
#define DMAC_CHCTRLA_TRIGSRC_TCC2_MC0 0x27 /* Index of TCC3 DMA Match/Compare trigger 0 */
#define DMAC_CHCTRLA_TRIGSRC_TCC2_MC1 0x28 /* Index of TCC3 DMA Match/Compare trigger 1 */
#define DMAC_CHCTRLA_TRIGSRC_TCC3_OVF 0x26 /* TCC3 DMA overflow/underflow/retrigger trigger */
#define DMAC_CHCTRLA_TRIGSRC_TCC3_MC0 0x27 /* Index of TCC3 DMA Match/Compare trigger 0 */
#define DMAC_CHCTRLA_TRIGSRC_TCC3_MC1 0x28 /* Index of TCC3 DMA Match/Compare trigger 1 */
#define DMAC_CHCTRLA_TRIGSRC_TCC4_OVF 0x29 /* TCC4 DMA overflow/underflow/retrigger trigger */
#define DMAC_CHCTRLA_TRIGSRC_TCC4_MC0 0x2a /* Index of TCC4 DMA Match/Compare trigger 0 */
#define DMAC_CHCTRLA_TRIGSRC_TCC4_MC1 0x2b /* Index of TCC4 DMA Match/Compare trigger 1 */
@ -325,10 +326,10 @@
#define DMAC_CHCTRLA_TRIGSRC_TC0_MC1 0x2e /* Index of TC0 DMA Match/Compare trigger 1 */
#define DMAC_CHCTRLA_TRIGSRC_TC1_OVF 0x2f /* TC1 DMA overflow/underflow trigger */
#define DMAC_CHCTRLA_TRIGSRC_TC1_MC0 0x30 /* Index of TC1 DMA Match/Compare trigger 0 */
#define DMAC_CHCTRLA_TRIGSRC_TC2_MC1 0x31 /* Index of TC1 DMA Match/Compare trigger 1 */
#define DMAC_CHCTRLA_TRIGSRC_TC2_OVF 0x32 /* TC1 DMA overflow/underflow trigger */
#define DMAC_CHCTRLA_TRIGSRC_TC2_MC0 0x33 /* Index of TC1 DMA Match/Compare trigger 0 */
#define DMAC_CHCTRLA_TRIGSRC_TC2_MC1 0x34 /* Index of TC1 DMA Match/Compare trigger 1 */
#define DMAC_CHCTRLA_TRIGSRC_TC1_MC1 0x31 /* Index of TC1 DMA Match/Compare trigger 1 */
#define DMAC_CHCTRLA_TRIGSRC_TC2_OVF 0x32 /* TC2 DMA overflow/underflow trigger */
#define DMAC_CHCTRLA_TRIGSRC_TC2_MC0 0x33 /* Index of TC2 DMA Match/Compare trigger 0 */
#define DMAC_CHCTRLA_TRIGSRC_TC2_MC1 0x34 /* Index of TC2 DMA Match/Compare trigger 1 */
#define DMAC_CHCTRLA_TRIGSRC_TC3_OVF 0x35 /* TC3 DMA overflow/underflow trigger */
#define DMAC_CHCTRLA_TRIGSRC_TC3_MC0 0x36 /* Index of TC3 DMA Match/Compare trigger 0 */
#define DMAC_CHCTRLA_TRIGSRC_TC3_MC1 0x37 /* Index of TC3 DMA Match/Compare trigger 1 */
@ -375,11 +376,11 @@
#define DMAC_CHPRILVL_MASK 0x03 /* Channel priority level */
# define DMAC_CHPRILVL(n) ((uint8_t)(n))
/* Channel Event Contol Register */
/* Channel Event Control Register */
#define DMAC_CHEVCTRL_EVACT_SHIFT (0) /* Bits 0-2: Channel event input action */
#define DMAC_CHEVCTRL_EVACT_MASK (7 << DMAC_CHEVCTRL_EVACT_SHIFT)
# define DMAC_CHEVCTRL_EVACT_NOACT (0 << DMAC_CHEVCTRL_EVACT_SHIFT) /* No action
# define DMAC_CHEVCTRL_EVACT_NOACT (0 << DMAC_CHEVCTRL_EVACT_SHIFT) /* No action */
# define DMAC_CHEVCTRL_EVACT_TRIG (1 << DMAC_CHEVCTRL_EVACT_SHIFT) /* Transfer/periodic transfer trigger */
# define DMAC_CHEVCTRL_EVACT_CTRIG (2 << DMAC_CHEVCTRL_EVACT_SHIFT) /* Conditional transfer trigger */
# define DMAC_CHEVCTRL_EVACT_CBLOCK (3 << DMAC_CHEVCTRL_EVACT_SHIFT) /* Conditional block transfer */

1367
arch/arm/src/samd5e5/sam_dmac.c Normal file
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335
arch/arm/src/samd5e5/sam_dmac.h Normal file
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@ -0,0 +1,335 @@
/************************************************************************************
* arch/arm/src/samd5e5/sam_dmac.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_DMAC_H
#define __ARCH_ARM_SRC_SAMD5E5_SAM_DMAC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "chip/sam_dmac.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* DMA ******************************************************************************/
/* Flags used to characterize the desired DMA channel. The naming convention is that
* one side is the peripheral and the other is memory (however, the interface could still
* be used if, for example, both sides were memory although the naming would be awkward)
*/
/* Common characteristics
*
* BEATSIZE - The size of one bus transfer or "beat". 8-, 16-, or 32-bits
* STEPSEL - The STEPSIZE may be applied only to the memory to the peripheral.
* STEPSIZE - When the address is incremented, it is increments by how many "beats"?
* PRIORITY - DMA transfer priority
* RUNSTDBY - DMA runs in standby mode
* BURSTLEN - Burst length.
* THRESHOLD - Threshold at which DMA starts to write (multi-BEAT transfers only)
*/
#define DMACH_FLAG_BEATSIZE_SHIFT (0) /* Bits 0-1: Beat size */
#define DMACH_FLAG_BEATSIZE_MASK (3 << DMACH_FLAG_BEATSIZE_SHIFT)
# define DMACH_FLAG_BEATSIZE_BYTE (0 << DMACH_FLAG_BEATSIZE_SHIFT) /* 8-bit bus transfer */
# define DMACH_FLAG_BEATSIZE_HWORD (1 << DMACH_FLAG_BEATSIZE_SHIFT) /* 16-bit bus transfer */
# define DMACH_FLAG_BEATSIZE_WORD (2 << DMACH_FLAG_BEATSIZE_SHIFT) /* 32-bit bus transfer */
#define DMACH_FLAG_STEPSEL (1 << 2) /* Bit 2: Step selection */
# define DMACH_FLAG_STEPSEL_MEM (0) /* 0=Step size applies to memory */
# define DMACH_FLAG_STEPSEL_PERIPH (1 << 2) /* 1=Step size applies to peripheral */
#define DMACH_FLAG_STEPSIZE_SHIFT (3) /* Bits 3-5: Address increment step */
#define DMACH_FLAG_STEPSIZE_MASK (7 << DMACH_FLAG_STEPSIZE_SHIFT)
# define DMACH_FLAG_STEPSIZE_X1 (0 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */
# define DMACH_FLAG_STEPSIZE_X2 (1 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 2 */
# define DMACH_FLAG_STEPSIZE_X4 (2 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 4 */
# define DMACH_FLAG_STEPSIZE_X8 (3 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 8 */
# define DMACH_FLAG_STEPSIZE_X16 (4 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 16 */
# define DMACH_FLAG_STEPSIZE_X32 (5 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 32 */
# define DMACH_FLAG_STEPSIZE_X64 (6 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 64 */
# define DMACH_FLAG_STEPSIZE_X128 (7 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */
#define DMACH_FLAG_PRIORITY_SHIFT (6) /* Bit 6-7: Arbitration priority */
#define DMACH_FLAG_PRIORITY_MASK (3 << DMACH_FLAG_PRIORITY_SHIFT)
# define DMACH_FLAG_PRIORITY(n) ((uint32_t)(n) << DMACH_FLAG_PRIORITY_SHIFT)
#define DMACH_FLAG_RUNINSTDBY (1 << 8) /* Bit 8: Run in standby */
#define DMACH_FLAG_BURSTLEN_SHIFT (9) /* Bits 9-12: Burst length */
#define DMACH_FLAG_BURSTLEN_MASK (15 << DMACH_FLAG_BURSTLEN_SHIFT)
# define DMACH_FLAG_BURSTLEN(n) ((uint32_t)(n) << DMACH_FLAG_BURSTLEN_SHIFT) /* n=1-16 */
#define DMACH_FLAG_THRESHOLD_SHIFT (13) /* Bits 13-14: Threshold */
#define DMACH_FLAG_THRESHOLD_MASK (15 << DMACH_FLAG_THRESHOLD_SHIFT)
# define DMACH_FLAG_THRESHOLD_1BEAT (0 << DMACH_FLAG_THRESHOLD_SHIFT) /* Write after 1 beat */
# define DMACH_FLAG_THRESHOLD_2BEATS (1 << DMACH_FLAG_THRESHOLD_SHIFT) /* Write after 2 beats */
# define DMACH_FLAG_THRESHOLD_4BEATS (2 << DMACH_FLAG_THRESHOLD_SHIFT) /* Write after 3 beats */
# define DMACH_FLAG_THRESHOLD_8BEATS (3 << DMACH_FLAG_THRESHOLD_SHIFT) /* Write after 8 beats */
/* Peripheral endpoint characteristics.
*
* PERIPH_TRIGSRC - The TX ID of the peripheral that provides the DMA trigger. This
* is one of the DMAC_CHCTRLA_TRIGSRC_*[_TX] definitions. This trigger source
* is selected when sam_dmatxsetup() is called.
* PERIPH_TRIGACT - Trigger action
* PERIPH_INCREMENT - Indicates the that peripheral address should be incremented on
* each "beat"
*/
#define DMACH_FLAG_PERIPH_TRIGSRC_SHIFT (15) /* Bits 15-21: See DMAC_CHCTRLA_TRIGSRC_* */
#define DMACH_FLAG_PERIPH_TRIGSRC_MASK (0x7f << DMACH_FLAG_PERIPH_TRIGSRC_SHIFT)
# define DMACH_FLAG_PERIPH_TRIGSRC(n) ((uint32_t)(n) << DMACH_FLAG_PERIPH_TRIGSRC_SHIFT)
#define DMACH_FLAG_PERIPH_TRIGACT_SHIFT (22) /* Bits 22-23: Tx trigger action */
#define DMACH_FLAG_PERIPH_TRIGACT_MASK (3 << DMACH_FLAG_PERIPH_TRIGACT_SHIFT)
# define DMACH_FLAG_PERIPH_TRIGACT_BLOCK (0 << DMACH_FLAG_PERIPH_TRIGACT_SHIFT) /* Trigger per block transfer */
# define DMACH_FLAG_PERIPH_TRIGACT_BURST (2 << DMACH_FLAG_PERIPH_TRIGACT_SHIFT) /* Trigger per burst transfer */
# define DMACH_FLAG_PERIPH_TRIGACT_TRANS (3 << DMACH_FLAG_PERIPH_TRIGACT_SHIFT) /* Trigger for each transaction */
#define DMACH_FLAG_PERIPH_INCREMENT (1 << 24) /* Bit 24: Autoincrement peripheral address */
/* Memory endpoint characteristics
*
* MEM_INCREMENT - Indicates the that memory address should be incremented on each
* "beat"
*/
#define DMACH_FLAG_MEM_INCREMENT (1 << 25) /* Bit 25: Autoincrement memory address */
/* Bits 26-31: Not used */
/************************************************************************************
* Public Types
************************************************************************************/
typedef FAR void *DMA_HANDLE;
typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
#ifdef CONFIG_DEBUG_DMA_INFO
struct sam_dmaregs_s
{
uint8_t chan; /* Channel index */
/* DMAC Registers */
uint8_t crcstatus; /* CRC Status Register */
uint8_t dbgctrl; /* Debug Control Register */
uint8_t chid; /* Channel ID Register */
uint8_t chctrlb; /* Channel Control B Register */
uint8_t chpirlvl; /* Channel Priority Level */
uint8_t chevctrl; /* Channel Event Control Register */
uint8_t chintflag; /* Channel Interrupt Flag Status and Clear Register */
uint8_t chstatus; /* Channel Status Register */
uint16_t ctrl; /* Control Register */
uint16_t crcctrl; /* CRC Control Register */
uint16_t intpend; /* Interrupt Pending Register */
uint32_t crcdatain; /* CRC Data Input Register */
uint32_t crcchksum; /* CRC Checksum Register */
uint32_t swtrigctrl; /* Software Trigger Control Register */
uint32_t prictrl0; /* Priority Control 0 Register */
uint32_t intstatus; /* Interrupt Status Register */
uint32_t busych; /* Busy Channels Register */
uint32_t pendch; /* Pending Channels Register */
uint32_t active; /* Active Channels and Levels Register */
uint32_t baseaddr; /* Descriptor Memory Section Base Address Register */
uint32_t wrbaddr; /* Write-Back Memory Section Base Address Register */
uint32_t chctrla; /* Channel Control A Register */
};
#endif
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: sam_dmachannel
*
* Description:
* Allocate a DMA channel. This function sets aside a DMA channel and gives the
* caller exclusive access to the DMA channel.
*
* The naming convention in all of the DMA interfaces is that one side is the
* 'peripheral' and the other is 'memory'. However, the interface could still be
* used if, for example, both sides were memory although the naming would be
* awkward.
*
* Returned Value:
* If a DMA channel if the required FIFO size is available, this function returns
* a non-NULL, void* DMA channel handle. NULL is returned on any failure.
*
************************************************************************************/
DMA_HANDLE sam_dmachannel(uint32_t txflags, uint32_t rxflags);
/************************************************************************************
* Name: sam_dmaconfig
*
* Description:
* There are two channel usage models: (1) The channel is allocated and
* configured in one step. This is the typical case where a DMA channel performs
* a constant role. The alternative is (2) where the DMA channel is reconfigured
* on the fly. In this case, the chflags provided to sam_dmachannel are not used
* and sam_dmaconfig() is called before each DMA to configure the DMA channel
* appropriately.
*
* Returned Value:
* None
*
************************************************************************************/
void sam_dmaconfig(DMA_HANDLE handle, uint32_t txflags, uint32_t rxflags);
/************************************************************************************
* Name: sam_dmafree
*
* Description:
* Release a DMA channel. NOTE: The 'handle' used in this argument must NEVER be
* used again until sam_dmachannel() is called again to re-gain a valid handle.
*
* Returned Value:
* None
*
************************************************************************************/
void sam_dmafree(DMA_HANDLE handle);
/************************************************************************************
* Name: sam_dmatxsetup
*
* Description:
* Configure DMA for transmit of one buffer (memory to peripheral). This function
* may be called multiple times to handle large and/or non-contiguous transfers.
* Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the
* same transfer, however.
*
************************************************************************************/
int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t nbytes);
/************************************************************************************
* Name: sam_dmarxsetup
*
* Description:
* Configure DMA for receipt of one buffer (peripheral to memory). This function
* may be called multiple times to handle large and/or non-contiguous transfers.
* Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the
* same transfer, however.
*
************************************************************************************/
int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t nbytes);
/************************************************************************************
* Name: sam_dmastart
*
* Description:
* Start the DMA transfer
*
************************************************************************************/
int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
/************************************************************************************
* Name: sam_dmastop
*
* Description:
* Cancel the DMA. After sam_dmastop() is called, the DMA channel is
* reset and sam_dmarx/txsetup() must be called before sam_dmastart() can be
* called again
*
************************************************************************************/
void sam_dmastop(DMA_HANDLE handle);
/************************************************************************************
* Name: sam_dmasample
*
* Description:
* Sample DMA register contents
*
************************************************************************************/
#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
#else
# define sam_dmasample(handle,regs)
#endif
/************************************************************************************
* Name: sam_dmadump
*
* Description:
* Dump previously sampled DMA register contents
*
************************************************************************************/
#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
const char *msg);
#else
# define sam_dmadump(handle,regs,msg)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_DMAC_H */

5
arch/arm/src/samd5e5/sam_i2c_master.c
View File

@ -1182,9 +1182,8 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency)
i2c_pad_configure(priv);
ctrla =
I2C_CTRLA_MODE_MASTER | I2C_CTRLA_RUNSTDBY | I2C_CTRLA_SPEED_FAST |
I2C_CTRLA_SDAHOLD_450NS | priv->attr->muxconfig;
ctrla = I2C_CTRLA_MODE_MASTER | I2C_CTRLA_RUNSTDBY | I2C_CTRLA_SPEED_FAST |
I2C_CTRLA_SDAHOLD_450NS | priv->attr->muxconfig;
i2c_putreg32(priv, ctrla, SAM_I2C_CTRLA_OFFSET);
i2c_wait_synchronization(priv);

1
arch/arm/src/samd5e5/sam_idle.c
View File

@ -46,7 +46,6 @@
#include <nuttx/irq.h>
#include "chip.h"
#include "up_internal.h"
/****************************************************************************

1
arch/arm/src/samd5e5/sam_serial.c
View File

@ -58,7 +58,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "chip.h"
#include "sam_config.h"
#include "sam_usart.h"
#include "sam_lowputc.h"

1
arch/arm/src/samd5e5/sam_usart.h
View File

@ -48,7 +48,6 @@
#include <arch/chip/chip.h>
#include "up_arch.h"
#include "chip.h"
#include "chip/sam_usart.h"
#include "sam_config.h"

1
arch/arm/src/samd5e5/sam_userspace.h
View File

@ -48,7 +48,6 @@
#include <stdbool.h>
#include "up_internal.h"
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions