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ARMv7-A: Need to set bits in the ICDDCR to enable forwarding of interrupts

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This commit is contained in:
Gregory Nutt 2016-03-31 09:18:55 -06:00
parent 12064b276a
commit 756e6050e4
2 changed files with 19 additions and 4 deletions
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13
arch/arm/src/armv7-a/arm_gicv2.c
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@ -169,6 +169,7 @@ void arm_gic0_initialize(void)
void arm_gic_initialize(void) void arm_gic_initialize(void)
{ {
uint32_t iccicr; uint32_t iccicr;
uint32_t icddcr;
/* Initialize PPIs. The following steps need to be done by all CPUs */ /* Initialize PPIs. The following steps need to be done by all CPUs */
@ -302,6 +303,7 @@ void arm_gic_initialize(void)
*/ */
iccicr |= GIC_ICCICR_ENABLE; iccicr |= GIC_ICCICR_ENABLE;
icddcr = GIC_ICDDCR_ENABLE;
#elif defined(CONFIG_ARCH_TRUSTZONE_SECURE) #elif defined(CONFIG_ARCH_TRUSTZONE_SECURE)
/* Enable the Group 0 interrupts, FIQEn and disable Group 0/1 /* Enable the Group 0 interrupts, FIQEn and disable Group 0/1
@ -311,6 +313,7 @@ void arm_gic_initialize(void)
iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_FIQBYPDISGRP0 | iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_FIQBYPDISGRP0 |
GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 |
GIC_ICCICRS_IRQBYPDISGRP1); GIC_ICCICRS_IRQBYPDISGRP1);
icddcr = GIC_ICDDCR_ENABLEGRP0;
#elif defined(CONFIG_ARCH_TRUSTZONE_BOTH) #elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
/* Enable the Group 0/1 interrupts, FIQEn and disable Group 0/1 /* Enable the Group 0/1 interrupts, FIQEn and disable Group 0/1
@ -320,16 +323,18 @@ void arm_gic_initialize(void)
iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 | iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 |
GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 |
GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1); GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1);
icddcr = (GIC_ICDDCR_ENABLEGRP0 | GIC_ICDDCR_ENABLEGRP1);
#else /* defined(CONFIG_ARCH_TRUSTZONE_NONSECURE) */ #else /* defined(CONFIG_ARCH_TRUSTZONE_NONSECURE) */
/* Enable the Group 1 interrupts and disable Group 1 bypass. */ /* Enable the Group 1 interrupts and disable Group 1 bypass. */
iccicr |= (GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 | iccicr |= (GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 |
GIC_ICCICRU_IRQBYPDISGRP1); GIC_ICCICRU_IRQBYPDISGRP1);
icddcr = GIC_ICDDCR_ENABLEGRP1;
#endif #endif
/* Write the final ICCICR value */ /* Write the final ICCICR value to enable the GIC. */
putreg32(iccicr, GIC_ICCICR); putreg32(iccicr, GIC_ICCICR);
@ -342,6 +347,12 @@ void arm_gic_initialize(void)
# warning Missing logic # warning Missing logic
#endif #endif
/* Write the ICDDCR value to enable the forwarding of interrupt by the
* distributor.
*/
putreg32(icddcr, GIC_ICDDCR);
} }
/**************************************************************************** /****************************************************************************

10
arch/arm/src/armv7-a/gic.h
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@ -327,10 +327,14 @@
#define GIC_ICCIDR_PARTNO_MASK (0xfff << GIC_ICCIDR_PARTNO_SHIFT) #define GIC_ICCIDR_PARTNO_MASK (0xfff << GIC_ICCIDR_PARTNO_SHIFT)
/* Distributor Registers */ /* Distributor Registers */
/* Distributor Control Register */ /* Distributor Control Register -- without security extensions */
#define GIC_ICDDCR_NONSECENAB (1 << 0) /* Bit 0: Enable distributor for Non-secure interrupts */ #define GIC_ICDDCR_ENABLE (1 << 0) /* Bit 0: Enable forwarding of interrupts */
#define GIC_ICDDCR_SECENABLE (1 << 1) /* Bit 1: Enable distributor for Secure interrupts */ /* Bits 1-31: Reserved */
/* Distributor Control Register -- with security extensions */
#define GIC_ICDDCR_ENABLEGRP0 (1 << 0) /* Bit 0: Enable forwarding of Group 0 interrupts */
#define GIC_ICDDCR_ENABLEGRP1 (1 << 1) /* Bit 1: Enable forwarding of Group 1 interrupts */
/* Bits 2-31: Reserved */ /* Bits 2-31: Reserved */
/* Interrupt Controller Type Register */ /* Interrupt Controller Type Register */